| Message ID | ac6a19d43a6d36ae6f7cab99a1ac25d2515339ad.1503249785.git.balaton@eik.bme.hu |
|---|---|
| State | New |
| Headers | show |
Hi Zoltan, On 08/20/2017 02:23 PM, BALATON Zoltan wrote: > These registers are present in 440 SoCs (and maybe in others too) and > U-Boot accesses them when printing register info. We don't emulate > these but add them to avoid crashing when they are read or written. Your code isn't incorrect but it doesn't sound the right way to fix your problem. Your firmware shouldn't *crash* on unimplemented dcr. Looking at ppc_dcr_read() I see that *valp isn't updated on unimp dcrn, while the dcr_read_plb() callback you are using return 0 on unimp (with an "avoid gcc warning" misleading comment). What is the hardware behavior on implemented dcr? return 0? In that case this should be used in ppc_dcr_read(), also adding some qemu_log_mask(LOG_UNIMP,...) log entry there. Regards, Phil. > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > hw/ppc/ppc405_uc.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index e621d0a..8e58065 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, > /*****************************************************************************/ > /* Peripheral local bus arbitrer */ > enum { > - PLB0_BESR = 0x084, > - PLB0_BEAR = 0x086, > - PLB0_ACR = 0x087, > + PLB3A0_ACR = 0x077, > + PLB4A0_ACR = 0x081, > + PLB0_BESR = 0x084, > + PLB0_BEAR = 0x086, > + PLB0_ACR = 0x087, > + PLB4A1_ACR = 0x089, > }; > > typedef struct ppc4xx_plb_t ppc4xx_plb_t; > @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) > ppc4xx_plb_t *plb; > > plb = g_malloc0(sizeof(ppc4xx_plb_t)); > + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); > + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); > qemu_register_reset(ppc4xx_plb_reset, plb); > } > >
On Sun, 20 Aug 2017, Philippe Mathieu-Daudé wrote: > On 08/20/2017 02:23 PM, BALATON Zoltan wrote: >> These registers are present in 440 SoCs (and maybe in others too) and >> U-Boot accesses them when printing register info. We don't emulate >> these but add them to avoid crashing when they are read or written. > > Your code isn't incorrect but it doesn't sound the right way to fix your > problem. Your firmware shouldn't *crash* on unimplemented dcr. The firmware shouldn't crash but it's just isn't written expecting missing DCRs (and we aim to run the board's patched U-Boot version as it is because it is needed by the OSes running on the board). QEMU makes it crash by raising an exception for unknown DCRs, I think in target/ppc/timebase_helper.c:150 > Looking at ppc_dcr_read() I see that *valp isn't updated on unimp dcrn, while > the dcr_read_plb() callback you are using return 0 on unimp (with an "avoid > gcc warning" misleading comment). > > What is the hardware behavior on implemented dcr? return 0? In that case this > should be used in ppc_dcr_read(), also adding some > qemu_log_mask(LOG_UNIMP,...) log entry there. Of course the right way would be to emulate what these registers do on hardware but I don't know what the hardware does and for a lot of DCRs the firmware just writes some values to initialise the hadware which is not needed on QEMU so we can just do read zero, ignore writes which we are doing here. (That's what I was trying to say in the commit message too.) Actually these registers aren't even used by the firmware, only included in register dumps so this should be safe until we find something tries to use it. > Regards, > > Phil. > >> >> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> >> --- >> hw/ppc/ppc405_uc.c | 12 +++++++++--- >> 1 file changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c >> index e621d0a..8e58065 100644 >> --- a/hw/ppc/ppc405_uc.c >> +++ b/hw/ppc/ppc405_uc.c >> @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, >> ppc4xx_bd_info_t *bd, >> /*****************************************************************************/ >> /* Peripheral local bus arbitrer */ >> enum { >> - PLB0_BESR = 0x084, >> - PLB0_BEAR = 0x086, >> - PLB0_ACR = 0x087, >> + PLB3A0_ACR = 0x077, >> + PLB4A0_ACR = 0x081, >> + PLB0_BESR = 0x084, >> + PLB0_BEAR = 0x086, >> + PLB0_ACR = 0x087, >> + PLB4A1_ACR = 0x089, >> }; >> typedef struct ppc4xx_plb_t ppc4xx_plb_t; >> @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) >> ppc4xx_plb_t *plb; >> plb = g_malloc0(sizeof(ppc4xx_plb_t)); >> + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); >> + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> qemu_register_reset(ppc4xx_plb_reset, plb); >> } >> > >
On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote: > These registers are present in 440 SoCs (and maybe in others too) and > U-Boot accesses them when printing register info. We don't emulate > these but add them to avoid crashing when they are read or written. > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> I'm ok with stub implementation, but I'm a bit uncomfortable with registering these DCRs unconditionally rather than just on the chips that actually implement them. > --- > hw/ppc/ppc405_uc.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index e621d0a..8e58065 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, > /*****************************************************************************/ > /* Peripheral local bus arbitrer */ > enum { > - PLB0_BESR = 0x084, > - PLB0_BEAR = 0x086, > - PLB0_ACR = 0x087, > + PLB3A0_ACR = 0x077, > + PLB4A0_ACR = 0x081, > + PLB0_BESR = 0x084, > + PLB0_BEAR = 0x086, > + PLB0_ACR = 0x087, > + PLB4A1_ACR = 0x089, > }; > > typedef struct ppc4xx_plb_t ppc4xx_plb_t; > @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) > ppc4xx_plb_t *plb; > > plb = g_malloc0(sizeof(ppc4xx_plb_t)); > + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); > ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); > + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); > qemu_register_reset(ppc4xx_plb_reset, plb); > } >
On Sun, Aug 20, 2017 at 06:58:52PM -0300, Philippe Mathieu-Daudé wrote: > Hi Zoltan, > > On 08/20/2017 02:23 PM, BALATON Zoltan wrote: > > These registers are present in 440 SoCs (and maybe in others too) and > > U-Boot accesses them when printing register info. We don't emulate > > these but add them to avoid crashing when they are read or written. > > Your code isn't incorrect but it doesn't sound the right way to fix your > problem. Your firmware shouldn't *crash* on unimplemented dcr. > > Looking at ppc_dcr_read() I see that *valp isn't updated on unimp dcrn, > while the dcr_read_plb() callback you are using return 0 on unimp (with an > "avoid gcc warning" misleading comment). Hrm.. I thought accessing a bad DCR led to a 0x700 exception rather than just returning a dummy value. > > What is the hardware behavior on implemented dcr? return 0? In that case > this should be used in ppc_dcr_read(), also adding some > qemu_log_mask(LOG_UNIMP,...) log entry there. > > Regards, > > Phil. > > > > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > > --- > > hw/ppc/ppc405_uc.c | 12 +++++++++--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > > index e621d0a..8e58065 100644 > > --- a/hw/ppc/ppc405_uc.c > > +++ b/hw/ppc/ppc405_uc.c > > @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, > > /*****************************************************************************/ > > /* Peripheral local bus arbitrer */ > > enum { > > - PLB0_BESR = 0x084, > > - PLB0_BEAR = 0x086, > > - PLB0_ACR = 0x087, > > + PLB3A0_ACR = 0x077, > > + PLB4A0_ACR = 0x081, > > + PLB0_BESR = 0x084, > > + PLB0_BEAR = 0x086, > > + PLB0_ACR = 0x087, > > + PLB4A1_ACR = 0x089, > > }; > > typedef struct ppc4xx_plb_t ppc4xx_plb_t; > > @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) > > ppc4xx_plb_t *plb; > > plb = g_malloc0(sizeof(ppc4xx_plb_t)); > > + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); > > ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); > > + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > qemu_register_reset(ppc4xx_plb_reset, plb); > > } > > >
On Wed, 23 Aug 2017, David Gibson wrote: > On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote: >> These registers are present in 440 SoCs (and maybe in others too) and >> U-Boot accesses them when printing register info. We don't emulate >> these but add them to avoid crashing when they are read or written. >> >> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > > I'm ok with stub implementation, but I'm a bit uncomfortable with > registering these DCRs unconditionally rather than just on the chips > that actually implement them. Problem is that I don't know which chips have these. I can only try to find out from the U-Boot sources where a comment says these are common registers for all SoCs (in u-boot/arch/powerpc/include/asm/ppc4xx.h: http://git.denx.de/?p=u-boot.git;a=blob;f=arch/powerpc/include/asm/ppc4xx.h;h=45ff5dbacd9243e83bb2f6551e2dd64a7e544bf5;hb=e2351d5cf1e97408b4c52bafeaa85e0ca85c920c while looking for this I've just noticed that u-boot has removed ppc440 support just before 2017.07-rc3 so this is the last version that still has these files). So if that's true it should be OK for 405 too. >> --- >> hw/ppc/ppc405_uc.c | 12 +++++++++--- >> 1 file changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c >> index e621d0a..8e58065 100644 >> --- a/hw/ppc/ppc405_uc.c >> +++ b/hw/ppc/ppc405_uc.c >> @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, >> /*****************************************************************************/ >> /* Peripheral local bus arbitrer */ >> enum { >> - PLB0_BESR = 0x084, >> - PLB0_BEAR = 0x086, >> - PLB0_ACR = 0x087, >> + PLB3A0_ACR = 0x077, >> + PLB4A0_ACR = 0x081, >> + PLB0_BESR = 0x084, >> + PLB0_BEAR = 0x086, >> + PLB0_ACR = 0x087, >> + PLB4A1_ACR = 0x089, >> }; >> >> typedef struct ppc4xx_plb_t ppc4xx_plb_t; >> @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) >> ppc4xx_plb_t *plb; >> >> plb = g_malloc0(sizeof(ppc4xx_plb_t)); >> + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); >> ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); >> + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); >> qemu_register_reset(ppc4xx_plb_reset, plb); >> } >> > >
On Wed, Aug 23, 2017 at 12:16:24PM +0200, BALATON Zoltan wrote: > On Wed, 23 Aug 2017, David Gibson wrote: > > On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote: > > > These registers are present in 440 SoCs (and maybe in others too) and > > > U-Boot accesses them when printing register info. We don't emulate > > > these but add them to avoid crashing when they are read or written. > > > > > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > > > > I'm ok with stub implementation, but I'm a bit uncomfortable with > > registering these DCRs unconditionally rather than just on the chips > > that actually implement them. > > Problem is that I don't know which chips have these. I can only try to find > out from the U-Boot sources where a comment says these are common registers > for all SoCs (in u-boot/arch/powerpc/include/asm/ppc4xx.h: > > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/powerpc/include/asm/ppc4xx.h;h=45ff5dbacd9243e83bb2f6551e2dd64a7e544bf5;hb=e2351d5cf1e97408b4c52bafeaa85e0ca85c920c > > while looking for this I've just noticed that u-boot has removed ppc440 > support just before 2017.07-rc3 so this is the last version that still has > these files). So if that's true it should be OK for 405 too. Ok, just to make sure I'm understanding correctly are you saying: 1) You suspect these registers were actually on all versions of the device, they just weren't implemented until now. or 2) The registers are definitely on only some versions of the device, but you're not sure which ones > > > > --- > > > hw/ppc/ppc405_uc.c | 12 +++++++++--- > > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > > > index e621d0a..8e58065 100644 > > > --- a/hw/ppc/ppc405_uc.c > > > +++ b/hw/ppc/ppc405_uc.c > > > @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, > > > /*****************************************************************************/ > > > /* Peripheral local bus arbitrer */ > > > enum { > > > - PLB0_BESR = 0x084, > > > - PLB0_BEAR = 0x086, > > > - PLB0_ACR = 0x087, > > > + PLB3A0_ACR = 0x077, > > > + PLB4A0_ACR = 0x081, > > > + PLB0_BESR = 0x084, > > > + PLB0_BEAR = 0x086, > > > + PLB0_ACR = 0x087, > > > + PLB4A1_ACR = 0x089, > > > }; > > > > > > typedef struct ppc4xx_plb_t ppc4xx_plb_t; > > > @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) > > > ppc4xx_plb_t *plb; > > > > > > plb = g_malloc0(sizeof(ppc4xx_plb_t)); > > > + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > > + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > > ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > > ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); > > > ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); > > > + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); > > > qemu_register_reset(ppc4xx_plb_reset, plb); > > > } > > > > > > > >
On Thu, 24 Aug 2017, David Gibson wrote: > On Wed, Aug 23, 2017 at 12:16:24PM +0200, BALATON Zoltan wrote: >> On Wed, 23 Aug 2017, David Gibson wrote: >>> On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote: >>>> These registers are present in 440 SoCs (and maybe in others too) and >>>> U-Boot accesses them when printing register info. We don't emulate >>>> these but add them to avoid crashing when they are read or written. >>>> >>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> >>> >>> I'm ok with stub implementation, but I'm a bit uncomfortable with >>> registering these DCRs unconditionally rather than just on the chips >>> that actually implement them. >> >> Problem is that I don't know which chips have these. I can only try to find >> out from the U-Boot sources where a comment says these are common registers >> for all SoCs (in u-boot/arch/powerpc/include/asm/ppc4xx.h: >> >> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/powerpc/include/asm/ppc4xx.h;h=45ff5dbacd9243e83bb2f6551e2dd64a7e544bf5;hb=e2351d5cf1e97408b4c52bafeaa85e0ca85c920c >> >> while looking for this I've just noticed that u-boot has removed ppc440 >> support just before 2017.07-rc3 so this is the last version that still has >> these files). So if that's true it should be OK for 405 too. > > Ok, just to make sure I'm understanding correctly are you saying: > > 1) You suspect these registers were actually on all versions of the > device, they just weren't implemented until now. That's what I suspect from the comment in the file quoted above but I don't have any other evidence. > or > > 2) The registers are definitely on only some versions of the device, > but you're not sure which ones I don't know any of these devices very well and have no definitive sources to confirm so I'm not sure but I think these should be on all the versions (at least on all three that QEMU emulates, namely 405, 440 and 460ex). >>>> --- >>>> hw/ppc/ppc405_uc.c | 12 +++++++++--- >>>> 1 file changed, 9 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c >>>> index e621d0a..8e58065 100644 >>>> --- a/hw/ppc/ppc405_uc.c >>>> +++ b/hw/ppc/ppc405_uc.c >>>> @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, >>>> /*****************************************************************************/ >>>> /* Peripheral local bus arbitrer */ >>>> enum { >>>> - PLB0_BESR = 0x084, >>>> - PLB0_BEAR = 0x086, >>>> - PLB0_ACR = 0x087, >>>> + PLB3A0_ACR = 0x077, >>>> + PLB4A0_ACR = 0x081, >>>> + PLB0_BESR = 0x084, >>>> + PLB0_BEAR = 0x086, >>>> + PLB0_ACR = 0x087, >>>> + PLB4A1_ACR = 0x089, >>>> }; >>>> >>>> typedef struct ppc4xx_plb_t ppc4xx_plb_t; >>>> @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) >>>> ppc4xx_plb_t *plb; >>>> >>>> plb = g_malloc0(sizeof(ppc4xx_plb_t)); >>>> + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >>>> + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >>>> ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); >>>> ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); >>>> ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); >>>> + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); >>>> qemu_register_reset(ppc4xx_plb_reset, plb); >>>> } >>>> >>> >>> >> > >
On Thu, Aug 24, 2017 at 10:28:15PM +0200, BALATON Zoltan wrote: > On Thu, 24 Aug 2017, David Gibson wrote: > > On Wed, Aug 23, 2017 at 12:16:24PM +0200, BALATON Zoltan wrote: > > > On Wed, 23 Aug 2017, David Gibson wrote: > > > > On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote: > > > > > These registers are present in 440 SoCs (and maybe in others too) and > > > > > U-Boot accesses them when printing register info. We don't emulate > > > > > these but add them to avoid crashing when they are read or written. > > > > > > > > > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > > > > > > > > I'm ok with stub implementation, but I'm a bit uncomfortable with > > > > registering these DCRs unconditionally rather than just on the chips > > > > that actually implement them. > > > > > > Problem is that I don't know which chips have these. I can only try to find > > > out from the U-Boot sources where a comment says these are common registers > > > for all SoCs (in u-boot/arch/powerpc/include/asm/ppc4xx.h: > > > > > > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/powerpc/include/asm/ppc4xx.h;h=45ff5dbacd9243e83bb2f6551e2dd64a7e544bf5;hb=e2351d5cf1e97408b4c52bafeaa85e0ca85c920c > > > > > > while looking for this I've just noticed that u-boot has removed ppc440 > > > support just before 2017.07-rc3 so this is the last version that still has > > > these files). So if that's true it should be OK for 405 too. > > > > Ok, just to make sure I'm understanding correctly are you saying: > > > > 1) You suspect these registers were actually on all versions of the > > device, they just weren't implemented until now. > > That's what I suspect from the comment in the file quoted above but I don't > have any other evidence. > > > or > > > > 2) The registers are definitely on only some versions of the device, > > but you're not sure which ones > > I don't know any of these devices very well and have no definitive sources > to confirm so I'm not sure but I think these should be on all the versions > (at least on all three that QEMU emulates, namely 405, 440 and > 460ex). Ah, ok. I couldn't seem to find any relevant manuals either. Ok, given the scanty evidence we have I'm ok with including the registers always, as proposed.
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e621d0a..8e58065 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, /*****************************************************************************/ /* Peripheral local bus arbitrer */ enum { - PLB0_BESR = 0x084, - PLB0_BEAR = 0x086, - PLB0_ACR = 0x087, + PLB3A0_ACR = 0x077, + PLB4A0_ACR = 0x081, + PLB0_BESR = 0x084, + PLB0_BEAR = 0x086, + PLB0_ACR = 0x087, + PLB4A1_ACR = 0x089, }; typedef struct ppc4xx_plb_t ppc4xx_plb_t; @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env) ppc4xx_plb_t *plb; plb = g_malloc0(sizeof(ppc4xx_plb_t)); + ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); + ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); + ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); qemu_register_reset(ppc4xx_plb_reset, plb); }
These registers are present in 440 SoCs (and maybe in others too) and U-Boot accesses them when printing register info. We don't emulate these but add them to avoid crashing when they are read or written. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- hw/ppc/ppc405_uc.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)