Message ID | 1498033898-15650-6-git-send-email-stefanc@malvell.com |
---|---|
State | Superseded |
Delegated to: | Stefan Roese |
Headers | show |
On Wed, Jun 21, 2017 at 3:31 AM, <stefanc@malvell.com> wrote: > From: Stefan Chulski <stefanc@marvell.com> > > U-boot use single physical tx queue with size 16 descriptors. > So aggregated tx queue size should be equal to physical tx queue > and cpu descriptor chunk(number of descriptors delivered from > physical tx queue to aggregated tx queue by one chunk) shouldn't be > larger than physical tx queue. > > Fix: > Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as > physical TXQ. > > Change-Id: I22c759a9bcf533ecddbdc495cd48d72e8761764e Drop internal tags in whole series. > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > Reviewed-on: http://vgitil04.il.marvell.com:8080/39964 > Tested-by: iSoC Platform CI <ykjenk@marvell.com> > Reviewed-by: Nadav Haklai <nadavh@marvell.com> > Reviewed-on: http://vgitil04.il.marvell.com:8080/39658 > Reviewed-by: Igal Liberman <igall@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index af3c3ef..901e9d8 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -623,10 +623,10 @@ enum mv_netc_lanes { #define MVPP2_MAX_TXD 16 /* Amount of Tx descriptors that can be reserved at once by CPU */ -#define MVPP2_CPU_DESC_CHUNK 64 +#define MVPP2_CPU_DESC_CHUNK 16 /* Max number of Tx descriptors in each aggregated queue */ -#define MVPP2_AGGR_TXQ_SIZE 256 +#define MVPP2_AGGR_TXQ_SIZE 16 /* Descriptor aligned size */ #define MVPP2_DESC_ALIGNED_SIZE 32