Message ID | 1497868601-30227-3-git-send-email-w.egorov@phytec.de |
---|---|
State | Accepted |
Commit | bafcf2db4176940953a96339025d7b06e96cb22e |
Delegated to: | Philipp Tomsich |
Headers | show |
> The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. > The module can be connected to different carrier boards. > It can be also equipped with different RAM, SPI flash and eMMC variants. > The Rapid Development Kit option is using the following setup: > > - 1 GB DDR3 RAM (2 Banks) > - 1x 4 KB EEPROM > - DP83867 Gigabit Ethernet PHY > - 16 MB SPI Flash > - 4 GB eMMC Flash > > Add basic support for the PCM-947 carrier board, a RK3288 based development > board made by PHYTEC. This board works in a combination with > the phyCORE-RK3288 System on Module. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > Reviewed-by: Simon Glass <sjg@chromium.org> > --- > Changes in v4: > - Use of_machine_is_compatible() > - Wrap phycore_init()/of_machine_is_compatible() with CONFIG_SPL_OF_PLATDATA > and CONFIG_SPL_POWER_SUPPORT. Needed because of_machine_is_compatible() and > rk818_spl_configure_*() is not available with all rk3288 board configs. > - Added Reviewed-by: Simon Glass <sjg@chromium.org> > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3288-phycore-rdk.dts | 294 ++++++++++++++++ > arch/arm/dts/rk3288-phycore-som.dtsi | 506 +++++++++++++++++++++++++++ > arch/arm/mach-rockchip/rk3288-board-spl.c | 40 +++ > arch/arm/mach-rockchip/rk3288/Kconfig | 10 + > board/phytec/phycore_rk3288/Kconfig | 15 + > board/phytec/phycore_rk3288/MAINTAINERS | 6 + > board/phytec/phycore_rk3288/Makefile | 8 + > board/phytec/phycore_rk3288/phycore-rk3288.c | 8 + > configs/phycore-rk3288_defconfig | 70 ++++ > include/configs/phycore_rk3288.h | 23 ++ > 11 files changed, 981 insertions(+) > create mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts > create mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi > create mode 100644 board/phytec/phycore_rk3288/Kconfig > create mode 100644 board/phytec/phycore_rk3288/MAINTAINERS > create mode 100644 board/phytec/phycore_rk3288/Makefile > create mode 100644 board/phytec/phycore_rk3288/phycore-rk3288.c > create mode 100644 configs/phycore-rk3288_defconfig > create mode 100644 include/configs/phycore_rk3288.h > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Mon, 19 Jun 2017, Wadim Egorov wrote: > The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. > The module can be connected to different carrier boards. > It can be also equipped with different RAM, SPI flash and eMMC variants. > The Rapid Development Kit option is using the following setup: > > - 1 GB DDR3 RAM (2 Banks) > - 1x 4 KB EEPROM > - DP83867 Gigabit Ethernet PHY > - 16 MB SPI Flash > - 4 GB eMMC Flash > > Add basic support for the PCM-947 carrier board, a RK3288 based development > board made by PHYTEC. This board works in a combination with > the phyCORE-RK3288 System on Module. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > Reviewed-by: Simon Glass <sjg@chromium.org> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > Changes in v4: > - Use of_machine_is_compatible() > - Wrap phycore_init()/of_machine_is_compatible() with CONFIG_SPL_OF_PLATDATA > and CONFIG_SPL_POWER_SUPPORT. Needed because of_machine_is_compatible() and > rk818_spl_configure_*() is not available with all rk3288 board configs. > - Added Reviewed-by: Simon Glass <sjg@chromium.org> > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3288-phycore-rdk.dts | 294 ++++++++++++++++ > arch/arm/dts/rk3288-phycore-som.dtsi | 506 +++++++++++++++++++++++++++ > arch/arm/mach-rockchip/rk3288-board-spl.c | 40 +++ > arch/arm/mach-rockchip/rk3288/Kconfig | 10 + > board/phytec/phycore_rk3288/Kconfig | 15 + > board/phytec/phycore_rk3288/MAINTAINERS | 6 + > board/phytec/phycore_rk3288/Makefile | 8 + > board/phytec/phycore_rk3288/phycore-rk3288.c | 8 + > configs/phycore-rk3288_defconfig | 70 ++++ > include/configs/phycore_rk3288.h | 23 ++ > 11 files changed, 981 insertions(+) > create mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts > create mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi > create mode 100644 board/phytec/phycore_rk3288/Kconfig > create mode 100644 board/phytec/phycore_rk3288/MAINTAINERS > create mode 100644 board/phytec/phycore_rk3288/Makefile > create mode 100644 board/phytec/phycore_rk3288/phycore-rk3288.c > create mode 100644 configs/phycore-rk3288_defconfig > create mode 100644 include/configs/phycore_rk3288.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 8b8f5e9..84f63e1 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ > rk3288-fennec.dtb \ > rk3288-firefly.dtb \ > rk3288-miqi.dtb \ > + rk3288-phycore-rdk.dtb \ > rk3288-popmetal.dtb \ > rk3288-rock2-square.dtb \ > rk3288-tinker.dtb \ > diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts > new file mode 100644 > index 0000000..f2bb7b5 > --- /dev/null > +++ b/arch/arm/dts/rk3288-phycore-rdk.dts > @@ -0,0 +1,294 @@ > +/* > + * Device tree file for Phytec PCM-947 carrier board > + * Copyright (C) 2017 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "rk3288-phycore-som.dtsi" > + > +/ { > + model = "Phytec RK3288 PCM-947"; > + compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; > + > + chosen { > + stdout-path = &uart2; > + }; > + > + config { > + u-boot,dm-pre-reloc; > + u-boot,boot0 = &emmc; > + }; > + > + user_buttons: user-buttons { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&user_button_pins>; > + > + button@0 { > + label = "home"; > + linux,code = <KEY_HOME>; > + gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + }; > + > + button@1 { > + label = "menu"; > + linux,code = <KEY_MENU>; > + gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + }; > + }; > + > + vcc_host0_5v: usb-host0-regulator { > + compatible = "regulator-fixed"; > + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&host0_vbus_drv>; > + regulator-name = "vcc_host0_5v"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + vin-supply = <&vdd_in_otg_out>; > + }; > + > + vcc_host1_5v: usb-host1-regulator { > + compatible = "regulator-fixed"; > + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&host1_vbus_drv>; > + regulator-name = "vcc_host1_5v"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + vin-supply = <&vdd_in_otg_out>; > + }; > + > + vcc_otg_5v: usb-otg-regulator { > + compatible = "regulator-fixed"; > + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&otg_vbus_drv>; > + regulator-name = "vcc_otg_5v"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + vin-supply = <&vdd_in_otg_out>; > + }; > +}; > + > +&dmc { > + rockchip,num-channels = <2>; > + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa > + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 > + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 > + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 > + 0x5 0x0>; > + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 > + 0xa60 0x40 0x10 0x0>; > + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; > + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; > +}; > + > +&gmac { > + status = "okay"; > +}; > + > +&hdmi { > + status = "okay"; > +}; > + > +&i2c1 { > + status = "okay"; > + > + touchscreen@44 { > + compatible = "st,stmpe811"; > + reg = <0x44>; > + }; > + > + adc@64 { > + compatible = "maxim,max1037"; > + reg = <0x64>; > + }; > + > + i2c_rtc: rtc@68 { > + compatible = "rv4162"; > + reg = <0x68>; > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c_rtc_int>; > + interrupt-parent = <&gpio5>; > + interrupts = <10 0>; > + }; > +}; > + > +&i2c3 { > + status = "okay"; > + > + i2c_eeprom_cb: eeprom@51 { > + compatible = "atmel,24c32"; > + reg = <0x51>; > + pagesize = <32>; > + }; > +}; > + > +&i2c4 { > + status = "okay"; > +}; > + > +&i2c5 { > + status = "okay"; > +}; > + > +&pinctrl { > + u-boot,dm-pre-reloc; > + > + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { > + bias-pull-up; > + drive-strength = <12>; > + }; > + > + buttons { > + user_button_pins: user-button-pins { > + /* button 1 */ > + rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>, > + /* button 2 */ > + <8 0 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > + > + rv4162 { > + i2c_rtc_int: i2c-rtc-int { > + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > + > + sdmmc { > + /* > + * Default drive strength isn't enough to achieve even > + * high-speed mode on pcm-947 board so bump up to 12 mA. > + */ > + sdmmc_bus4: sdmmc-bus4 { > + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, > + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, > + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, > + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; > + }; > + > + sdmmc_clk: sdmmc-clk { > + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; > + }; > + > + sdmmc_cmd: sdmmc-cmd { > + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; > + }; > + > + sdmmc_pwr: sdmmc-pwr { > + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > + touchscreen { > + ts_irq_pin: ts-irq-pin { > + rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > + usb_host { > + host0_vbus_drv: host0-vbus-drv { > + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + host1_vbus_drv: host1-vbus-drv { > + rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > + usb_otg { > + otg_vbus_drv: otg-vbus-drv { > + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > +}; > + > +&sdmmc { > + u-boot,dm-pre-reloc; > + > + bus-width = <4>; > + cap-mmc-highspeed; > + cap-sd-highspeed; > + card-detect-delay = <200>; > + disable-wp; > + num-slots = <1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; > + vmmc-supply = <&vdd_io_sd>; > + vqmmc-supply = <&vdd_io_sd>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; > + status = "okay"; > +}; > + > +&uart2 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&usbphy { > + status = "okay"; > +}; > + > +&usb_host0_ehci { > + status = "okay"; > +}; > + > +&usb_host1 { > + status = "okay"; > +}; > + > +&usb_otg { > + status = "okay"; > +}; > diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi > new file mode 100644 > index 0000000..fd463f4 > --- /dev/null > +++ b/arch/arm/dts/rk3288-phycore-som.dtsi > @@ -0,0 +1,506 @@ > +/* > + * Device tree file for Phytec phyCORE-RK3288 SoM > + * Copyright (C) 2017 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/net/ti-dp83867.h> > +#include "rk3288.dtsi" > + > +/ { > + model = "Phytec RK3288 phyCORE"; > + compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; > + > + /* > + * Set the minimum memory size here and > + * let the bootloader set the real size. > + */ > + memory { > + device_type = "memory"; > + reg = <0 0x8000000>; > + }; > + > + aliases { > + rtc0 = &i2c_rtc; > + rtc1 = &rk818; > + }; > + > + ext_gmac: external-gmac-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "ext_gmac"; > + }; > + > + io_domains: io_domains { > + compatible = "rockchip,rk3288-io-voltage-domain"; > + > + status = "okay"; > + sdcard-supply = <&vdd_io_sd>; > + flash0-supply = <&vdd_emmc_io>; > + flash1-supply = <&vdd_misc_1v8>; > + gpio1830-supply = <&vdd_3v3_io>; > + gpio30-supply = <&vdd_3v3_io>; > + bb-supply = <&vdd_3v3_io>; > + dvp-supply = <&vdd_3v3_io>; > + lcdc-supply = <&vdd_3v3_io>; > + wifi-supply = <&vdd_3v3_io>; > + audio-supply = <&vdd_3v3_io>; > + }; > + > + leds: user-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&user_led>; > + > + user { > + label = "green_led"; > + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + default-state = "keep"; > + }; > + }; > + > + vdd_emmc_io: vdd-emmc-io { > + compatible = "regulator-fixed"; > + regulator-name = "vdd_emmc_io"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vin-supply = <&vdd_3v3_io>; > + }; > + > + vdd_in_otg_out: vdd-in-otg-out { > + compatible = "regulator-fixed"; > + regulator-name = "vdd_in_otg_out"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + vdd_misc_1v8: vdd-misc-1v8 { > + compatible = "regulator-fixed"; > + regulator-name = "vdd_misc_1v8"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > +}; > + > +&cpu0 { > + cpu0-supply = <&vdd_cpu>; > + operating-points = < > + /* KHz uV */ > + 1800000 1400000 > + 1608000 1350000 > + 1512000 1300000 > + 1416000 1200000 > + 1200000 1100000 > + 1008000 1050000 > + 816000 1000000 > + 696000 950000 > + 600000 900000 > + 408000 900000 > + 312000 900000 > + 216000 900000 > + 126000 900000 > + >; > +}; > + > +&emmc { > + status = "okay"; > + u-boot,dm-pre-reloc; > + > + bus-width = <8>; > + cap-mmc-highspeed; > + disable-wp; > + non-removable; > + num-slots = <1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; > + vmmc-supply = <&vdd_3v3_io>; > + vqmmc-supply = <&vdd_emmc_io>; > +}; > + > +&gmac { > + assigned-clocks = <&cru SCLK_MAC>; > + assigned-clock-parents = <&ext_gmac>; > + clock_in_out = "input"; > + pinctrl-names = "default"; > + pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; > + phy-handle = <&phy0>; > + phy-supply = <&vdd_eth_2v5>; > + phy-mode = "rgmii-id"; > + snps,reset-active-low; > + snps,reset-delays-us = <0 10000 1000000>; > + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; > + tx_delay = <0x0>; > + rx_delay = <0x0>; > + > + mdio0 { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + phy0: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + interrupt-parent = <&gpio4>; > + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + enet-phy-lane-no-swap; > + }; > + }; > +}; > + > +&hdmi { > + ddc-i2c-bus = <&i2c5>; > +}; > + > +&i2c0 { > + status = "okay"; > + u-boot,dm-pre-reloc; > + > + clock-frequency = <400000>; > + > + rk818: pmic@1c { > + status = "okay"; > + compatible = "rockchip,rk818"; > + reg = <0x1c>; > + interrupt-parent = <&gpio0>; > + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_int>; > + rockchip,system-power-controller; > + wakeup-source; > + #clock-cells = <1>; > + u-boot,dm-pre-reloc; > + > + vcc1-supply = <&vdd_sys>; > + vcc2-supply = <&vdd_sys>; > + vcc3-supply = <&vdd_sys>; > + vcc4-supply = <&vdd_sys>; > + boost-supply = <&vdd_in_otg_out>; > + vcc6-supply = <&vdd_sys>; > + vcc7-supply = <&vdd_misc_1v8>; > + vcc8-supply = <&vdd_misc_1v8>; > + vcc9-supply = <&vdd_3v3_io>; > + vddio-supply = <&vdd_3v3_io>; > + > + regulators { > + u-boot,dm-pre-reloc; > + vdd_log: DCDC_REG1 { > + regulator-name = "vdd_log"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vdd_gpu: DCDC_REG2 { > + regulator-name = "vdd_gpu"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1250000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <1000000>; > + }; > + }; > + > + vcc_ddr: DCDC_REG3 { > + regulator-name = "vcc_ddr"; > + regulator-always-on; > + regulator-boot-on; > + regulator-state-mem { > + regulator-on-in-suspend; > + }; > + }; > + > + vdd_3v3_io: DCDC_REG4 { > + regulator-name = "vdd_3v3_io"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <3300000>; > + }; > + }; > + > + vdd_sys: DCDC_BOOST { > + regulator-name = "vdd_sys"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <5000000>; > + }; > + }; > + > + /* vcc9 */ > + vdd_sd: SWITCH_REG { > + regulator-name = "vdd_sd"; > + regulator-always-on; > + regulator-boot-on; > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + /* vcc6 */ > + vdd_eth_2v5: LDO_REG2 { > + regulator-name = "vdd_eth_2v5"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <2500000>; > + }; > + }; > + > + /* vcc7 */ > + vdd_1v0: LDO_REG3 { > + regulator-name = "vdd_1v0"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <1000000>; > + }; > + }; > + > + /* vcc8 */ > + vdd_1v8_lcd_ldo: LDO_REG4 { > + regulator-name = "vdd_1v8_lcd_ldo"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <1800000>; > + }; > + }; > + > + /* vcc8 */ > + vdd_1v0_lcd: LDO_REG6 { > + regulator-name = "vdd_1v0_lcd"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <1000000>; > + }; > + }; > + > + /* vcc7 */ > + vdd_1v8_ldo: LDO_REG7 { > + regulator-name = "vdd_1v8_ldo"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-state-mem { > + regulator-off-in-suspend; > + regulator-suspend-microvolt = <1800000>; > + }; > + }; > + > + /* vcc9 */ > + vdd_io_sd: LDO_REG9 { > + regulator-name = "vdd_io_sd"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <3300000>; > + }; > + }; > + }; > + }; > + > + /* M24C32-D */ > + i2c_eeprom: eeprom@50 { > + compatible = "atmel,24c32"; > + reg = <0x50>; > + pagesize = <32>; > + }; > + > + vdd_cpu: regulator@60 { > + compatible = "fcs,fan53555"; > + reg = <0x60>; > + fcs,suspend-voltage-selector = <1>; > + regulator-always-on; > + regulator-boot-on; > + regulator-enable-ramp-delay = <300>; > + regulator-name = "vdd_cpu"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1430000>; > + regulator-ramp-delay = <8000>; > + vin-supply = <&vdd_sys>; > + }; > +}; > + > +&pinctrl { > + pcfg_output_high: pcfg-output-high { > + output-high; > + }; > + > + emmc { > + /* > + * We run eMMC at max speed; bump up drive strength. > + * We also have external pulls, so disable the internal ones. > + */ > + emmc_clk: emmc-clk { > + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; > + }; > + > + emmc_cmd: emmc-cmd { > + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; > + }; > + > + emmc_bus8: emmc-bus8 { > + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, > + <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; > + }; > + }; > + > + gmac { > + phy_int: phy-int { > + rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + > + phy_rst: phy-rst { > + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; > + }; > + }; > + > + leds { > + user_led: user-led { > + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; > + }; > + }; > + > + pmic { > + pmic_int: pmic-int { > + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + > + /* Pin for switching state between sleep and non-sleep state */ > + pmic_sleep: pmic-sleep { > + rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > +}; > + > +&pwm1 { > + status = "okay"; > +}; > + > +&saradc { > + status = "okay"; > + vref-supply = <&vdd_1v8_ldo>; > +}; > + > +&spi2 { > + status = "okay"; > + > + serial_flash: flash@0 { > + compatible = "micron,n25q128a13", "jedec,spi-nor"; > + reg = <0x0>; > + spi-max-frequency = <50000000>; > + m25p,fast-read; > + #address-cells = <1>; > + #size-cells = <1>; > + status = "okay"; > + }; > +}; > + > +&tsadc { > + status = "okay"; > + rockchip,hw-tshut-mode = <0>; > + rockchip,hw-tshut-polarity = <0>; > +}; > + > +&vopb { > + status = "okay"; > +}; > + > +&vopb_mmu { > + status = "okay"; > +}; > + > +&vopl { > + status = "okay"; > +}; > + > +&vopl_mmu { > + status = "okay"; > +}; > + > +&wdt { > + status = "okay"; > +}; > diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c > index 8ca6b1e..5668fd2 100644 > --- a/arch/arm/mach-rockchip/rk3288-board-spl.c > +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c > @@ -8,6 +8,7 @@ > #include <debug_uart.h> > #include <dm.h> > #include <fdtdec.h> > +#include <i2c.h> > #include <led.h> > #include <malloc.h> > #include <ram.h> > @@ -25,6 +26,7 @@ > #include <dm/test.h> > #include <dm/util.h> > #include <power/regulator.h> > +#include <power/rk8xx_pmic.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -157,6 +159,32 @@ static int configure_emmc(struct udevice *pinctrl) > } > #endif > > +#if !defined(CONFIG_SPL_OF_PLATDATA) > +static int phycore_init(void) > +{ > + struct udevice *pmic; > + int ret; > + > + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); > + if (ret) > + return ret; > + > +#if defined(CONFIG_SPL_POWER_SUPPORT) > + /* Increase USB input current to 2A */ > + ret = rk818_spl_configure_usb_input_current(pmic, 2000); > + if (ret) > + return ret; > + > + /* Close charger when USB lower then 3.26V */ > + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); > + if (ret) > + return ret; > +#endif > + > + return 0; > +} > +#endif If possible, use CONFIG_IS_ENABLED (e.g. CONFIG_IS_ENABLED(OF_PLATDATA)). This comment applies to the entire patchset. > + > void board_init_f(ulong dummy) > { > struct udevice *pinctrl; > @@ -203,6 +231,18 @@ void board_init_f(ulong dummy) > debug("Pinctrl init failed: %d\n", ret); > return; > } > + > +#if !defined(CONFIG_SPL_OF_PLATDATA) > + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { > + ret = phycore_init(); > + if (ret) { > + debug("Failed to set up phycore power settings: %d\n", > + ret); > + return; > + } > + } > +#endif > + > debug("\nspl:init dram\n"); > ret = uclass_get_device(UCLASS_RAM, 0, &dev); > if (ret) { > diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig > index 8e7355e..53cc9a0 100644 > --- a/arch/arm/mach-rockchip/rk3288/Kconfig > +++ b/arch/arm/mach-rockchip/rk3288/Kconfig > @@ -66,6 +66,14 @@ config TARGET_MIQI_RK3288 > has 1 or 2 GiB SDRAM. Expansion connectors provide access to > I2C, SPI, UART, GPIOs and fan control. > > +config TARGET_PHYCORE_RK3288 > + bool "phyCORE-RK3288" > + select BOARD_LATE_INIT > + help > + Add basic support for the PCM-947 carrier board, a RK3288 based > + development board made by PHYTEC. This board works in a combination > + with the phyCORE-RK3288 System on Module. > + > config TARGET_POPMETAL_RK3288 > bool "PopMetal-RK3288" > select BOARD_LATE_INIT > @@ -129,6 +137,8 @@ source "board/google/veyron/Kconfig" > > source "board/mqmaker/miqi_rk3288/Kconfig" > > +source "board/phytec/phycore_rk3288/Kconfig" > + > source "board/radxa/rock2/Kconfig" > > source "board/rockchip/evb_rk3288/Kconfig" > diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig > new file mode 100644 > index 0000000..57cd8e2 > --- /dev/null > +++ b/board/phytec/phycore_rk3288/Kconfig > @@ -0,0 +1,15 @@ > +if TARGET_PHYCORE_RK3288 > + > +config SYS_BOARD > + default "phycore_rk3288" > + > +config SYS_VENDOR > + default "phytec" > + > +config SYS_CONFIG_NAME > + default "phycore_rk3288" > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + > +endif > diff --git a/board/phytec/phycore_rk3288/MAINTAINERS b/board/phytec/phycore_rk3288/MAINTAINERS > new file mode 100644 > index 0000000..9c0de3c > --- /dev/null > +++ b/board/phytec/phycore_rk3288/MAINTAINERS > @@ -0,0 +1,6 @@ > +phyCORE-RK3288 > +M: Wadim Egorov <w.egorov@phytec.de> > +S: Maintained > +F: board/phytec/phycore_rk3288 > +F: include/configs/phycore_rk3288.h > +F: configs/phycore-rk3288_defconfig > diff --git a/board/phytec/phycore_rk3288/Makefile b/board/phytec/phycore_rk3288/Makefile > new file mode 100644 > index 0000000..f379fbe > --- /dev/null > +++ b/board/phytec/phycore_rk3288/Makefile > @@ -0,0 +1,8 @@ > +# > +# Copyright (C) 2017 PHYTEC Messtechnik GmbH > +# Author: Wadim Egorov <w.egorov@phytec.de> > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += phycore-rk3288.o > diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c > new file mode 100644 > index 0000000..20696f6 > --- /dev/null > +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c > @@ -0,0 +1,8 @@ > +/* > + * Copyright (C) 2017 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> Please don't create an empty file. Note that there's no reason to include 'common.h', if there's no further code in this compilation unit. > diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig > new file mode 100644 > index 0000000..823db06 > --- /dev/null > +++ b/configs/phycore-rk3288_defconfig > @@ -0,0 +1,70 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_ROCKCHIP_RK3288=y > +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y > +CONFIG_TARGET_PHYCORE_RK3288=y > +CONFIG_SPL_STACK_R_ADDR=0x80000 > +CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk" > +CONFIG_DEBUG_UART=y > +CONFIG_SILENT_CONSOLE=y > +CONFIG_CONSOLE_MUX=y > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 > +CONFIG_SPL_I2C_SUPPORT=y > +CONFIG_SPL_POWER_SUPPORT=y > +# CONFIG_CMD_IMLS is not set > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_GPIO=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_PMIC=y > +CONFIG_CMD_REGULATOR=y > +# CONFIG_SPL_DOS_PARTITION is not set > +# CONFIG_SPL_ISO_PARTITION is not set > +# CONFIG_SPL_EFI_PARTITION is not set > +CONFIG_SPL_PARTITION_UUIDS=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_REGMAP=y > +CONFIG_SPL_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_SYSCON=y > +# CONFIG_SPL_SIMPLE_BUS is not set > +CONFIG_CLK=y > +CONFIG_SPL_CLK=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +# CONFIG_SPL_PINCTRL_FULL is not set > +CONFIG_PINCTRL_ROCKCHIP_RK3288=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_RAM=y > +CONFIG_SPL_RAM=y > +CONFIG_DEBUG_UART_BASE=0xff690000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550=y > +CONFIG_SYSRESET=y > +CONFIG_USB=y > +CONFIG_USB_STORAGE=y > +CONFIG_USE_TINY_PRINTF=y > +CONFIG_CMD_DHRYSTONE=y > +CONFIG_ERRNO_STR=y > diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h > new file mode 100644 > index 0000000..aab43ed > --- /dev/null > +++ b/include/configs/phycore_rk3288.h > @@ -0,0 +1,23 @@ > +/* > + * Copyright (C) 2017 PHYTEC Messtechnik GmbH > + * Author: Wadim Egorov <w.egorov@phytec.de> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#define ROCKCHIP_DEVICE_SETTINGS > +#include <configs/rk3288_common.h> > + > +#undef BOOT_TARGET_DEVICES > + > +#define BOOT_TARGET_DEVICES(func) \ > + func(MMC, mmc, 0) \ > + func(MMC, mmc, 1) > + > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_SYS_MMC_ENV_DEV 1 > + > +#endif >
> The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. > The module can be connected to different carrier boards. > It can be also equipped with different RAM, SPI flash and eMMC variants. > The Rapid Development Kit option is using the following setup: > > - 1 GB DDR3 RAM (2 Banks) > - 1x 4 KB EEPROM > - DP83867 Gigabit Ethernet PHY > - 16 MB SPI Flash > - 4 GB eMMC Flash > > Add basic support for the PCM-947 carrier board, a RK3288 based development > board made by PHYTEC. This board works in a combination with > the phyCORE-RK3288 System on Module. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > Reviewed-by: Simon Glass <sjg@chromium.org> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > Changes in v4: > - Use of_machine_is_compatible() > - Wrap phycore_init()/of_machine_is_compatible() with CONFIG_SPL_OF_PLATDATA > and CONFIG_SPL_POWER_SUPPORT. Needed because of_machine_is_compatible() and > rk818_spl_configure_*() is not available with all rk3288 board configs. > - Added Reviewed-by: Simon Glass <sjg@chromium.org> > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3288-phycore-rdk.dts | 294 ++++++++++++++++ > arch/arm/dts/rk3288-phycore-som.dtsi | 506 +++++++++++++++++++++++++++ > arch/arm/mach-rockchip/rk3288-board-spl.c | 40 +++ > arch/arm/mach-rockchip/rk3288/Kconfig | 10 + > board/phytec/phycore_rk3288/Kconfig | 15 + > board/phytec/phycore_rk3288/MAINTAINERS | 6 + > board/phytec/phycore_rk3288/Makefile | 8 + > board/phytec/phycore_rk3288/phycore-rk3288.c | 8 + > configs/phycore-rk3288_defconfig | 70 ++++ > include/configs/phycore_rk3288.h | 23 ++ > 11 files changed, 981 insertions(+) > create mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts > create mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi > create mode 100644 board/phytec/phycore_rk3288/Kconfig > create mode 100644 board/phytec/phycore_rk3288/MAINTAINERS > create mode 100644 board/phytec/phycore_rk3288/Makefile > create mode 100644 board/phytec/phycore_rk3288/phycore-rk3288.c > create mode 100644 configs/phycore-rk3288_defconfig > create mode 100644 include/configs/phycore_rk3288.h > Applied to u-boot-rockchip/next, thanks!
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8b8f5e9..84f63e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-tinker.dtb \ diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts new file mode 100644 index 0000000..f2bb7b5 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -0,0 +1,294 @@ +/* + * Device tree file for Phytec PCM-947 carrier board + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "rk3288-phycore-som.dtsi" + +/ { + model = "Phytec RK3288 PCM-947"; + compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + config { + u-boot,dm-pre-reloc; + u-boot,boot0 = &emmc; + }; + + user_buttons: user-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_button_pins>; + + button@0 { + label = "home"; + linux,code = <KEY_HOME>; + gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + button@1 { + label = "menu"; + linux,code = <KEY_MENU>; + gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + }; + + vcc_host0_5v: usb-host0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host0_vbus_drv>; + regulator-name = "vcc_host0_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_host1_5v: usb-host1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host1_vbus_drv>; + regulator-name = "vcc_host1_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; +}; + +&gmac { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; + + i2c_rtc: rtc@68 { + compatible = "rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_rtc_int>; + interrupt-parent = <&gpio5>; + interrupts = <10 0>; + }; +}; + +&i2c3 { + status = "okay"; + + i2c_eeprom_cb: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + buttons { + user_button_pins: user-button-pins { + /* button 1 */ + rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>, + /* button 2 */ + <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rv4162 { + i2c_rtc_int: i2c-rtc-int { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on pcm-947 board so bump up to 12 mA. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + ts_irq_pin: ts-irq-pin { + rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host0_vbus_drv: host0-vbus-drv { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host1_vbus_drv: host1-vbus-drv { + rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vdd_io_sd>; + vqmmc-supply = <&vdd_io_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi new file mode 100644 index 0000000..fd463f4 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -0,0 +1,506 @@ +/* + * Device tree file for Phytec phyCORE-RK3288 SoM + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include "rk3288.dtsi" + +/ { + model = "Phytec RK3288 phyCORE"; + compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0 0x8000000>; + }; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rk818; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + io_domains: io_domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + + status = "okay"; + sdcard-supply = <&vdd_io_sd>; + flash0-supply = <&vdd_emmc_io>; + flash1-supply = <&vdd_misc_1v8>; + gpio1830-supply = <&vdd_3v3_io>; + gpio30-supply = <&vdd_3v3_io>; + bb-supply = <&vdd_3v3_io>; + dvp-supply = <&vdd_3v3_io>; + lcdc-supply = <&vdd_3v3_io>; + wifi-supply = <&vdd_3v3_io>; + audio-supply = <&vdd_3v3_io>; + }; + + leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led>; + + user { + label = "green_led"; + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "keep"; + }; + }; + + vdd_emmc_io: vdd-emmc-io { + compatible = "regulator-fixed"; + regulator-name = "vdd_emmc_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3_io>; + }; + + vdd_in_otg_out: vdd-in-otg-out { + compatible = "regulator-fixed"; + regulator-name = "vdd_in_otg_out"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_misc_1v8: vdd-misc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_misc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; + operating-points = < + /* KHz uV */ + 1800000 1400000 + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; +}; + +&emmc { + status = "okay"; + u-boot,dm-pre-reloc; + + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vdd_3v3_io>; + vqmmc-supply = <&vdd_emmc_io>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; + phy-handle = <&phy0>; + phy-supply = <&vdd_eth_2v5>; + phy-mode = "rgmii-id"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + tx_delay = <0x0>; + rx_delay = <0x0>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + enet-phy-lane-no-swap; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + clock-frequency = <400000>; + + rk818: pmic@1c { + status = "okay"; + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + boost-supply = <&vdd_in_otg_out>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vdd_misc_1v8>; + vcc8-supply = <&vdd_misc_1v8>; + vcc9-supply = <&vdd_3v3_io>; + vddio-supply = <&vdd_3v3_io>; + + regulators { + u-boot,dm-pre-reloc; + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_3v3_io: DCDC_REG4 { + regulator-name = "vdd_3v3_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_sys: DCDC_BOOST { + regulator-name = "vdd_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + /* vcc9 */ + vdd_sd: SWITCH_REG { + regulator-name = "vdd_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* vcc6 */ + vdd_eth_2v5: LDO_REG2 { + regulator-name = "vdd_eth_2v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2500000>; + }; + }; + + /* vcc7 */ + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc8 */ + vdd_1v8_lcd_ldo: LDO_REG4 { + regulator-name = "vdd_1v8_lcd_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc8 */ + vdd_1v0_lcd: LDO_REG6 { + regulator-name = "vdd_1v0_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc7 */ + vdd_1v8_ldo: LDO_REG7 { + regulator-name = "vdd_1v8_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc9 */ + vdd_io_sd: LDO_REG9 { + regulator-name = "vdd_io_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; + }; + + /* M24C32-D */ + i2c_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + vdd_cpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1430000>; + regulator-ramp-delay = <8000>; + vin-supply = <&vdd_sys>; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + user_led: user-led { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* Pin for switching state between sleep and non-sleep state */ + pmic_sleep: pmic-sleep { + rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_ldo>; +}; + +&spi2 { + status = "okay"; + + serial_flash: flash@0 { + compatible = "micron,n25q128a13", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 8ca6b1e..5668fd2 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -8,6 +8,7 @@ #include <debug_uart.h> #include <dm.h> #include <fdtdec.h> +#include <i2c.h> #include <led.h> #include <malloc.h> #include <ram.h> @@ -25,6 +26,7 @@ #include <dm/test.h> #include <dm/util.h> #include <power/regulator.h> +#include <power/rk8xx_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -157,6 +159,32 @@ static int configure_emmc(struct udevice *pinctrl) } #endif +#if !defined(CONFIG_SPL_OF_PLATDATA) +static int phycore_init(void) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); + if (ret) + return ret; + +#if defined(CONFIG_SPL_POWER_SUPPORT) + /* Increase USB input current to 2A */ + ret = rk818_spl_configure_usb_input_current(pmic, 2000); + if (ret) + return ret; + + /* Close charger when USB lower then 3.26V */ + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); + if (ret) + return ret; +#endif + + return 0; +} +#endif + void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -203,6 +231,18 @@ void board_init_f(ulong dummy) debug("Pinctrl init failed: %d\n", ret); return; } + +#if !defined(CONFIG_SPL_OF_PLATDATA) + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { + ret = phycore_init(); + if (ret) { + debug("Failed to set up phycore power settings: %d\n", + ret); + return; + } + } +#endif + debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 8e7355e..53cc9a0 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -66,6 +66,14 @@ config TARGET_MIQI_RK3288 has 1 or 2 GiB SDRAM. Expansion connectors provide access to I2C, SPI, UART, GPIOs and fan control. +config TARGET_PHYCORE_RK3288 + bool "phyCORE-RK3288" + select BOARD_LATE_INIT + help + Add basic support for the PCM-947 carrier board, a RK3288 based + development board made by PHYTEC. This board works in a combination + with the phyCORE-RK3288 System on Module. + config TARGET_POPMETAL_RK3288 bool "PopMetal-RK3288" select BOARD_LATE_INIT @@ -129,6 +137,8 @@ source "board/google/veyron/Kconfig" source "board/mqmaker/miqi_rk3288/Kconfig" +source "board/phytec/phycore_rk3288/Kconfig" + source "board/radxa/rock2/Kconfig" source "board/rockchip/evb_rk3288/Kconfig" diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig new file mode 100644 index 0000000..57cd8e2 --- /dev/null +++ b/board/phytec/phycore_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PHYCORE_RK3288 + +config SYS_BOARD + default "phycore_rk3288" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/phytec/phycore_rk3288/MAINTAINERS b/board/phytec/phycore_rk3288/MAINTAINERS new file mode 100644 index 0000000..9c0de3c --- /dev/null +++ b/board/phytec/phycore_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +phyCORE-RK3288 +M: Wadim Egorov <w.egorov@phytec.de> +S: Maintained +F: board/phytec/phycore_rk3288 +F: include/configs/phycore_rk3288.h +F: configs/phycore-rk3288_defconfig diff --git a/board/phytec/phycore_rk3288/Makefile b/board/phytec/phycore_rk3288/Makefile new file mode 100644 index 0000000..f379fbe --- /dev/null +++ b/board/phytec/phycore_rk3288/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 PHYTEC Messtechnik GmbH +# Author: Wadim Egorov <w.egorov@phytec.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += phycore-rk3288.o diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c new file mode 100644 index 0000000..20696f6 --- /dev/null +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig new file mode 100644 index 0000000..823db06 --- /dev/null +++ b/configs/phycore-rk3288_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_PHYCORE_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk" +CONFIG_DEBUG_UART=y +CONFIG_SILENT_CONSOLE=y +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h new file mode 100644 index 0000000..aab43ed --- /dev/null +++ b/include/configs/phycore_rk3288.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#endif