===================================================================
@@ -141,11 +141,13 @@ (define_insn "movsf_low_st_di"
;; 64-bit MachO load/store support
(define_insn "movdi_low"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
+ (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
- "{l|ld} %0,lo16(%2)(%1)"
+ "@
+ {l|ld} %0,lo16(%2)(%1)
+ lfd %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
@@ -159,11 +161,13 @@ (define_insn "movsi_low_st"
(set_attr "length" "4")])
(define_insn "movdi_low_st"
- [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
+ [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
- (match_operand:DI 0 "gpc_reg_operand" "r"))]
+ (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
"TARGET_MACHO && TARGET_64BIT"
- "{st|std} %0,lo16(%2)(%1)"
+ "@
+ {st|std} %0,lo16(%2)(%1)
+ stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])