===================================================================
@@ -133,6 +133,9 @@
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
+(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
+ "BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
+
;; wB needs ISA 2.07 VUPKHSW
(define_constraint "wB"
"Signed 5-bit constant integer that can be loaded into an altivec register."
===================================================================
@@ -2468,6 +2468,7 @@
"wx reg_class = %s\n"
"wy reg_class = %s\n"
"wz reg_class = %s\n"
+ "wA reg_class = %s\n"
"wH reg_class = %s\n"
"wI reg_class = %s\n"
"wJ reg_class = %s\n"
@@ -2500,6 +2501,7 @@
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
@@ -3210,7 +3212,10 @@
}
if (TARGET_POWERPC64)
- rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
+ {
+ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
+ }
if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
{
===================================================================
@@ -1612,6 +1612,7 @@
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wy, /* VSX register for SF */
RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
+ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
===================================================================
@@ -3072,7 +3072,7 @@
"=<VSa>, <VSa>,we,<VS_64dm>")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "splat_input_operand"
- "<VS_64reg>,Z, b, wr")))]
+ "<VS_64reg>,Z, b, wA")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
===================================================================
@@ -3122,6 +3122,9 @@
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.
+@item wA
+Address base register if 64-bit instructions are enabled or NO_REGS.
+
@item wB
Signed 5-bit constant integer that can be loaded into an altivec register.