| Message ID | 20170317225254.19182-1-palmer@dabbelt.com |
|---|---|
| State | New |
| Headers | show |
On Fri, 17 Mar 2017 15:52:54 PDT (-0700), Palmer Dabbelt wrote: > The RISC-V memory model is still in the process of being formally > specified, so for now we're going to be safe and add the I/O bits to > userspace fences because there's no way to know if userspace is touching > memory-mapped I/O regions at compile time. > > This will have no impact on existing microarchitecutres because they > treat all fences conservatively. > > gcc/ChangeLog: > > 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> > > * config/riscv/riscv.c (riscv_print_operand): Use "fence > iorw,ow". > * config/riscv/sync.mc (mem_thread_fence_1): Use "fence > iorw,iorw". > --- > gcc/ChangeLog | 7 +++++++ > gcc/config/riscv/riscv.c | 2 +- > gcc/config/riscv/sync.md | 2 +- > 3 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/gcc/ChangeLog b/gcc/ChangeLog > index 3e108dd..de32689 100644 > --- a/gcc/ChangeLog > +++ b/gcc/ChangeLog > @@ -1,3 +1,10 @@ > +2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> > + > + * config/riscv/riscv.c (riscv_print_operand): Use "fence > + iorw,ow". > + * config/riscv/sync.mc (mem_thread_fence_1): Use "fence > + iorw,iorw". > + > 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com > > * doc/install.texi (Specific) <riscv32-*-elf>: Add riscv32-*-elf, > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c > index 25cc803..fa93c3c 100644 > --- a/gcc/config/riscv/riscv.c > +++ b/gcc/config/riscv/riscv.c > @@ -2794,7 +2794,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) > > case 'F': > if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) > - fputs ("fence rw,w; ", file); > + fputs ("fence iorw,ow; ", file); > break; > > default: > diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md > index 09970b9..cde19e3 100644 > --- a/gcc/config/riscv/sync.md > +++ b/gcc/config/riscv/sync.md > @@ -53,7 +53,7 @@ > (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) > (match_operand:SI 1 "const_int_operand" "")] ;; model > "" > - "fence\trw,rw") > + "fence\tiorw,iorw") > > ;; Atomic memory operations. Committed.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e108dd..de32689 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> + + * config/riscv/riscv.c (riscv_print_operand): Use "fence + iorw,ow". + * config/riscv/sync.mc (mem_thread_fence_1): Use "fence + iorw,iorw". + 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com * doc/install.texi (Specific) <riscv32-*-elf>: Add riscv32-*-elf, diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 25cc803..fa93c3c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2794,7 +2794,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'F': if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) - fputs ("fence rw,w; ", file); + fputs ("fence iorw,ow; ", file); break; default: diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 09970b9..cde19e3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,7 @@ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\trw,rw") + "fence\tiorw,iorw") ;; Atomic memory operations.
The RISC-V memory model is still in the process of being formally specified, so for now we're going to be safe and add the I/O bits to userspace fences because there's no way to know if userspace is touching memory-mapped I/O regions at compile time. This will have no impact on existing microarchitecutres because they treat all fences conservatively. gcc/ChangeLog: 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> * config/riscv/riscv.c (riscv_print_operand): Use "fence iorw,ow". * config/riscv/sync.mc (mem_thread_fence_1): Use "fence iorw,iorw". --- gcc/ChangeLog | 7 +++++++ gcc/config/riscv/riscv.c | 2 +- gcc/config/riscv/sync.md | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-)