| Message ID | 20170317225416.19343-1-palmer@dabbelt.com |
|---|---|
| State | New |
| Headers | show |
On Fri, 17 Mar 2017 15:54:16 PDT (-0700), Palmer Dabbelt wrote: > On RISC-V we can't store integers in floating-point registers as this is > forbidden by the ISA. We've always disallowed this, but we were > setting the preferred mode to FP_REGS for some integer modes. This > caused the LRA to blow up with some hard to read error messages. > > This patch removes the prefered mode hook, as the right thing to do here > is nothing. > > Thanks to Kito for finding the bug, and mpf for the fix. See also > <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79912>. > > PR target/79912 > --- > gcc/ChangeLog | 6 ++++++ > gcc/config/riscv/riscv.c | 13 ------------- > 2 files changed, 6 insertions(+), 13 deletions(-) > > diff --git a/gcc/ChangeLog b/gcc/ChangeLog > index de32689..5e90179 100644 > --- a/gcc/ChangeLog > +++ b/gcc/ChangeLog > @@ -1,5 +1,11 @@ > 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> > > + PR target/79912 > + * config/riscv/riscv.c (riscv_preferred_reload_class): Remove. > + (TARGET_PREFERRED_RELOAD_CLASS): Likewise. > + > +2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> > + > * config/riscv/riscv.c (riscv_print_operand): Use "fence > iorw,ow". > * config/riscv/sync.mc (mem_thread_fence_1): Use "fence > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c > index fa93c3c..d5928c3 100644 > --- a/gcc/config/riscv/riscv.c > +++ b/gcc/config/riscv/riscv.c > @@ -3629,16 +3629,6 @@ riscv_class_max_nregs (reg_class_t rclass, enum machine_mode mode) > return 0; > } > > -/* Implement TARGET_PREFERRED_RELOAD_CLASS. */ > - > -static reg_class_t > -riscv_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) > -{ > - return reg_class_subset_p (FP_REGS, rclass) ? FP_REGS : > - reg_class_subset_p (GR_REGS, rclass) ? GR_REGS : > - rclass; > -} > - > /* Implement TARGET_MEMORY_MOVE_COST. */ > > static int > @@ -4031,9 +4021,6 @@ riscv_cannot_copy_insn_p (rtx_insn *insn) > #undef TARGET_ADDRESS_COST > #define TARGET_ADDRESS_COST riscv_address_cost > > -#undef TARGET_PREFERRED_RELOAD_CLASS > -#define TARGET_PREFERRED_RELOAD_CLASS riscv_preferred_reload_class > - > #undef TARGET_ASM_FILE_START > #define TARGET_ASM_FILE_START riscv_file_start > #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE Committed.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index de32689..5e90179 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> + PR target/79912 + * config/riscv/riscv.c (riscv_preferred_reload_class): Remove. + (TARGET_PREFERRED_RELOAD_CLASS): Likewise. + +2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> + * config/riscv/riscv.c (riscv_print_operand): Use "fence iorw,ow". * config/riscv/sync.mc (mem_thread_fence_1): Use "fence diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index fa93c3c..d5928c3 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3629,16 +3629,6 @@ riscv_class_max_nregs (reg_class_t rclass, enum machine_mode mode) return 0; } -/* Implement TARGET_PREFERRED_RELOAD_CLASS. */ - -static reg_class_t -riscv_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) -{ - return reg_class_subset_p (FP_REGS, rclass) ? FP_REGS : - reg_class_subset_p (GR_REGS, rclass) ? GR_REGS : - rclass; -} - /* Implement TARGET_MEMORY_MOVE_COST. */ static int @@ -4031,9 +4021,6 @@ riscv_cannot_copy_insn_p (rtx_insn *insn) #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST riscv_address_cost -#undef TARGET_PREFERRED_RELOAD_CLASS -#define TARGET_PREFERRED_RELOAD_CLASS riscv_preferred_reload_class - #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START riscv_file_start #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE