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[i386] : Change stack probing and allocation implementation

Message ID AANLkTimwp0i-9QTR=ejWnRVNJKzMVT7jLNdu8fEJAHkS@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak Sept. 26, 2010, 4:35 p.m. UTC 
Hello!

> >> 2010-08-19  Kai Tietz
> >>
> >>        * config/i386/cygwin.asm (___chkstk_ms): New.
> >>        * config/i386/i386.c (override_options): Replace
> >>        gen_allocate_stack_worker_,, by gen_allocate_stack_worker_probe_,,.
> >>        (ix86_expand_prologue): Adjust probed stack allocation.
> >>        * config/i386/i386.md (define_insn "allocate_stack_worker_32): Removed.
> >>        (define_insn "allocate_stack_worker_64): Removed.
> >>        (define_insn "allocate_stack_worker_probe_32): New.
> >>        (define_insn "allocate_stack_worker_probe_64): New.
> >>        (allocate_stack): Adjust probed stack allocation.
>
> I altered the patch a bit.  Tidied up the .md changes with macros,
> tidied up the assembly file with multiple object files and dwarf2
> unwind info.  Adjusted the prologue code to use the value in eax.

> +(define_insn "pro_epilogue_adjust_stack_<mode>_2"
> +  [(set (match_operand:P 0 "register_operand" "=r")
> +	(plus:P (match_operand:DI 1 "register_operand" "0")
> +		 (match_operand:DI 2 "register_operand" "r")))
>     (clobber (reg:CC FLAGS_REG))
>     (clobber (mem:BLK (scratch)))]

Hm, this can't be right for Pmode == SImode. Alternatively, it is now
possible to merge pro_epilogue_..._1 and pro_epilogue_,,,_2 into:

(define_insn "pro_epilogue_adjust_stack_<mode>_add"
  [(set (match_operand:P 0 "register_operand" "=r,r")
	(plus:P (match_operand:P 1 "register_operand" "0,r")
	        (match_operand:P 2 "<nonmemory_operand>" "r<i>,l<i>")))
   (clobber (reg:CC FLAGS_REG))
   (clobber (mem:BLK (scratch)))]
  ""
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOV:
      return "mov{<imodesuffix>}\t{%1, %0|%0, %1}";

    case TYPE_ALU:
      gcc_assert (rtx_equal_p (operands[0], operands[1]));
      if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
	return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";

      return "add{<imodesuffix>}\t{%2, %0|%0, %2}";

    default:
      operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
      return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
    }
}
  [(set (attr "type")
	(cond [(and (eq_attr "alternative" "0")
		    (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
		 (const_string "alu")
	       (match_operand:<MODE> 2 "const0_operand" "")
		 (const_string "imov")
	      ]
	      (const_string "lea")))
   (set (attr "length_immediate")
	(cond [(eq_attr "type" "imov")
		 (const_string "0")
	       (and (eq_attr "type" "alu")
		    (match_operand 2 "const128_operand" ""))
		 (const_string "1")
	      ]
	      (const_string "*")))
   (set_attr "mode" "<MODE>")])

Attached [RFC] patch implements this merge, and some related cleanups
involving renames and indirect functions. Patch was tested on
x86_64-pc-linux-gnu without regressions.

Uros.

Comments

Richard Henderson Sept. 26, 2010, 6:08 p.m. UTC | #1 
On 09/26/2010 09:35 AM, Uros Bizjak wrote:
>> +(define_insn "pro_epilogue_adjust_stack_<mode>_2"
>> +  [(set (match_operand:P 0 "register_operand" "=r")
>> +	(plus:P (match_operand:DI 1 "register_operand" "0")
>> +		 (match_operand:DI 2 "register_operand" "r")))
>>     (clobber (reg:CC FLAGS_REG))
>>     (clobber (mem:BLK (scratch)))]
> 
> Hm, this can't be right for Pmode == SImode.

Oh shoot.  I fixed that in one tree, but failed to push that
back to the copy from which I pushed the change.

> Attached [RFC] patch implements this merge, and some related cleanups
> involving renames and indirect functions. Patch was tested on
> x86_64-pc-linux-gnu without regressions.

It's a good cleanup.  Please commit.


r~
Uros Bizjak Sept. 26, 2010, 6:30 p.m. UTC | #2 
On Sun, Sep 26, 2010 at 8:08 PM, Richard Henderson <rth@redhat.com> wrote:
> On 09/26/2010 09:35 AM, Uros Bizjak wrote:
>>> +(define_insn "pro_epilogue_adjust_stack_<mode>_2"
>>> +  [(set (match_operand:P 0 "register_operand" "=r")
>>> +    (plus:P (match_operand:DI 1 "register_operand" "0")
>>> +             (match_operand:DI 2 "register_operand" "r")))
>>>     (clobber (reg:CC FLAGS_REG))
>>>     (clobber (mem:BLK (scratch)))]
>>
>> Hm, this can't be right for Pmode == SImode.
>
> Oh shoot.  I fixed that in one tree, but failed to push that
> back to the copy from which I pushed the change.
>
>> Attached [RFC] patch implements this merge, and some related cleanups
>> involving renames and indirect functions. Patch was tested on
>> x86_64-pc-linux-gnu without regressions.
>
> It's a good cleanup.  Please commit.

Committed with following ChangeLog:

2010-09-26  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (pro_epilogue_adjust_stack_<mode>_add): Merge
	from pro_epilogue_adjust_stack_<mode>_{1,2}.
	(pro_epilogue_adjust_stack_<mode>_add): Rename from
	pro_epilogue_adjust_stack_<mode>_3.
	* config/i386/i386.c (pro_epilogue_adjust_stack): Update for
	renamed pro_epilogue_adjust_stack_{si,di}_add.
	(ix86_expand_prologue): Use indirect functions.  Update for renamed
	pro_epilogue_adjust_stack_{si,di}_sub.

Uros.
diff mbox

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 164630)
+++ i386.md	(working copy)
@@ -16246,10 +16246,10 @@ 
 ;;
 ;; in proper program order.
 
-(define_insn "pro_epilogue_adjust_stack_<mode>_1"
+(define_insn "pro_epilogue_adjust_stack_<mode>_add"
   [(set (match_operand:P 0 "register_operand" "=r,r")
 	(plus:P (match_operand:P 1 "register_operand" "0,r")
-	        (match_operand:P 2 "<immediate_operand>" "<i>,<i>")))
+	        (match_operand:P 2 "<nonmemory_operand>" "r<i>,l<i>")))
    (clobber (reg:CC FLAGS_REG))
    (clobber (mem:BLK (scratch)))]
   ""
@@ -16289,18 +16289,7 @@ 
 	      (const_string "*")))
    (set_attr "mode" "<MODE>")])
 
-(define_insn "pro_epilogue_adjust_stack_<mode>_2"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(plus:P (match_operand:DI 1 "register_operand" "0")
-		 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC FLAGS_REG))
-   (clobber (mem:BLK (scratch)))]
-  ""
-  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "pro_epilogue_adjust_stack_<mode>_3"
+(define_insn "pro_epilogue_adjust_stack_<mode>_sub"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(minus:P (match_operand:P 1 "register_operand" "0")
 		 (match_operand:P 2 "register_operand" "r")))
Index: i386.c
===================================================================
--- i386.c	(revision 164630)
+++ i386.c	(working copy)
@@ -8777,9 +8777,11 @@  pro_epilogue_adjust_stack (rtx dest, rtx
   rtx insn;
 
   if (! TARGET_64BIT)
-    insn = emit_insn (gen_pro_epilogue_adjust_stack_si_1 (dest, src, offset));
+    insn = emit_insn (gen_pro_epilogue_adjust_stack_si_add (dest,
+							    src, offset));
   else if (x86_64_immediate_operand (offset, DImode))
-    insn = emit_insn (gen_pro_epilogue_adjust_stack_di_1 (dest, src, offset));
+    insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest,
+							    src, offset));
   else
     {
       rtx tmp;
@@ -8796,7 +8798,7 @@  pro_epilogue_adjust_stack (rtx dest, rtx
       insn = emit_insn (gen_rtx_SET (DImode, tmp, offset));
       if (style < 0)
 	RTX_FRAME_RELATED_P (insn) = 1;
-      insn = emit_insn (gen_pro_epilogue_adjust_stack_di_2 (dest, src, tmp));
+      insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp));
     }
 
   if (style >= 0)
@@ -9698,6 +9700,8 @@  ix86_expand_prologue (void)
     {
       rtx eax = gen_rtx_REG (Pmode, AX_REG);
       rtx r10 = NULL;
+      rtx (*adjust_stack_insn)(rtx, rtx, rtx);
+
       bool eax_live = false;
       bool r10_live = false;
 
@@ -9722,13 +9726,12 @@  ix86_expand_prologue (void)
       emit_insn (ix86_gen_allocate_stack_worker (eax, eax));
 
       /* Use the fact that AX still contains ALLOCATE.  */
-      if (TARGET_64BIT)
-	insn = gen_pro_epilogue_adjust_stack_di_3 (stack_pointer_rtx,
-					           stack_pointer_rtx, eax);
-      else
-	insn = gen_pro_epilogue_adjust_stack_si_3 (stack_pointer_rtx,
-					           stack_pointer_rtx, eax);
-      insn = emit_insn (insn);
+      adjust_stack_insn = (TARGET_64BIT
+			   ? gen_pro_epilogue_adjust_stack_di_sub
+			   : gen_pro_epilogue_adjust_stack_si_sub);
+
+      insn = emit_insn (adjust_stack_insn (stack_pointer_rtx,
+					   stack_pointer_rtx, eax));
 
       if (m->fs.cfa_reg == stack_pointer_rtx)
 	{