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[v2,1/3] target-m68k: add abcd/sbcd/nbcd

Message ID 1478121319-31986-2-git-send-email-laurent@vivier.eu
State New
Headers show

Commit Message

Laurent Vivier Nov. 2, 2016, 9:15 p.m. UTC 
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c | 242 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 242 insertions(+)

Comments

Richard Henderson Nov. 3, 2016, 4:16 p.m. UTC | #1 
On 11/02/2016 03:15 PM, Laurent Vivier wrote:
> +static void bcd_sub(TCGv dest, TCGv src)
> +{
> +    TCGv t0, t1, t2;
> +
> +    /*  dest10 = dest10 - src10 - X
> +     *         = bcd_add(dest + 1 - X, 0xf99 - src)
> +     */
> +
> +    /* t0 = 0xfff - src */
> +
> +    t0 = tcg_temp_new();
> +    tcg_gen_neg_i32(t0, src);
> +    tcg_gen_addi_i32(t0, t0, 0xfff);

tcg_gen_subfi_i32(t0, 0xfff, src);

And how did we get 0xfff from 0xf99?  Also, see below...

> +
> +    /* t1 = t0 + dest + 1 - X*/
> +
> +    t1 = tcg_temp_new();
> +    tcg_gen_add_i32(t1, t0, dest);
> +    tcg_gen_addi_i32(t1, t1, 1);
> +    tcg_gen_sub_i32(t1, t1, QREG_CC_X);
> +
> +    /* t2 = t0 ^ dest ^ 1 ^ X */
> +
> +    t2 = tcg_temp_new();
> +    tcg_gen_xor_i32(t2, t0, dest);
> +    tcg_gen_xori_i32(t2, t2, 1);
> +    tcg_gen_xor_i32(t2, t2, QREG_CC_X);

Since you only care about bits 0x110, you can drop the ^ 1 ^ X; they won't 
affect the result.  (Similarly wrt bcd_add, dropping ^ X).

> +    /* t2 = ~t0 & 0x110 */
> +
> +    tcg_gen_not_i32(t2, t0);
> +    tcg_gen_andi_i32(t2, t2, 0x110);
> +
> +    /* t0 = (t2 >> 2) | (t2 >> 3) */
> +
> +    tcg_gen_shri_i32(t0, t2, 2);
> +    tcg_gen_shri_i32(t2, t2, 3);
> +    tcg_gen_or_i32(t0, t0, t2);

For the benefit of hosts that have 8-bit immediate AND insns (e.g. arm32), it 
would be better to rearrange this a little:

     t2 = t0 >> 3;
     t3 = ~t2 & 0x22;
     t4 = t3 + t3;
     t5 = t3 + t4;

(Similarly in bcd_add).

> +
> +    /* return t1 - t0 */
> +
> +    tcg_gen_sub_i32(dest, t1, t0);
> +}
> +
> +static void bcd_flags(TCGv val)
> +{
> +    tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
> +    tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
> +
> +    tcg_gen_movi_i32(QREG_CC_X, 0);
> +    tcg_gen_andi_i32(val, val, 0xf00);
> +    tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_C, val, QREG_CC_X);

Surely 0x100 is the carry.  I don't see how you could produce 0x2xx from 
addition.  For subtraction, I think we got things other than 0/1 in the third 
nibble simply because we started with 0xf99 instead of 0x199.


r~
diff mbox

Patch

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d0a3b0f..1cf88a4 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1313,6 +1313,243 @@  DISAS_INSN(divl)
     set_cc_op(s, CC_OP_FLAGS);
 }
 
+static void bcd_add(TCGv dest, TCGv src)
+{
+    TCGv t0, t1;
+
+    /*  dest10 = dest10 + src10 + X
+     *
+     *        t1 = src
+     *        t2 = t1 + 0x066
+     *        t3 = t2 + dest + X
+     *        t4 = t2 ^ dest ^ X
+     *        t5 = t3 ^ t4
+     *        t6 = ~t5 & 0x110
+     *        t7 = (t6 >> 2) | (t6 >> 3)
+     *        return t3 - t7
+     */
+
+    /* t1 = (src + 0x066) + dest + X
+     *    = result with some possible exceding 0x6
+     */
+
+    t0 = tcg_const_i32(0x066);
+    tcg_gen_add_i32(t0, t0, src);
+
+    t1 = tcg_temp_new();
+    tcg_gen_add_i32(t1, t0, dest);
+    tcg_gen_add_i32(t1, t1, QREG_CC_X);
+
+    /* we will remove exceding 0x6 where there is no carry */
+
+    /* t0 = (src + 0x0066) ^ dest ^ X
+     *    = t1 without carries
+     */
+
+    tcg_gen_xor_i32(t0, t0, dest);
+    tcg_gen_xor_i32(t0, t0, QREG_CC_X);
+
+    /* extract the carries
+     * t0 = t0 ^ t1
+     *    = only the carries
+     */
+
+    tcg_gen_xor_i32(t0, t0, t1);
+
+    /* generate 0x1 where there is no carry */
+
+    tcg_gen_not_i32(t0, t0);
+    tcg_gen_andi_i32(t0, t0, 0x110);
+
+    /* for each 0x10, generate a 0x6 */
+
+    tcg_gen_shri_i32(dest, t0, 2);
+    tcg_gen_shri_i32(t0, t0, 3);
+    tcg_gen_or_i32(dest, dest, t0);
+    tcg_temp_free(t0);
+
+    /* remove the exceding 0x6
+     * for digits that have not generated a carry
+     */
+
+    tcg_gen_sub_i32(dest, t1, dest);
+    tcg_temp_free(t1);
+}
+
+static void bcd_sub(TCGv dest, TCGv src)
+{
+    TCGv t0, t1, t2;
+
+    /*  dest10 = dest10 - src10 - X
+     *         = bcd_add(dest + 1 - X, 0xf99 - src)
+     */
+
+    /* t0 = 0xfff - src */
+
+    t0 = tcg_temp_new();
+    tcg_gen_neg_i32(t0, src);
+    tcg_gen_addi_i32(t0, t0, 0xfff);
+
+    /* t1 = t0 + dest + 1 - X*/
+
+    t1 = tcg_temp_new();
+    tcg_gen_add_i32(t1, t0, dest);
+    tcg_gen_addi_i32(t1, t1, 1);
+    tcg_gen_sub_i32(t1, t1, QREG_CC_X);
+
+    /* t2 = t0 ^ dest ^ 1 ^ X */
+
+    t2 = tcg_temp_new();
+    tcg_gen_xor_i32(t2, t0, dest);
+    tcg_gen_xori_i32(t2, t2, 1);
+    tcg_gen_xor_i32(t2, t2, QREG_CC_X);
+
+    /* t0 = t1 ^ t2 */
+
+    tcg_gen_xor_i32(t0, t1, t2);
+
+    /* t2 = ~t0 & 0x110 */
+
+    tcg_gen_not_i32(t2, t0);
+    tcg_gen_andi_i32(t2, t2, 0x110);
+
+    /* t0 = (t2 >> 2) | (t2 >> 3) */
+
+    tcg_gen_shri_i32(t0, t2, 2);
+    tcg_gen_shri_i32(t2, t2, 3);
+    tcg_gen_or_i32(t0, t0, t2);
+
+    /* return t1 - t0 */
+
+    tcg_gen_sub_i32(dest, t1, t0);
+}
+
+static void bcd_flags(TCGv val)
+{
+    tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
+    tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
+
+    tcg_gen_movi_i32(QREG_CC_X, 0);
+    tcg_gen_andi_i32(val, val, 0xf00);
+    tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_C, val, QREG_CC_X);
+
+    tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
+}
+
+DISAS_INSN(abcd_reg)
+{
+    TCGv src;
+    TCGv dest;
+
+    gen_flush_flags(s); /* !Z is sticky */
+
+    src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
+    dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
+    bcd_add(dest, src);
+    gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
+
+    bcd_flags(dest);
+}
+
+DISAS_INSN(abcd_mem)
+{
+    TCGv src;
+    TCGv addr_src;
+    TCGv dest;
+    TCGv addr_dest;
+
+    gen_flush_flags(s); /* !Z is sticky */
+
+    addr_src = tcg_temp_new();
+    tcg_gen_subi_i32(addr_src, AREG(insn, 0), opsize_bytes(OS_BYTE));
+    src = gen_load(s, OS_BYTE, addr_src, 0);
+
+    addr_dest = tcg_temp_new();
+    if (REG(insn, 0) == REG(insn, 9)) {
+        tcg_gen_subi_i32(addr_dest, addr_src, opsize_bytes(OS_BYTE));
+    } else {
+        tcg_gen_subi_i32(addr_dest, AREG(insn, 9), opsize_bytes(OS_BYTE));
+    }
+    dest = gen_load(s, OS_BYTE, addr_dest, 0);
+
+    bcd_add(dest, src);
+
+    gen_store(s, OS_BYTE, addr_dest, dest);
+
+    tcg_gen_mov_i32(AREG(insn, 0), addr_src);
+    tcg_temp_free(addr_src);
+    tcg_gen_mov_i32(AREG(insn, 9), addr_dest);
+    tcg_temp_free(addr_dest);
+
+    bcd_flags(dest);
+}
+
+DISAS_INSN(sbcd_reg)
+{
+    TCGv src, dest;
+
+    gen_flush_flags(s); /* !Z is sticky */
+
+    src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
+    dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
+
+    bcd_sub(dest, src);
+
+    gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
+
+    bcd_flags(dest);
+}
+
+DISAS_INSN(sbcd_mem)
+{
+    TCGv src, dest;
+    TCGv addr_src, addr_dest;
+
+    gen_flush_flags(s); /* !Z is sticky */
+
+    addr_src = tcg_temp_new();
+    tcg_gen_subi_i32(addr_src, AREG(insn, 0), opsize_bytes(OS_BYTE));
+    src = gen_load(s, OS_BYTE, addr_src, 0);
+
+    addr_dest = tcg_temp_new();
+    if (REG(insn, 0) == REG(insn, 9)) {
+        tcg_gen_subi_i32(addr_dest, addr_src, opsize_bytes(OS_BYTE));
+    } else {
+        tcg_gen_subi_i32(addr_dest, AREG(insn, 9), opsize_bytes(OS_BYTE));
+    }
+    dest = gen_load(s, OS_BYTE, addr_dest, 0);
+
+    bcd_sub(dest, src);
+
+    gen_store(s, OS_BYTE, addr_dest, dest);
+
+    tcg_gen_mov_i32(AREG(insn, 0), addr_src);
+    tcg_temp_free(addr_src);
+    tcg_gen_mov_i32(AREG(insn, 9), addr_dest);
+    tcg_temp_free(addr_dest);
+
+    bcd_flags(dest);
+}
+
+DISAS_INSN(nbcd)
+{
+    TCGv src, dest;
+    TCGv addr;
+
+    gen_flush_flags(s); /* !Z is sticky */
+
+    SRC_EA(env, src, OS_BYTE, 0, &addr);
+
+    dest = tcg_const_i32(0);
+    bcd_sub(dest, src);
+
+    DEST_EA(env, insn, OS_BYTE, dest, &addr);
+
+    bcd_flags(dest);
+
+    tcg_temp_free(dest);
+}
+
 DISAS_INSN(addsub)
 {
     TCGv reg;
@@ -3616,6 +3853,7 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(not,       4600, ff00, M68000);
     INSN(undef,     46c0, ffc0, M68000);
     INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
+    INSN(nbcd,      4800, ffc0, M68000);
     INSN(linkl,     4808, fff8, M68000);
     BASE(pea,       4840, ffc0);
     BASE(swap,      4840, fff8);
@@ -3667,6 +3905,8 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(mvzs,      7100, f100, CF_ISA_B);
     BASE(or,        8000, f000);
     BASE(divw,      80c0, f0c0);
+    INSN(sbcd_reg,  8100, f1f8, M68000);
+    INSN(sbcd_mem,  8108, f1f8, M68000);
     BASE(addsub,    9000, f000);
     INSN(undef,     90c0, f0c0, CF_ISA_A);
     INSN(subx_reg,  9180, f1f8, CF_ISA_A);
@@ -3704,6 +3944,8 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(exg_aa,    c148, f1f8, M68000);
     INSN(exg_da,    c188, f1f8, M68000);
     BASE(mulw,      c0c0, f0c0);
+    INSN(abcd_reg,  c100, f1f8, M68000);
+    INSN(abcd_mem,  c108, f1f8, M68000);
     BASE(addsub,    d000, f000);
     INSN(undef,     d0c0, f0c0, CF_ISA_A);
     INSN(addx_reg,      d180, f1f8, CF_ISA_A);