diff mbox

[vect] Ask for review and approving the patch about vect and loongson

Message ID AANLkTikTbrcXwEk30AD_X_g0gWiZhFdvtv=juwcdAU6L@mail.gmail.com
State New
Headers show

Commit Message

Mingjie Xing Aug. 13, 2010, 5:59 a.m. UTC 
Hello,

> Eric Fisher <joefoxreal@gmail.com> writes:
>> Thanks. I've updated the patch in the attachment.
>
> Watch the formatting: the (match_operand: ...)s should line up vertically.
>
> The patch is OK with that change.  Obviously we'll have to wait until
> the copyright assignment is sorted out before the patches can be applied.
>
> Richard
>

My GCC assignment/disclaimer process with the FSF is currently
complete. I've put the previously reviewed patches in the attachment
and changed the contact also.

Mingjie Xing  <mingjie.xing@gmail.com>

gcc/ChangeLog
 * loongson.md: Change define_insn "loongson_pmull<V_suffix>" to "mul<mode>3".
 * mips.c: Add "#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3".

testsuite/ChangeLog
 * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
 * vect.exp: Run the vect testsuite when the target is loongson*
 * target-supports.exp: Check loongson target in vector specific attributes.

BTW, I don't have write access to svn.

Regards,
Mingjie

Comments

Richard Sandiford Aug. 14, 2010, 7:53 p.m. UTC | #1 
Mingjie Xing <mingjie.xing@gmail.com> writes:
> My GCC assignment/disclaimer process with the FSF is currently
> complete. I've put the previously reviewed patches in the attachment
> and changed the contact also.

Great!  Thanks for contributions, and for seeing this through.

I've applied loongson_mult.patch, fast-math-vect-reduc-8.patch and
target-supports.patch.  Uros is right about the other vect.exps;
sorry for not catching that.

Richard
diff mbox

Patch

Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 163219)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1620,7 +1620,9 @@  proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+	      || ([istarget mips*-*-*]
+	           && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2156,7 +2158,9 @@  proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2270,7 +2274,9 @@  proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2643,7 +2649,9 @@  proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2833,8 +2841,10 @@  proc check_effective_target_vect_short_m
 	     || [istarget spu-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-             || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+	     || [istarget powerpc*-*-*]
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }