@@ -42,7 +42,7 @@ along with GCC; see the file COPYING3.
struct target_expmed default_target_expmed;
#if SWITCHABLE_TARGET
-struct target_expmed *this_target_expmed;
+struct target_expmed *this_target_expmed = &default_target_expmed;
#endif
static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
@@ -27,7 +27,7 @@ struct target_gcse {
/* Nonzero for each mode that supports (set (reg) (reg)).
This is trivially true for integer and floating point values.
It may or may not be true for condition codes. */
- int x_can_copy[(int) NUM_MACHINE_MODES];
+ char x_can_copy[(int) NUM_MACHINE_MODES];
/* True if the previous field has been initialized. */
bool x_can_copy_init_p;
@@ -575,10 +575,6 @@ hard_reg_set_iter_next (hard_reg_set_ite
/* Define some standard sets of registers. */
-/* For each reg class, a boolean saying whether the class contains only
- fixed registers. */
-extern bool class_only_fixed_regs[N_REG_CLASSES];
-
/* Indexed by hard register number, contains 1 for registers
that are being used for global register decls.
These must be exempt from ordinary flow analysis
@@ -634,6 +630,10 @@ struct target_hard_regs {
/* For each reg class, a HARD_REG_SET saying which registers are in it. */
HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
+ /* For each reg class, a boolean saying whether the class contains only
+ fixed registers. */
+ bool x_class_only_fixed_regs[N_REG_CLASSES];
+
/* For each reg class, number of regs it contains. */
unsigned int x_reg_class_size[N_REG_CLASSES];
@@ -681,6 +681,8 @@ extern struct target_hard_regs *this_tar
(this_target_hard_regs->x_inv_reg_alloc_order)
#define reg_class_contents \
(this_target_hard_regs->x_reg_class_contents)
+#define class_only_fixed_regs \
+ (this_target_hard_regs->x_class_only_fixed_regs)
#define reg_class_size \
(this_target_hard_regs->x_reg_class_size)
#define reg_class_subclasses \
@@ -328,8 +328,8 @@ along with GCC; see the file COPYING3.
struct target_ira default_target_ira;
struct target_ira_int default_target_ira_int;
#if SWITCHABLE_TARGET
-struct target_ira *this_target_ira;
-struct target_ira_int *this_target_ira_int;
+struct target_ira *this_target_ira = &default_target_ira;
+struct target_ira_int *this_target_ira_int = &default_target_ira_int;
#endif
/* A modified value of flag `-fira-verbose' used internally. */
@@ -48,8 +48,8 @@ along with GCC; see the file COPYING3.
struct target_optabs default_target_optabs;
struct target_libfuncs default_target_libfuncs;
#if SWITCHABLE_TARGET
-struct target_optabs *this_target_optabs;
-struct target_libfuncs *this_target_libfuncs;
+struct target_optabs *this_target_optabs = &default_target_optabs;
+struct target_libfuncs *this_target_libfuncs = &default_target_libfuncs;
#endif
#define libfunc_hash \
@@ -101,10 +101,6 @@ static bitmap_obstack persistent_obstack
static int initial_reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
#endif
-/* For each reg class, a boolean saying whether the class contains only
- fixed registers. */
-bool class_only_fixed_regs[N_REG_CLASSES];
-
/* The same information, but as an array of unsigned ints. We copy from
these unsigned ints to the table above. We do this so the tm.h files
do not have to be aware of the wordsize for machines with <= 64 regs.