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ARM patch: Add a Thumb-1 ldrsb peephole

Message ID 4C36F592.6040901@codesourcery.com
State New
Headers show

Commit Message

Bernd Schmidt July 9, 2010, 10:10 a.m. UTC 
Here's a small by-product of my attempts to tune Thumb-1 code.

-       add     r3, r3, #124
-       mov     r7, #0
+       mov     r7, #124
        ldrsb   r7, [r3, r7]

Tested in the same run as mentioned in
  http://gcc.gnu.org/ml/gcc-patches/2010-07/msg00756.html

Ok?


Bernd
* config/arm/arm.md (Thumb-1 ldrsb peephole): New.

Comments

Richard Earnshaw July 9, 2010, 10:24 a.m. UTC | #1 
On Fri, 2010-07-09 at 12:10 +0200, Bernd Schmidt wrote:
> Here's a small by-product of my attempts to tune Thumb-1 code.
> 
> -       add     r3, r3, #124
> -       mov     r7, #0
> +       mov     r7, #124
>         ldrsb   r7, [r3, r7]
> 
> Tested in the same run as mentioned in
>   http://gcc.gnu.org/ml/gcc-patches/2010-07/msg00756.html
> 
> Ok?
> 

This is OK.

Hmm, makes me think.  Could we also have a peephole to optimize the
thumb-2 case?

	add	r3, r3, r4
	ldrsb	r7, [r3, #124] // 32-bit, r3 dead

into
	add	r3, r3, #124
	ldrsb	r7, [r3, r4]  // 16-bit
diff mbox

Patch

Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 161987)
+++ config/arm/arm.md	(working copy)
@@ -4619,6 +4619,27 @@  (define_split
   operands[3] = change_address (operands[1], QImode, addr);
 })
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (match_dup 0) (match_operand 1 "const_int_operand")))
+   (set (match_operand:SI 2 "register_operand" "") (const_int 0))
+   (set (match_operand:SI 3 "register_operand" "")
+	(sign_extend:SI (match_operand:QI 4 "memory_operand" "")))]
+  "TARGET_THUMB1
+   && GET_CODE (XEXP (operands[4], 0)) == PLUS
+   && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0))
+   && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1))
+   && (peep2_reg_dead_p (3, operands[0])
+       || rtx_equal_p (operands[0], operands[3]))
+   && (peep2_reg_dead_p (3, operands[2])
+       || rtx_equal_p (operands[2], operands[3]))"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 3) (sign_extend:SI (match_dup 4)))]
+{
+  rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
+  operands[4] = change_address (operands[4], QImode, addr);
+})
+
 (define_insn "thumb1_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=l,l,l")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]