diff mbox

ARM improvements for GCSE

Message ID 4C227355.60505@codesourcery.com
State New
Headers show

Commit Message

Maxim Kuvyrkov June 23, 2010, 8:49 p.m. UTC 
This patch improves handling of "J" and "K" constants.

If a pseudo assigned a constant and set only once, IRA/reload can 
rematerialize it to decrease high register pressure.

OK to check in?

Comments

Richard Earnshaw June 24, 2010, 10:22 a.m. UTC | #1 
On Thu, 2010-06-24 at 00:49 +0400, Maxim Kuvyrkov wrote:
> This patch improves handling of "J" and "K" constants.
> 
> If a pseudo assigned a constant and set only once, IRA/reload can 
> rematerialize it to decrease high register pressure.
> 
> OK to check in?


OK.

R.
diff mbox

Patch

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 5057bac..5671587 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6931,6 +6931,10 @@  thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
         {
           if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
             return 0;
+	  /* See split "TARGET_THUMB1 && satisfies_constraint_J".  */
+	  if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
+            return COSTS_N_INSNS (2);
+	  /* See split "TARGET_THUMB1 && satisfies_constraint_K".  */
           if (thumb_shiftable_const (INTVAL (x)))
             return COSTS_N_INSNS (2);
           return COSTS_N_INSNS (3);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 628bd62..b6cca49 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5191,17 +5191,21 @@ 
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_operand:SI 1 "const_int_operand" ""))]
   "TARGET_THUMB1 && satisfies_constraint_J (operands[1])"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (neg:SI (match_dup 0)))]
-  "operands[1] = GEN_INT (- INTVAL (operands[1]));"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (neg:SI (match_dup 2)))]
+  "
+  {
+    operands[1] = GEN_INT (- INTVAL (operands[1]));
+    operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
+  }"
 )
 
 (define_split 
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_operand:SI 1 "const_int_operand" ""))]
   "TARGET_THUMB1 && satisfies_constraint_K (operands[1])"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))]
   "
   {
     unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu;
@@ -5212,12 +5216,13 @@ 
       if ((val & (mask << i)) == val)
         break;
 
-    /* Shouldn't happen, but we don't want to split if the shift is zero.  */
+    /* Don't split if the shift is zero.  */
     if (i == 0)
       FAIL;
 
     operands[1] = GEN_INT (val >> i);
-    operands[2] = GEN_INT (i);
+    operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
+    operands[3] = GEN_INT (i);
   }"
 )