Message ID | 1442142873-20213-4-git-send-email-marc.zyngier@arm.com |
---|---|
State | New |
Headers | show |
Hello! > From: Pavel Fedin <p.fedin@samsung.com> > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: Thank you for the cooperation, i'm now back from my vacation. What about the first patch in the series, which actually enables GICv2m on 32 bits? I don't see it anywhere, neither there are reviews. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia
On Thu, 24 Sep 2015 11:19:33 +0300 Pavel Fedin <p.fedin@samsung.com> wrote: > Hello! > > > From: Pavel Fedin <p.fedin@samsung.com> > > > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: > > Thank you for the cooperation, i'm now back from my vacation. > What about the first patch in the series, which actually enables > GICv2m on 32 bits? I don't see it anywhere, neither there are reviews. This is a patch that touches arch/arm, so this is Russell that you have to convince, not me. Thanks, M.
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index db04fc1..12985da 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -95,8 +95,8 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) struct v2m_data *v2m = irq_data_get_irq_chip_data(data); phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS; - msg->address_hi = (u32) (addr >> 32); - msg->address_lo = (u32) (addr); + msg->address_hi = upper_32_bits(addr); + msg->address_lo = lower_32_bits(addr); msg->data = data->hwirq; }