| Message ID | 20100301191351.20987.49730.sendpatchset@norville.austin.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Josh Boyer |
| Headers | show |
On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote: >powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > >From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > >There are still some unstable bits on the DD1 and DD1.1 cores. Don't use >the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and >CPU_FTR_476_DD1_1 for additional workarounds in later patches. > >The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 >and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 >defined. DD1, DD1.1, and all others have the same PVR value? How do you tell which core version you have? josh
On Mon, 2010-03-01 at 15:24 -0500, Josh Boyer wrote: > On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote: > >powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > > > >From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > > >There are still some unstable bits on the DD1 and DD1.1 cores. Don't use > >the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and > >CPU_FTR_476_DD1_1 for additional workarounds in later patches. > > > >The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 > >and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 > >defined. > > DD1, DD1.1, and all others have the same PVR value? How do you tell which > core version you have? I seemed to have lost the change to the DD1.1 PVR value. I originally coded it this way while I was waiting to find out what it was. DD1.1 is 0x11A52040. I don't know a value for the future versions, so that will have to be filled in later. Actually, I should probably use 0x11A52000, since that's what's defined in reg.h. Thanks, Shaggy
On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp <shaggy@linux.vnet.ibm.com>wrote: > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > There are still some unstable bits on the DD1 and DD1.1 cores. Don't use > the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and > CPU_FTR_476_DD1_1 for additional workarounds in later patches. > > The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 > and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 > defined. > > Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... -Hollis
On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote: > On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp <shaggy@linux.vnet.ibm.com> wrote: > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > There are still some unstable bits on the DD1 and DD1.1 cores. Don't use > the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and > CPU_FTR_476_DD1_1 for additional workarounds in later patches. > > The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 > and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 > defined. > > Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... > > -Hollis I'm with Hollis. Cluttering the code with non-production errata could get very ugly as well as burning feature bits up like made. - k
On Fri, 2010-03-05 at 03:15 -0600, Kumar Gala wrote: > On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote: > > > On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp <shaggy@linux.vnet.ibm.com> wrote: > > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > > > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > > > There are still some unstable bits on the DD1 and DD1.1 cores. Don't use > > the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and > > CPU_FTR_476_DD1_1 for additional workarounds in later patches. > > > > The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 > > and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 > > defined. > > > > Isn't the policy generally not to commit workarounds for > early/errataful hardware which will not be seen in the real world? > Otherwise, every new half-broken core could burn a bunch of feature > bits... > > > > -Hollis > > I'm with Hollis. Cluttering the code with non-production errata could > get very ugly as well as burning feature bits up like made. Ben's going to make the decision on whether or not these patches should be included into mainline. I'd be happy maintaining them separately if not. I'm separating out the DD1 workaround from the others, since it's less likely that one will be needed long-term. Thanks, Shaggy
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 9fff628..d28eaf7 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -153,8 +153,10 @@ extern const char *powerpc_base_platform; #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) +#define CPU_FTR_476_DD1 ASM_CONST(0x0000000000010000) #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) +#define CPU_FTR_476_DD1_1 ASM_CONST(0x0000000000080000) #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index a06e6d3..0ea9134 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1701,15 +1701,29 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_440A, .platform = "ppc440", }, - { /* 476 core */ + { /* 476 DD1 core - needs DD1.1 feature as well */ .pvr_mask = 0xffff0000, .pvr_value = 0x11a50000, .cpu_name = "476", - .cpu_features = CPU_FTRS_47X, - .cpu_user_features = COMMON_USER_BOOKE | - PPC_FEATURE_HAS_FPU, + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1 | + CPU_FTR_476_DD1_1 | CPU_FTR_FPU_UNAVAILABLE, + .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_47x | - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, + MMU_FTR_LOCK_BCAST_INVAL, + .icache_bsize = 32, + .dcache_bsize = 128, + .machine_check = machine_check_47x, + .platform = "ppc470", + }, + { /* 476 DD1.1 core */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x11a50000, + .cpu_name = "476", + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 | + CPU_FTR_FPU_UNAVAILABLE, + .cpu_user_features = COMMON_USER_BOOKE, + .mmu_features = MMU_FTR_TYPE_47x | + MMU_FTR_LOCK_BCAST_INVAL, .icache_bsize = 32, .dcache_bsize = 128, .machine_check = machine_check_47x, @@ -1724,6 +1738,20 @@ static struct cpu_spec __initdata cpu_specs[] = { PPC_FEATURE_HAS_FPU, .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_47x | + MMU_FTR_LOCK_BCAST_INVAL, + .icache_bsize = 32, + .dcache_bsize = 128, + .machine_check = machine_check_47x, + .platform = "ppc470", + }, + { /* 476 others */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x11a50000, + .cpu_name = "476", + .cpu_features = CPU_FTRS_47X, + .cpu_user_features = COMMON_USER_BOOKE | + PPC_FEATURE_HAS_FPU, + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, .icache_bsize = 32, .dcache_bsize = 128,