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[U-Boot] arm: socfpga: Assure ISWGRP 0 and 1 are inited

Message ID 1440409906-18892-1-git-send-email-marex@denx.de
State Accepted
Delegated to: Marek Vasut
Headers show

Commit Message

Marek Vasut Aug. 24, 2015, 9:51 a.m. UTC 
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/reset_manager.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Marek Vasut Aug. 24, 2015, 5:40 p.m. UTC | #1 
On Monday, August 24, 2015 at 11:51:46 AM, Marek Vasut wrote:
> This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
> correctly inited. In case those registers are not initialized,
> it is not possible to access the registers synthesised in the
> FPGA through the bridges. Any such access produces data abort.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Since this fixes an actual issue, applied.

Best regards,
Marek Vasut
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Patch

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 1186358..b6beaa2 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -7,13 +7,16 @@ 
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
@@ -97,6 +100,9 @@  void socfpga_bridges_reset(int enable)
 		/* brdmodrst */
 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
 	} else {
+		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
+		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+
 		/* Check signal from FPGA. */
 		if (!fpgamgr_test_fpga_ready()) {
 			/* FPGA not ready, do nothing. */