| Message ID | 1263297526-13518-5-git-send-email-agraf@suse.de |
|---|---|
| State | New |
| Headers | show |
On Tue, Jan 12, 2010 at 11:58 AM, Alexander Graf <agraf@suse.de> wrote: > To ease debugging and to know what we're lacking, I found it really useful to > have an lspci dump of a real U3 based G5 around. So I added a comment for it. > > If people don't think it's important enough to include this information in the > sources, just don't apply this patch. I think it would be useful, but the right place would be in ppc_newworld.c, because that is where the PCI bus is populated. For unin_pci.c, an interesting reference would be a link to the data sheet.
On 12.01.2010, at 21:16, Blue Swirl wrote: > On Tue, Jan 12, 2010 at 11:58 AM, Alexander Graf <agraf@suse.de> wrote: >> To ease debugging and to know what we're lacking, I found it really useful to >> have an lspci dump of a real U3 based G5 around. So I added a comment for it. >> >> If people don't think it's important enough to include this information in the >> sources, just don't apply this patch. > > I think it would be useful, but the right place would be in > ppc_newworld.c, because that is where the PCI bus is populated. Hum, that file is pretty cluttered already. How about we create a Documentation subdir in qemu that contains information about various devices? > For unin_pci.c, an interesting reference would be a link to the data sheet. I'm not aware of any. The only real specification I know of is for the U4. Alex
On Tue, Jan 12, 2010 at 8:35 PM, Alexander Graf <agraf@suse.de> wrote: > > On 12.01.2010, at 21:16, Blue Swirl wrote: > >> On Tue, Jan 12, 2010 at 11:58 AM, Alexander Graf <agraf@suse.de> wrote: >>> To ease debugging and to know what we're lacking, I found it really useful to >>> have an lspci dump of a real U3 based G5 around. So I added a comment for it. >>> >>> If people don't think it's important enough to include this information in the >>> sources, just don't apply this patch. >> >> I think it would be useful, but the right place would be in >> ppc_newworld.c, because that is where the PCI bus is populated. > > Hum, that file is pretty cluttered already. How about we create a Documentation subdir in qemu that contains information about various devices? Nobody reads documentation :) There's plenty of room near line 50, that's where I have put references in other files. >> For unin_pci.c, an interesting reference would be a link to the data sheet. > > I'm not aware of any. The only real specification I know of is for the U4. Then U4 may be a more interesting machine to be implemented than U3, at least if there are more documented devices or fewer critical undocumented devices.
On 12.01.2010, at 21:43, Blue Swirl wrote: > On Tue, Jan 12, 2010 at 8:35 PM, Alexander Graf <agraf@suse.de> wrote: >> >> On 12.01.2010, at 21:16, Blue Swirl wrote: >> >>> On Tue, Jan 12, 2010 at 11:58 AM, Alexander Graf <agraf@suse.de> wrote: >>>> To ease debugging and to know what we're lacking, I found it really useful to >>>> have an lspci dump of a real U3 based G5 around. So I added a comment for it. >>>> >>>> If people don't think it's important enough to include this information in the >>>> sources, just don't apply this patch. >>> >>> I think it would be useful, but the right place would be in >>> ppc_newworld.c, because that is where the PCI bus is populated. >> >> Hum, that file is pretty cluttered already. How about we create a Documentation subdir in qemu that contains information about various devices? > > Nobody reads documentation :) There's plenty of room near line 50, > that's where I have put references in other files. > >>> For unin_pci.c, an interesting reference would be a link to the data sheet. >> >> I'm not aware of any. The only real specification I know of is for the U4. > > Then U4 may be a more interesting machine to be implemented than U3, > at least if there are more documented devices or fewer critical > undocumented devices. The easy part about U3 is that it's accessed the same way as U2, so the PPC32 code can be reused. Eventually we need a U4 target though, especially since that also implements PCIe. For now it's one thing at a time - first a proof of concept for KVM and then a U4 :). Alex
diff --git a/hw/unin_pci.c b/hw/unin_pci.c index 8e1a471..1e32d63 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -244,6 +244,31 @@ PCIBus *pci_pmac_init(qemu_irq *pic) return d->host_state.bus; } +/* + * PCI bus layout on a real G5 (U3 based): + * + * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] + * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] + * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] + * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) + * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) + * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] + * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] + * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] + * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] + * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] + * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) + * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] + * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] + * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) + * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) + * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) + * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] + * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] + * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] + * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] + * + */ PCIBus *pci_pmac_u3_init(qemu_irq *pic) { DeviceState *dev;
To ease debugging and to know what we're lacking, I found it really useful to have an lspci dump of a real U3 based G5 around. So I added a comment for it. If people don't think it's important enough to include this information in the sources, just don't apply this patch. Signed-off-by: Alexander Graf <agraf@suse.de> --- hw/unin_pci.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-)