@@ -11,7 +11,7 @@
#include <asm/system.h>
-#ifndef CONFIG_ARM64
+#ifndef __aarch64__
/*
* Invalidate L2 Cache using co-proc instruction
@@ -10,7 +10,7 @@
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
#define CONFIG_PHYS_64BIT
#define CONFIG_STATIC_RELA
#endif
@@ -61,7 +61,7 @@ static inline gd_t *get_gd(void)
{
gd_t *gd_ptr;
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
/*
* Make will already error that reserving x18 is not supported at the
* time of writing, clang: error: unknown argument: '-ffixed-x18'
@@ -76,7 +76,7 @@ static inline gd_t *get_gd(void)
#else
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
#else
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
@@ -54,7 +54,7 @@
bcs 1b
.endm
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
/*
* Register aliases.
*/
@@ -198,7 +198,7 @@ lr .req x30
.endm
#endif
-#endif /* CONFIG_ARM64 */
+#endif /* __aarch64__ */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_MACRO_H__ */
@@ -10,7 +10,7 @@
#ifndef __ASM_PROC_PTRACE_H
#define __ASM_PROC_PTRACE_H
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
#define PCMASK 0
@@ -27,7 +27,7 @@ struct pt_regs {
#endif /* __ASSEMBLY__ */
-#else /* CONFIG_ARM64 */
+#else /* __aarch64__ */
#define USR26_MODE 0x00
#define FIQ26_MODE 0x01
@@ -125,6 +125,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_ARM64 */
+#endif /* __aarch64__ */
#endif
@@ -13,7 +13,7 @@
/*
* Save the current interrupt enable state & disable IRQs
*/
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
/*
* Save the current interrupt enable state
@@ -65,7 +65,7 @@
: "memory"); \
})
-#else /* CONFIG_ARM64 */
+#else /* __aarch64__ */
#define local_irq_save(x) \
({ \
@@ -161,10 +161,10 @@
: "r" (x) \
: "memory")
-#endif /* CONFIG_ARM64 */
+#endif /* __aarch64__ */
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
- defined(CONFIG_ARM64)
+ defined(__aarch64__)
/*
* On the StrongARM, "swp" is terminally broken since it bypasses the
* cache totally. This means that the cache becomes inconsistent, and,
@@ -1,7 +1,7 @@
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
/*
* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
@@ -80,7 +80,7 @@ void smp_kick_all_cpus(void);
#endif /* __ASSEMBLY__ */
-#else /* CONFIG_ARM64 */
+#else /* __aarch64__ */
#ifdef __KERNEL__
@@ -221,6 +221,6 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* __KERNEL__ */
-#endif /* CONFIG_ARM64 */
+#endif /* __aarch64__ */
#endif
@@ -39,11 +39,11 @@ typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
#define BITS_PER_LONG 64
-#else /* CONFIG_ARM64 */
+#else
#define BITS_PER_LONG 32
-#endif /* CONFIG_ARM64 */
+#endif
/* Dma addresses are 32-bits wide. */
@@ -52,7 +52,7 @@ void do_software_interrupt(struct pt_regs *pt_regs);
void do_prefetch_abort(struct pt_regs *pt_regs);
void do_data_abort(struct pt_regs *pt_regs);
void do_not_used(struct pt_regs *pt_regs);
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
void do_fiq(struct pt_regs *pt_regs, unsigned int esr);
void do_irq(struct pt_regs *pt_regs, unsigned int esr);
#else
@@ -43,7 +43,7 @@ typedef struct bd_info {
#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
-#ifndef CONFIG_ARM64
+#ifndef __aarch64__
#define IH_ARCH_DEFAULT IH_ARCH_ARM
#else
#define IH_ARCH_DEFAULT IH_ARCH_ARM64
@@ -401,7 +401,7 @@ void board_init_f(ulong bootflag)
}
#endif
-#ifndef CONFIG_ARM64
+#ifndef __aarch64__
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
@@ -414,10 +414,10 @@ void board_init_f(ulong bootflag)
/* 8-byte alignment for ABI compliance */
addr_sp &= ~0x07;
-#else /* CONFIG_ARM64 */
+#else
/* 16-byte alignment for ABI compliance */
addr_sp &= ~0x0f;
-#endif /* CONFIG_ARM64 */
+#endif
#else
addr_sp += 128; /* leave 32 words for abort-stack */
gd->irq_sp = addr_sp;
@@ -187,7 +187,7 @@ static void setup_end_tag(bd_t *bd)
__weak void setup_board_tags(struct tag **in_params) {}
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
static void do_nonsec_virt_switch(void)
{
smp_kick_all_cpus();
@@ -260,7 +260,7 @@ bool armv7_boot_nonsec(void)
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
void (*kernel_entry)(void *fdt_addr, void *res0, void *res1,
void *res2);
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
@@ -29,7 +29,7 @@
static long smh_trap(unsigned int sysnum, void *addr)
{
register long result asm("r0");
-#if defined(CONFIG_ARM64)
+#if defined(__aarch64__)
asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
#else
/* Note - untested placeholder */
@@ -595,7 +595,7 @@ static int reserve_stacks(void)
* TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
* to handle this and put in arch/xxx/lib/stack.c
*/
-# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+# if defined(CONFIG_ARM)
# ifdef CONFIG_USE_IRQ
gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
@@ -866,7 +866,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
int i;
#endif
-#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
gd = new_gd;
#endif
@@ -33,8 +33,8 @@ Notes
5. Generic board is supported.
-6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
- aarch32 specific codes.
+6. __arch64__ is used to distinguish aarch64 and aarch32 specific codes.
+ CONFIG_ARM64 is used in makefile to select specific source files.
Contributor
===========
@@ -277,7 +277,7 @@ struct smc91111_priv{
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
-#elif CONFIG_ARM64
+#elif __aarch64__
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
@@ -291,7 +291,7 @@ struct smc91111_priv{
({ (*((volatile word*)((a)->iobase+((r)))) = d); \
SSYNC(); \
})
-#elif CONFIG_ARM64
+#elif __aarch64__
#define SMC_outw(a, d, r) \
(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
#else
@@ -38,7 +38,7 @@ gd_t *global_data;
" bctr\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r11");
#elif defined(CONFIG_ARM)
-#ifdef CONFIG_ARM64
+#ifdef __aarch64__
/*
* x18 holds the pointer to the global_data, x9 is a call-clobbered
* register