[{"id":1961072,"web_url":"http://patchwork.ozlabs.org/comment/1961072/","msgid":"<20180725173919.0792b751@bbrezillon>","list_archive_url":null,"date":"2018-07-25T15:39:19","subject":"Re: [PATCH v5 04/17] mtd: rawnand: omap2: convert driver to\n\tnand_scan()","submitter":{"id":73370,"url":"http://patchwork.ozlabs.org/api/people/73370/","name":"Boris Brezillon","email":"boris.brezillon@bootlin.com"},"content":"On Wed, 25 Jul 2018 15:31:39 +0200\nMiquel Raynal <miquel.raynal@bootlin.com> wrote:\n\n> Two helpers have been added to the core to do all kind of controller\n> side configuration/initialization between the detection phase and the\n> final NAND scan. Implement these hooks so that we can convert the driver\n> to just use nand_scan() instead of the nand_scan_ident() +\n> nand_scan_tail() pair.\n> \n> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n\nReviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>\n\n> ---\n>  drivers/mtd/nand/raw/omap2.c | 533 +++++++++++++++++++++----------------------\n>  1 file changed, 265 insertions(+), 268 deletions(-)\n> \n> diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c\n> index e943b2e5a5e2..4546ac0bed4a 100644\n> --- a/drivers/mtd/nand/raw/omap2.c\n> +++ b/drivers/mtd/nand/raw/omap2.c\n> @@ -144,12 +144,6 @@ static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,\n>  \t0xac, 0x6b, 0xff, 0x99, 0x7b};\n>  static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};\n>  \n> -/* Shared among all NAND instances to synchronize access to the ECC Engine */\n> -static struct nand_controller omap_gpmc_controller = {\n> -\t.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),\n> -\t.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),\n> -};\n> -\n>  struct omap_nand_info {\n>  \tstruct nand_chip\t\tnand;\n>  \tstruct platform_device\t\t*pdev;\n> @@ -1915,17 +1909,278 @@ static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {\n>  \t.free = omap_sw_ooblayout_free,\n>  };\n>  \n> +static int omap_nand_attach_chip(struct nand_chip *chip)\n> +{\n> +\tstruct mtd_info *mtd = nand_to_mtd(chip);\n> +\tstruct omap_nand_info *info = mtd_to_omap(mtd);\n> +\tstruct device *dev = &info->pdev->dev;\n> +\tint min_oobbytes = BADBLOCK_MARKER_LENGTH;\n> +\tint oobbytes_per_step;\n> +\tdma_cap_mask_t mask;\n> +\tint err;\n> +\n> +\tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n> +\t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n> +\telse\n> +\t\tchip->options |= NAND_SKIP_BBTSCAN;\n> +\n> +\t/* Re-populate low-level callbacks based on xfer modes */\n> +\tswitch (info->xfer_type) {\n> +\tcase NAND_OMAP_PREFETCH_POLLED:\n> +\t\tchip->read_buf = omap_read_buf_pref;\n> +\t\tchip->write_buf = omap_write_buf_pref;\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_POLLED:\n> +\t\t/* Use nand_base defaults for {read,write}_buf */\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_PREFETCH_DMA:\n> +\t\tdma_cap_zero(mask);\n> +\t\tdma_cap_set(DMA_SLAVE, mask);\n> +\t\tinfo->dma = dma_request_chan(dev, \"rxtx\");\n> +\n> +\t\tif (IS_ERR(info->dma)) {\n> +\t\t\tdev_err(dev, \"DMA engine request failed\\n\");\n> +\t\t\treturn PTR_ERR(info->dma);\n> +\t\t} else {\n> +\t\t\tstruct dma_slave_config cfg;\n> +\n> +\t\t\tmemset(&cfg, 0, sizeof(cfg));\n> +\t\t\tcfg.src_addr = info->phys_base;\n> +\t\t\tcfg.dst_addr = info->phys_base;\n> +\t\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> +\t\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> +\t\t\tcfg.src_maxburst = 16;\n> +\t\t\tcfg.dst_maxburst = 16;\n> +\t\t\terr = dmaengine_slave_config(info->dma, &cfg);\n> +\t\t\tif (err) {\n> +\t\t\t\tdev_err(dev,\n> +\t\t\t\t\t\"DMA engine slave config failed: %d\\n\",\n> +\t\t\t\t\terr);\n> +\t\t\t\treturn err;\n> +\t\t\t}\n> +\t\t\tchip->read_buf = omap_read_buf_dma_pref;\n> +\t\t\tchip->write_buf = omap_write_buf_dma_pref;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_PREFETCH_IRQ:\n> +\t\tinfo->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);\n> +\t\tif (info->gpmc_irq_fifo <= 0) {\n> +\t\t\tdev_err(dev, \"Error getting fifo IRQ\\n\");\n> +\t\t\treturn -ENODEV;\n> +\t\t}\n> +\t\terr = devm_request_irq(dev, info->gpmc_irq_fifo,\n> +\t\t\t\t       omap_nand_irq, IRQF_SHARED,\n> +\t\t\t\t       \"gpmc-nand-fifo\", info);\n> +\t\tif (err) {\n> +\t\t\tdev_err(dev, \"Requesting IRQ %d, error %d\\n\",\n> +\t\t\t\tinfo->gpmc_irq_fifo, err);\n> +\t\t\tinfo->gpmc_irq_fifo = 0;\n> +\t\t\treturn err;\n> +\t\t}\n> +\n> +\t\tinfo->gpmc_irq_count = platform_get_irq(info->pdev, 1);\n> +\t\tif (info->gpmc_irq_count <= 0) {\n> +\t\t\tdev_err(dev, \"Error getting IRQ count\\n\");\n> +\t\t\treturn -ENODEV;\n> +\t\t}\n> +\t\terr = devm_request_irq(dev, info->gpmc_irq_count,\n> +\t\t\t\t       omap_nand_irq, IRQF_SHARED,\n> +\t\t\t\t       \"gpmc-nand-count\", info);\n> +\t\tif (err) {\n> +\t\t\tdev_err(dev, \"Requesting IRQ %d, error %d\\n\",\n> +\t\t\t\tinfo->gpmc_irq_count, err);\n> +\t\t\tinfo->gpmc_irq_count = 0;\n> +\t\t\treturn err;\n> +\t\t}\n> +\n> +\t\tchip->read_buf = omap_read_buf_irq_pref;\n> +\t\tchip->write_buf = omap_write_buf_irq_pref;\n> +\n> +\t\tbreak;\n> +\n> +\tdefault:\n> +\t\tdev_err(dev, \"xfer_type %d not supported!\\n\", info->xfer_type);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\tif (!omap2_nand_ecc_check(info))\n> +\t\treturn -EINVAL;\n> +\n> +\t/*\n> +\t * Bail out earlier to let NAND_ECC_SOFT code create its own\n> +\t * ooblayout instead of using ours.\n> +\t */\n> +\tif (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {\n> +\t\tchip->ecc.mode = NAND_ECC_SOFT;\n> +\t\tchip->ecc.algo = NAND_ECC_HAMMING;\n> +\t\treturn 0;\n> +\t}\n> +\n> +\t/* Populate MTD interface based on ECC scheme */\n> +\tswitch (info->ecc_opt) {\n> +\tcase OMAP_ECC_HAM1_CODE_HW:\n> +\t\tdev_info(dev, \"nand: using OMAP_ECC_HAM1_CODE_HW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.bytes\t\t= 3;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.strength\t= 1;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc;\n> +\t\tchip->ecc.correct\t= omap_correct_data;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\tif (!(chip->options & NAND_BUSWIDTH_16))\n> +\t\t\tmin_oobbytes\t= 1;\n> +\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 7;\n> +\t\tchip->ecc.strength\t= 4;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= nand_bch_correct_data;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> +\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> +\t\t/* Reserve one byte for the OMAP marker */\n> +\t\toobbytes_per_step\t= chip->ecc.bytes + 1;\n> +\t\t/* Software BCH library is used for locating errors */\n> +\t\tchip->ecc.priv\t\t= nand_bch_init(mtd);\n> +\t\tif (!chip->ecc.priv) {\n> +\t\t\tdev_err(dev, \"Unable to use BCH library\\n\");\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH4_CODE_HW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> +\t\tchip->ecc.bytes\t\t= 7 + 1;\n> +\t\tchip->ecc.strength\t= 4;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH4_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 13;\n> +\t\tchip->ecc.strength\t= 8;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= nand_bch_correct_data;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> +\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> +\t\t/* Reserve one byte for the OMAP marker */\n> +\t\toobbytes_per_step\t= chip->ecc.bytes + 1;\n> +\t\t/* Software BCH library is used for locating errors */\n> +\t\tchip->ecc.priv\t\t= nand_bch_init(mtd);\n> +\t\tif (!chip->ecc.priv) {\n> +\t\t\tdev_err(dev, \"unable to use BCH library\\n\");\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH8_CODE_HW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> +\t\tchip->ecc.bytes\t\t= 13 + 1;\n> +\t\tchip->ecc.strength\t= 8;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH8_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH16_CODE_HW:\n> +\t\tpr_info(\"Using OMAP_ECC_BCH16_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 26;\n> +\t\tchip->ecc.strength\t= 16;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH16_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\n> +\t\tbreak;\n> +\tdefault:\n> +\t\tdev_err(dev, \"Invalid or unsupported ECC scheme\\n\");\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\t/* Check if NAND device's OOB is enough to store ECC signatures */\n> +\tmin_oobbytes += (oobbytes_per_step *\n> +\t\t\t (mtd->writesize / chip->ecc.size));\n> +\tif (mtd->oobsize < min_oobbytes) {\n> +\t\tdev_err(dev,\n> +\t\t\t\"Not enough OOB bytes: required = %d, available=%d\\n\",\n> +\t\t\tmin_oobbytes, mtd->oobsize);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static const struct nand_controller_ops omap_nand_controller_ops = {\n> +\t.attach_chip = omap_nand_attach_chip,\n> +};\n> +\n> +/* Shared among all NAND instances to synchronize access to the ECC Engine */\n> +static struct nand_controller omap_gpmc_controller = {\n> +\t.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),\n> +\t.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),\n> +\t.ops = &omap_nand_controller_ops,\n> +};\n> +\n>  static int omap_nand_probe(struct platform_device *pdev)\n>  {\n>  \tstruct omap_nand_info\t\t*info;\n>  \tstruct mtd_info\t\t\t*mtd;\n>  \tstruct nand_chip\t\t*nand_chip;\n>  \tint\t\t\t\terr;\n> -\tdma_cap_mask_t\t\t\tmask;\n>  \tstruct resource\t\t\t*res;\n>  \tstruct device\t\t\t*dev = &pdev->dev;\n> -\tint\t\t\t\tmin_oobbytes = BADBLOCK_MARKER_LENGTH;\n> -\tint\t\t\t\toobbytes_per_step;\n>  \n>  \tinfo = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),\n>  \t\t\t\tGFP_KERNEL);\n> @@ -1998,266 +2253,8 @@ static int omap_nand_probe(struct platform_device *pdev)\n>  \n>  \t/* scan NAND device connected to chip controller */\n>  \tnand_chip->options |= info->devsize & NAND_BUSWIDTH_16;\n> -\terr = nand_scan_ident(mtd, 1, NULL);\n> -\tif (err) {\n> -\t\tdev_err(&info->pdev->dev,\n> -\t\t\t\"scan failed, may be bus-width mismatch\\n\");\n> -\t\tgoto return_error;\n> -\t}\n>  \n> -\tif (nand_chip->bbt_options & NAND_BBT_USE_FLASH)\n> -\t\tnand_chip->bbt_options |= NAND_BBT_NO_OOB;\n> -\telse\n> -\t\tnand_chip->options |= NAND_SKIP_BBTSCAN;\n> -\n> -\t/* re-populate low-level callbacks based on xfer modes */\n> -\tswitch (info->xfer_type) {\n> -\tcase NAND_OMAP_PREFETCH_POLLED:\n> -\t\tnand_chip->read_buf   = omap_read_buf_pref;\n> -\t\tnand_chip->write_buf  = omap_write_buf_pref;\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_POLLED:\n> -\t\t/* Use nand_base defaults for {read,write}_buf */\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_PREFETCH_DMA:\n> -\t\tdma_cap_zero(mask);\n> -\t\tdma_cap_set(DMA_SLAVE, mask);\n> -\t\tinfo->dma = dma_request_chan(pdev->dev.parent, \"rxtx\");\n> -\n> -\t\tif (IS_ERR(info->dma)) {\n> -\t\t\tdev_err(&pdev->dev, \"DMA engine request failed\\n\");\n> -\t\t\terr = PTR_ERR(info->dma);\n> -\t\t\tgoto return_error;\n> -\t\t} else {\n> -\t\t\tstruct dma_slave_config cfg;\n> -\n> -\t\t\tmemset(&cfg, 0, sizeof(cfg));\n> -\t\t\tcfg.src_addr = info->phys_base;\n> -\t\t\tcfg.dst_addr = info->phys_base;\n> -\t\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> -\t\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> -\t\t\tcfg.src_maxburst = 16;\n> -\t\t\tcfg.dst_maxburst = 16;\n> -\t\t\terr = dmaengine_slave_config(info->dma, &cfg);\n> -\t\t\tif (err) {\n> -\t\t\t\tdev_err(&pdev->dev, \"DMA engine slave config failed: %d\\n\",\n> -\t\t\t\t\terr);\n> -\t\t\t\tgoto return_error;\n> -\t\t\t}\n> -\t\t\tnand_chip->read_buf   = omap_read_buf_dma_pref;\n> -\t\t\tnand_chip->write_buf  = omap_write_buf_dma_pref;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_PREFETCH_IRQ:\n> -\t\tinfo->gpmc_irq_fifo = platform_get_irq(pdev, 0);\n> -\t\tif (info->gpmc_irq_fifo <= 0) {\n> -\t\t\tdev_err(&pdev->dev, \"error getting fifo irq\\n\");\n> -\t\t\terr = -ENODEV;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\terr = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,\n> -\t\t\t\t\tomap_nand_irq, IRQF_SHARED,\n> -\t\t\t\t\t\"gpmc-nand-fifo\", info);\n> -\t\tif (err) {\n> -\t\t\tdev_err(&pdev->dev, \"requesting irq(%d) error:%d\",\n> -\t\t\t\t\t\tinfo->gpmc_irq_fifo, err);\n> -\t\t\tinfo->gpmc_irq_fifo = 0;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\n> -\t\tinfo->gpmc_irq_count = platform_get_irq(pdev, 1);\n> -\t\tif (info->gpmc_irq_count <= 0) {\n> -\t\t\tdev_err(&pdev->dev, \"error getting count irq\\n\");\n> -\t\t\terr = -ENODEV;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\terr = devm_request_irq(&pdev->dev, info->gpmc_irq_count,\n> -\t\t\t\t\tomap_nand_irq, IRQF_SHARED,\n> -\t\t\t\t\t\"gpmc-nand-count\", info);\n> -\t\tif (err) {\n> -\t\t\tdev_err(&pdev->dev, \"requesting irq(%d) error:%d\",\n> -\t\t\t\t\t\tinfo->gpmc_irq_count, err);\n> -\t\t\tinfo->gpmc_irq_count = 0;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\n> -\t\tnand_chip->read_buf  = omap_read_buf_irq_pref;\n> -\t\tnand_chip->write_buf = omap_write_buf_irq_pref;\n> -\n> -\t\tbreak;\n> -\n> -\tdefault:\n> -\t\tdev_err(&pdev->dev,\n> -\t\t\t\"xfer_type(%d) not supported!\\n\", info->xfer_type);\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\tif (!omap2_nand_ecc_check(info)) {\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\t/*\n> -\t * Bail out earlier to let NAND_ECC_SOFT code create its own\n> -\t * ooblayout instead of using ours.\n> -\t */\n> -\tif (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {\n> -\t\tnand_chip->ecc.mode = NAND_ECC_SOFT;\n> -\t\tnand_chip->ecc.algo = NAND_ECC_HAMMING;\n> -\t\tgoto scan_tail;\n> -\t}\n> -\n> -\t/* populate MTD interface based on ECC scheme */\n> -\tswitch (info->ecc_opt) {\n> -\tcase OMAP_ECC_HAM1_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_HAM1_CODE_HW\\n\");\n> -\t\tnand_chip->ecc.mode             = NAND_ECC_HW;\n> -\t\tnand_chip->ecc.bytes            = 3;\n> -\t\tnand_chip->ecc.size             = 512;\n> -\t\tnand_chip->ecc.strength         = 1;\n> -\t\tnand_chip->ecc.calculate        = omap_calculate_ecc;\n> -\t\tnand_chip->ecc.hwctl            = omap_enable_hwecc;\n> -\t\tnand_chip->ecc.correct          = omap_correct_data;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\tif (!(nand_chip->options & NAND_BUSWIDTH_16))\n> -\t\t\tmin_oobbytes\t\t= 1;\n> -\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 7;\n> -\t\tnand_chip->ecc.strength\t\t= 4;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= nand_bch_correct_data;\n> -\t\tnand_chip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> -\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> -\t\t/* Reserve one byte for the OMAP marker */\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes + 1;\n> -\t\t/* software bch library is used for locating errors */\n> -\t\tnand_chip->ecc.priv\t\t= nand_bch_init(mtd);\n> -\t\tif (!nand_chip->ecc.priv) {\n> -\t\t\tdev_err(&info->pdev->dev, \"unable to use BCH library\\n\");\n> -\t\t\terr = -EINVAL;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH4_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> -\t\tnand_chip->ecc.bytes\t\t= 7 + 1;\n> -\t\tnand_chip->ecc.strength\t\t= 4;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH4_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 13;\n> -\t\tnand_chip->ecc.strength\t\t= 8;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= nand_bch_correct_data;\n> -\t\tnand_chip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> -\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> -\t\t/* Reserve one byte for the OMAP marker */\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes + 1;\n> -\t\t/* software bch library is used for locating errors */\n> -\t\tnand_chip->ecc.priv\t\t= nand_bch_init(mtd);\n> -\t\tif (!nand_chip->ecc.priv) {\n> -\t\t\tdev_err(&info->pdev->dev, \"unable to use BCH library\\n\");\n> -\t\t\terr = -EINVAL;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH8_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> -\t\tnand_chip->ecc.bytes\t\t= 13 + 1;\n> -\t\tnand_chip->ecc.strength\t\t= 8;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH8_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH16_CODE_HW:\n> -\t\tpr_info(\"using OMAP_ECC_BCH16_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 26;\n> -\t\tnand_chip->ecc.strength\t\t= 16;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH16_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\n> -\t\tbreak;\n> -\tdefault:\n> -\t\tdev_err(&info->pdev->dev, \"invalid or unsupported ECC scheme\\n\");\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\t/* check if NAND device's OOB is enough to store ECC signatures */\n> -\tmin_oobbytes += (oobbytes_per_step *\n> -\t\t\t (mtd->writesize / nand_chip->ecc.size));\n> -\tif (mtd->oobsize < min_oobbytes) {\n> -\t\tdev_err(&info->pdev->dev,\n> -\t\t\t\"not enough OOB bytes required = %d, available=%d\\n\",\n> -\t\t\tmin_oobbytes, mtd->oobsize);\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -scan_tail:\n> -\t/* second phase scan */\n> -\terr = nand_scan_tail(mtd);\n> +\terr = nand_scan(mtd, 1);\n>  \tif (err)\n>  \t\tgoto return_error;\n>","headers":{"Return-Path":"<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; 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bh=pYKe7lU40k67ABQI4THb6bh9ZxyJs4EleUBmOMvxiCs=;\n\tb=URxpD5Dwr+2YLo\n\tyJF1j2emPNXSfqiZDh01y8f630xr0mYpVwOH3ldIA7HZ4RTpK3/unVyOxjaamkZF5mEr4wcjJCiBD\n\t0Xge5/leMmetBm6APokgGOTKSjUVWZ+Y5vzg4PqUco0O2LwJHDGJ8Z7ykFsM2odKBuMSUlcXZ2uci\n\t03e9hmbYBjeY4gCWVJ6ilLwwPwmWxiYKt6DC0jLPvfAVcX+9WIepNRQo9Fiu9O1S//kNr63+byGkT\n\tSb0EWS7jqu2iq36TdMISrVq+LMq/EPGfXL/kWk2uuvre5avpHQzcBZrQHmE8P8u0TkFm/ABF1WUta\n\t5d83xDwZDRDW1PPl537w==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Wed, 25 Jul 2018 17:39:19 +0200","From":"Boris Brezillon <boris.brezillon@bootlin.com>","To":"Miquel Raynal <miquel.raynal@bootlin.com>","Subject":"Re: [PATCH v5 04/17] mtd: rawnand: omap2: convert driver to\n\tnand_scan()","Message-ID":"<20180725173919.0792b751@bbrezillon>","In-Reply-To":"<20180725133152.30898-5-miquel.raynal@bootlin.com>","References":"<20180725133152.30898-1-miquel.raynal@bootlin.com>\n\t<20180725133152.30898-5-miquel.raynal@bootlin.com>","X-Mailer":"Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20180725_083941_401831_E5B39F80 ","X-CRM114-Status":"GOOD (  27.62  )","X-Spam-Score":"-0.0 (/)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-0.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [62.4.15.54 listed in list.dnswl.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-mtd/>","List-Post":"<mailto:linux-mtd@lists.infradead.org>","List-Help":"<mailto:linux-mtd-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>","Cc":"Lucas Stach <dev@lynxeye.de>, Wenyou Yang <wenyou.yang@microchip.com>,\n\tRichard Weinberger <richard@nod.at>, Stefan Agner <stefan@agner.ch>, \n\tMarek Vasut <marek.vasut@gmail.com>, linux-mtd@lists.infradead.org,\n\tJosh Wu <rainyfeeling@outlook.com>,\n\tBrian Norris <computersforpeace@gmail.com>, \n\tDavid Woodhouse <dwmw2@infradead.org>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":2052655,"web_url":"http://patchwork.ozlabs.org/comment/2052655/","msgid":"<20181213190111.2f32cfaffa5ea26f77bae520@gmail.com>","list_archive_url":null,"date":"2018-12-13T18:01:11","subject":"Re: [v5,04/17] mtd: rawnand: omap2: convert driver to nand_scan()","submitter":{"id":65943,"url":"http://patchwork.ozlabs.org/api/people/65943/","name":"Alexander Sverdlin","email":"alexander.sverdlin@gmail.com"},"content":"Hello Miquel, Boris,\n\nOn Wed, 25 Jul 2018 15:31:39 +0200\nMiquel Raynal <miquel.raynal@bootlin.com> wrote:\n\n> Two helpers have been added to the core to do all kind of controller\n> side configuration/initialization between the detection phase and the\n> final NAND scan. Implement these hooks so that we can convert the driver\n> to just use nand_scan() instead of the nand_scan_ident() +\n> nand_scan_tail() pair.\n> \n> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>\n\nI've bisected this patch to brake Beagle Bone Black boot\n(from NAND, at least in DMA mode):\n\n[    0.243337] edma 49000000.edma: TI EDMA DMA engine driver\n\n... skipped...\n\n[    1.888170] omap-gpmc 50000000.gpmc: GPMC revision 6.0\n[    1.893597] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000\n[    1.901776] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda\n[    1.908589] nand: Micron MT29F2G08ABAEAWP\n[    1.912807] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64\n[    1.920802] omap2-nand 8000000.nand: DMA engine request failed\n\n... unrelated...\n\n[    1.985544] UBI error: cannot open mtd NAND.root-squashfs2, error -2\n[    1.992432] UBI error: cannot open mtd NAND.root-ubifs, error -2\n[    1.998897] UBI: block: can't open volume on ubi0_0, err=-19\n\n... unrelated...\n\n[    2.025751] VFS: Cannot open root device \"ubiblock0_0\" or unknown-block(0,0): error -6\n[    2.034168] Please append a correct \"root=\" boot option; here are the available partitions:\n[    2.042997] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)\n\nEDMA driver is here, yet the channel cannot be obtained after\ncommit e1e6255c31.\n\n> ---\n>  drivers/mtd/nand/raw/omap2.c | 533 +++++++++++++++++++++----------------------\n>  1 file changed, 265 insertions(+), 268 deletions(-)\n> \n> diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c\n> index e943b2e5a5e2..4546ac0bed4a 100644\n> --- a/drivers/mtd/nand/raw/omap2.c\n> +++ b/drivers/mtd/nand/raw/omap2.c\n> @@ -144,12 +144,6 @@ static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,\n>  \t0xac, 0x6b, 0xff, 0x99, 0x7b};\n>  static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};\n>  \n> -/* Shared among all NAND instances to synchronize access to the ECC Engine */\n> -static struct nand_controller omap_gpmc_controller = {\n> -\t.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),\n> -\t.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),\n> -};\n> -\n>  struct omap_nand_info {\n>  \tstruct nand_chip\t\tnand;\n>  \tstruct platform_device\t\t*pdev;\n> @@ -1915,17 +1909,278 @@ static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {\n>  \t.free = omap_sw_ooblayout_free,\n>  };\n>  \n> +static int omap_nand_attach_chip(struct nand_chip *chip)\n> +{\n> +\tstruct mtd_info *mtd = nand_to_mtd(chip);\n> +\tstruct omap_nand_info *info = mtd_to_omap(mtd);\n> +\tstruct device *dev = &info->pdev->dev;\n> +\tint min_oobbytes = BADBLOCK_MARKER_LENGTH;\n> +\tint oobbytes_per_step;\n> +\tdma_cap_mask_t mask;\n> +\tint err;\n> +\n> +\tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n> +\t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n> +\telse\n> +\t\tchip->options |= NAND_SKIP_BBTSCAN;\n> +\n> +\t/* Re-populate low-level callbacks based on xfer modes */\n> +\tswitch (info->xfer_type) {\n> +\tcase NAND_OMAP_PREFETCH_POLLED:\n> +\t\tchip->read_buf = omap_read_buf_pref;\n> +\t\tchip->write_buf = omap_write_buf_pref;\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_POLLED:\n> +\t\t/* Use nand_base defaults for {read,write}_buf */\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_PREFETCH_DMA:\n> +\t\tdma_cap_zero(mask);\n> +\t\tdma_cap_set(DMA_SLAVE, mask);\n> +\t\tinfo->dma = dma_request_chan(dev, \"rxtx\");\n> +\n> +\t\tif (IS_ERR(info->dma)) {\n> +\t\t\tdev_err(dev, \"DMA engine request failed\\n\");\n> +\t\t\treturn PTR_ERR(info->dma);\n> +\t\t} else {\n> +\t\t\tstruct dma_slave_config cfg;\n> +\n> +\t\t\tmemset(&cfg, 0, sizeof(cfg));\n> +\t\t\tcfg.src_addr = info->phys_base;\n> +\t\t\tcfg.dst_addr = info->phys_base;\n> +\t\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> +\t\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> +\t\t\tcfg.src_maxburst = 16;\n> +\t\t\tcfg.dst_maxburst = 16;\n> +\t\t\terr = dmaengine_slave_config(info->dma, &cfg);\n> +\t\t\tif (err) {\n> +\t\t\t\tdev_err(dev,\n> +\t\t\t\t\t\"DMA engine slave config failed: %d\\n\",\n> +\t\t\t\t\terr);\n> +\t\t\t\treturn err;\n> +\t\t\t}\n> +\t\t\tchip->read_buf = omap_read_buf_dma_pref;\n> +\t\t\tchip->write_buf = omap_write_buf_dma_pref;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase NAND_OMAP_PREFETCH_IRQ:\n> +\t\tinfo->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);\n> +\t\tif (info->gpmc_irq_fifo <= 0) {\n> +\t\t\tdev_err(dev, \"Error getting fifo IRQ\\n\");\n> +\t\t\treturn -ENODEV;\n> +\t\t}\n> +\t\terr = devm_request_irq(dev, info->gpmc_irq_fifo,\n> +\t\t\t\t       omap_nand_irq, IRQF_SHARED,\n> +\t\t\t\t       \"gpmc-nand-fifo\", info);\n> +\t\tif (err) {\n> +\t\t\tdev_err(dev, \"Requesting IRQ %d, error %d\\n\",\n> +\t\t\t\tinfo->gpmc_irq_fifo, err);\n> +\t\t\tinfo->gpmc_irq_fifo = 0;\n> +\t\t\treturn err;\n> +\t\t}\n> +\n> +\t\tinfo->gpmc_irq_count = platform_get_irq(info->pdev, 1);\n> +\t\tif (info->gpmc_irq_count <= 0) {\n> +\t\t\tdev_err(dev, \"Error getting IRQ count\\n\");\n> +\t\t\treturn -ENODEV;\n> +\t\t}\n> +\t\terr = devm_request_irq(dev, info->gpmc_irq_count,\n> +\t\t\t\t       omap_nand_irq, IRQF_SHARED,\n> +\t\t\t\t       \"gpmc-nand-count\", info);\n> +\t\tif (err) {\n> +\t\t\tdev_err(dev, \"Requesting IRQ %d, error %d\\n\",\n> +\t\t\t\tinfo->gpmc_irq_count, err);\n> +\t\t\tinfo->gpmc_irq_count = 0;\n> +\t\t\treturn err;\n> +\t\t}\n> +\n> +\t\tchip->read_buf = omap_read_buf_irq_pref;\n> +\t\tchip->write_buf = omap_write_buf_irq_pref;\n> +\n> +\t\tbreak;\n> +\n> +\tdefault:\n> +\t\tdev_err(dev, \"xfer_type %d not supported!\\n\", info->xfer_type);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\tif (!omap2_nand_ecc_check(info))\n> +\t\treturn -EINVAL;\n> +\n> +\t/*\n> +\t * Bail out earlier to let NAND_ECC_SOFT code create its own\n> +\t * ooblayout instead of using ours.\n> +\t */\n> +\tif (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {\n> +\t\tchip->ecc.mode = NAND_ECC_SOFT;\n> +\t\tchip->ecc.algo = NAND_ECC_HAMMING;\n> +\t\treturn 0;\n> +\t}\n> +\n> +\t/* Populate MTD interface based on ECC scheme */\n> +\tswitch (info->ecc_opt) {\n> +\tcase OMAP_ECC_HAM1_CODE_HW:\n> +\t\tdev_info(dev, \"nand: using OMAP_ECC_HAM1_CODE_HW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.bytes\t\t= 3;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.strength\t= 1;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc;\n> +\t\tchip->ecc.correct\t= omap_correct_data;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\tif (!(chip->options & NAND_BUSWIDTH_16))\n> +\t\t\tmin_oobbytes\t= 1;\n> +\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 7;\n> +\t\tchip->ecc.strength\t= 4;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= nand_bch_correct_data;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> +\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> +\t\t/* Reserve one byte for the OMAP marker */\n> +\t\toobbytes_per_step\t= chip->ecc.bytes + 1;\n> +\t\t/* Software BCH library is used for locating errors */\n> +\t\tchip->ecc.priv\t\t= nand_bch_init(mtd);\n> +\t\tif (!chip->ecc.priv) {\n> +\t\t\tdev_err(dev, \"Unable to use BCH library\\n\");\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH4_CODE_HW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> +\t\tchip->ecc.bytes\t\t= 7 + 1;\n> +\t\tchip->ecc.strength\t= 4;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH4_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 13;\n> +\t\tchip->ecc.strength\t= 8;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= nand_bch_correct_data;\n> +\t\tchip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> +\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> +\t\t/* Reserve one byte for the OMAP marker */\n> +\t\toobbytes_per_step\t= chip->ecc.bytes + 1;\n> +\t\t/* Software BCH library is used for locating errors */\n> +\t\tchip->ecc.priv\t\t= nand_bch_init(mtd);\n> +\t\tif (!chip->ecc.priv) {\n> +\t\t\tdev_err(dev, \"unable to use BCH library\\n\");\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH8_CODE_HW:\n> +\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> +\t\tchip->ecc.bytes\t\t= 13 + 1;\n> +\t\tchip->ecc.strength\t= 8;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH8_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\n> +\t\tbreak;\n> +\n> +\tcase OMAP_ECC_BCH16_CODE_HW:\n> +\t\tpr_info(\"Using OMAP_ECC_BCH16_CODE_HW ECC scheme\\n\");\n> +\t\tchip->ecc.mode\t\t= NAND_ECC_HW;\n> +\t\tchip->ecc.size\t\t= 512;\n> +\t\tchip->ecc.bytes\t\t= 26;\n> +\t\tchip->ecc.strength\t= 16;\n> +\t\tchip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> +\t\tchip->ecc.correct\t= omap_elm_correct_data;\n> +\t\tchip->ecc.read_page\t= omap_read_page_bch;\n> +\t\tchip->ecc.write_page\t= omap_write_page_bch;\n> +\t\tchip->ecc.write_subpage\t= omap_write_subpage_bch;\n> +\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> +\t\toobbytes_per_step\t= chip->ecc.bytes;\n> +\n> +\t\terr = elm_config(info->elm_dev, BCH16_ECC,\n> +\t\t\t\t mtd->writesize / chip->ecc.size,\n> +\t\t\t\t chip->ecc.size, chip->ecc.bytes);\n> +\t\tif (err < 0)\n> +\t\t\treturn err;\n> +\n> +\t\tbreak;\n> +\tdefault:\n> +\t\tdev_err(dev, \"Invalid or unsupported ECC scheme\\n\");\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\t/* Check if NAND device's OOB is enough to store ECC signatures */\n> +\tmin_oobbytes += (oobbytes_per_step *\n> +\t\t\t (mtd->writesize / chip->ecc.size));\n> +\tif (mtd->oobsize < min_oobbytes) {\n> +\t\tdev_err(dev,\n> +\t\t\t\"Not enough OOB bytes: required = %d, available=%d\\n\",\n> +\t\t\tmin_oobbytes, mtd->oobsize);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static const struct nand_controller_ops omap_nand_controller_ops = {\n> +\t.attach_chip = omap_nand_attach_chip,\n> +};\n> +\n> +/* Shared among all NAND instances to synchronize access to the ECC Engine */\n> +static struct nand_controller omap_gpmc_controller = {\n> +\t.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),\n> +\t.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),\n> +\t.ops = &omap_nand_controller_ops,\n> +};\n> +\n>  static int omap_nand_probe(struct platform_device *pdev)\n>  {\n>  \tstruct omap_nand_info\t\t*info;\n>  \tstruct mtd_info\t\t\t*mtd;\n>  \tstruct nand_chip\t\t*nand_chip;\n>  \tint\t\t\t\terr;\n> -\tdma_cap_mask_t\t\t\tmask;\n>  \tstruct resource\t\t\t*res;\n>  \tstruct device\t\t\t*dev = &pdev->dev;\n> -\tint\t\t\t\tmin_oobbytes = BADBLOCK_MARKER_LENGTH;\n> -\tint\t\t\t\toobbytes_per_step;\n>  \n>  \tinfo = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),\n>  \t\t\t\tGFP_KERNEL);\n> @@ -1998,266 +2253,8 @@ static int omap_nand_probe(struct platform_device *pdev)\n>  \n>  \t/* scan NAND device connected to chip controller */\n>  \tnand_chip->options |= info->devsize & NAND_BUSWIDTH_16;\n> -\terr = nand_scan_ident(mtd, 1, NULL);\n> -\tif (err) {\n> -\t\tdev_err(&info->pdev->dev,\n> -\t\t\t\"scan failed, may be bus-width mismatch\\n\");\n> -\t\tgoto return_error;\n> -\t}\n>  \n> -\tif (nand_chip->bbt_options & NAND_BBT_USE_FLASH)\n> -\t\tnand_chip->bbt_options |= NAND_BBT_NO_OOB;\n> -\telse\n> -\t\tnand_chip->options |= NAND_SKIP_BBTSCAN;\n> -\n> -\t/* re-populate low-level callbacks based on xfer modes */\n> -\tswitch (info->xfer_type) {\n> -\tcase NAND_OMAP_PREFETCH_POLLED:\n> -\t\tnand_chip->read_buf   = omap_read_buf_pref;\n> -\t\tnand_chip->write_buf  = omap_write_buf_pref;\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_POLLED:\n> -\t\t/* Use nand_base defaults for {read,write}_buf */\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_PREFETCH_DMA:\n> -\t\tdma_cap_zero(mask);\n> -\t\tdma_cap_set(DMA_SLAVE, mask);\n> -\t\tinfo->dma = dma_request_chan(pdev->dev.parent, \"rxtx\");\n> -\n> -\t\tif (IS_ERR(info->dma)) {\n> -\t\t\tdev_err(&pdev->dev, \"DMA engine request failed\\n\");\n> -\t\t\terr = PTR_ERR(info->dma);\n> -\t\t\tgoto return_error;\n> -\t\t} else {\n> -\t\t\tstruct dma_slave_config cfg;\n> -\n> -\t\t\tmemset(&cfg, 0, sizeof(cfg));\n> -\t\t\tcfg.src_addr = info->phys_base;\n> -\t\t\tcfg.dst_addr = info->phys_base;\n> -\t\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> -\t\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n> -\t\t\tcfg.src_maxburst = 16;\n> -\t\t\tcfg.dst_maxburst = 16;\n> -\t\t\terr = dmaengine_slave_config(info->dma, &cfg);\n> -\t\t\tif (err) {\n> -\t\t\t\tdev_err(&pdev->dev, \"DMA engine slave config failed: %d\\n\",\n> -\t\t\t\t\terr);\n> -\t\t\t\tgoto return_error;\n> -\t\t\t}\n> -\t\t\tnand_chip->read_buf   = omap_read_buf_dma_pref;\n> -\t\t\tnand_chip->write_buf  = omap_write_buf_dma_pref;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase NAND_OMAP_PREFETCH_IRQ:\n> -\t\tinfo->gpmc_irq_fifo = platform_get_irq(pdev, 0);\n> -\t\tif (info->gpmc_irq_fifo <= 0) {\n> -\t\t\tdev_err(&pdev->dev, \"error getting fifo irq\\n\");\n> -\t\t\terr = -ENODEV;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\terr = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,\n> -\t\t\t\t\tomap_nand_irq, IRQF_SHARED,\n> -\t\t\t\t\t\"gpmc-nand-fifo\", info);\n> -\t\tif (err) {\n> -\t\t\tdev_err(&pdev->dev, \"requesting irq(%d) error:%d\",\n> -\t\t\t\t\t\tinfo->gpmc_irq_fifo, err);\n> -\t\t\tinfo->gpmc_irq_fifo = 0;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\n> -\t\tinfo->gpmc_irq_count = platform_get_irq(pdev, 1);\n> -\t\tif (info->gpmc_irq_count <= 0) {\n> -\t\t\tdev_err(&pdev->dev, \"error getting count irq\\n\");\n> -\t\t\terr = -ENODEV;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\terr = devm_request_irq(&pdev->dev, info->gpmc_irq_count,\n> -\t\t\t\t\tomap_nand_irq, IRQF_SHARED,\n> -\t\t\t\t\t\"gpmc-nand-count\", info);\n> -\t\tif (err) {\n> -\t\t\tdev_err(&pdev->dev, \"requesting irq(%d) error:%d\",\n> -\t\t\t\t\t\tinfo->gpmc_irq_count, err);\n> -\t\t\tinfo->gpmc_irq_count = 0;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\n> -\t\tnand_chip->read_buf  = omap_read_buf_irq_pref;\n> -\t\tnand_chip->write_buf = omap_write_buf_irq_pref;\n> -\n> -\t\tbreak;\n> -\n> -\tdefault:\n> -\t\tdev_err(&pdev->dev,\n> -\t\t\t\"xfer_type(%d) not supported!\\n\", info->xfer_type);\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\tif (!omap2_nand_ecc_check(info)) {\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\t/*\n> -\t * Bail out earlier to let NAND_ECC_SOFT code create its own\n> -\t * ooblayout instead of using ours.\n> -\t */\n> -\tif (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {\n> -\t\tnand_chip->ecc.mode = NAND_ECC_SOFT;\n> -\t\tnand_chip->ecc.algo = NAND_ECC_HAMMING;\n> -\t\tgoto scan_tail;\n> -\t}\n> -\n> -\t/* populate MTD interface based on ECC scheme */\n> -\tswitch (info->ecc_opt) {\n> -\tcase OMAP_ECC_HAM1_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_HAM1_CODE_HW\\n\");\n> -\t\tnand_chip->ecc.mode             = NAND_ECC_HW;\n> -\t\tnand_chip->ecc.bytes            = 3;\n> -\t\tnand_chip->ecc.size             = 512;\n> -\t\tnand_chip->ecc.strength         = 1;\n> -\t\tnand_chip->ecc.calculate        = omap_calculate_ecc;\n> -\t\tnand_chip->ecc.hwctl            = omap_enable_hwecc;\n> -\t\tnand_chip->ecc.correct          = omap_correct_data;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\tif (!(nand_chip->options & NAND_BUSWIDTH_16))\n> -\t\t\tmin_oobbytes\t\t= 1;\n> -\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 7;\n> -\t\tnand_chip->ecc.strength\t\t= 4;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= nand_bch_correct_data;\n> -\t\tnand_chip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> -\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> -\t\t/* Reserve one byte for the OMAP marker */\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes + 1;\n> -\t\t/* software bch library is used for locating errors */\n> -\t\tnand_chip->ecc.priv\t\t= nand_bch_init(mtd);\n> -\t\tif (!nand_chip->ecc.priv) {\n> -\t\t\tdev_err(&info->pdev->dev, \"unable to use BCH library\\n\");\n> -\t\t\terr = -EINVAL;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH4_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> -\t\tnand_chip->ecc.bytes\t\t= 7 + 1;\n> -\t\tnand_chip->ecc.strength\t\t= 4;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH4_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 13;\n> -\t\tnand_chip->ecc.strength\t\t= 8;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= nand_bch_correct_data;\n> -\t\tnand_chip->ecc.calculate\t= omap_calculate_ecc_bch_sw;\n> -\t\tmtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);\n> -\t\t/* Reserve one byte for the OMAP marker */\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes + 1;\n> -\t\t/* software bch library is used for locating errors */\n> -\t\tnand_chip->ecc.priv\t\t= nand_bch_init(mtd);\n> -\t\tif (!nand_chip->ecc.priv) {\n> -\t\t\tdev_err(&info->pdev->dev, \"unable to use BCH library\\n\");\n> -\t\t\terr = -EINVAL;\n> -\t\t\tgoto return_error;\n> -\t\t}\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH8_CODE_HW:\n> -\t\tpr_info(\"nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\t/* 14th bit is kept reserved for ROM-code compatibility */\n> -\t\tnand_chip->ecc.bytes\t\t= 13 + 1;\n> -\t\tnand_chip->ecc.strength\t\t= 8;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH8_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\n> -\t\tbreak;\n> -\n> -\tcase OMAP_ECC_BCH16_CODE_HW:\n> -\t\tpr_info(\"using OMAP_ECC_BCH16_CODE_HW ECC scheme\\n\");\n> -\t\tnand_chip->ecc.mode\t\t= NAND_ECC_HW;\n> -\t\tnand_chip->ecc.size\t\t= 512;\n> -\t\tnand_chip->ecc.bytes\t\t= 26;\n> -\t\tnand_chip->ecc.strength\t\t= 16;\n> -\t\tnand_chip->ecc.hwctl\t\t= omap_enable_hwecc_bch;\n> -\t\tnand_chip->ecc.correct\t\t= omap_elm_correct_data;\n> -\t\tnand_chip->ecc.read_page\t= omap_read_page_bch;\n> -\t\tnand_chip->ecc.write_page\t= omap_write_page_bch;\n> -\t\tnand_chip->ecc.write_subpage\t= omap_write_subpage_bch;\n> -\t\tmtd_set_ooblayout(mtd, &omap_ooblayout_ops);\n> -\t\toobbytes_per_step\t\t= nand_chip->ecc.bytes;\n> -\n> -\t\terr = elm_config(info->elm_dev, BCH16_ECC,\n> -\t\t\t\t mtd->writesize / nand_chip->ecc.size,\n> -\t\t\t\t nand_chip->ecc.size, nand_chip->ecc.bytes);\n> -\t\tif (err < 0)\n> -\t\t\tgoto return_error;\n> -\n> -\t\tbreak;\n> -\tdefault:\n> -\t\tdev_err(&info->pdev->dev, \"invalid or unsupported ECC scheme\\n\");\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -\t/* check if NAND device's OOB is enough to store ECC signatures */\n> -\tmin_oobbytes += (oobbytes_per_step *\n> -\t\t\t (mtd->writesize / nand_chip->ecc.size));\n> -\tif (mtd->oobsize < min_oobbytes) {\n> -\t\tdev_err(&info->pdev->dev,\n> -\t\t\t\"not enough OOB bytes required = %d, available=%d\\n\",\n> -\t\t\tmin_oobbytes, mtd->oobsize);\n> -\t\terr = -EINVAL;\n> -\t\tgoto return_error;\n> -\t}\n> -\n> -scan_tail:\n> -\t/* second phase scan */\n> -\terr = nand_scan_tail(mtd);\n> +\terr = nand_scan(mtd, 1);\n>  \tif (err)\n>  \t\tgoto return_error;\n>","headers":{"Return-Path":"<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=gmail.com","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"n/C/JhcK\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"edXN8r2i\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org 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<alexander.sverdlin@gmail.com>","To":"Miquel Raynal <miquel.raynal@bootlin.com>, Boris Brezillon\n\t<boris.brezillon@bootlin.com>","Subject":"Re: [v5,04/17] mtd: rawnand: omap2: convert driver to nand_scan()","Message-Id":"<20181213190111.2f32cfaffa5ea26f77bae520@gmail.com>","In-Reply-To":"<20180725133152.30898-5-miquel.raynal@bootlin.com>","References":"<20180725133152.30898-5-miquel.raynal@bootlin.com>","X-Mailer":"Sylpheed 3.7.0 (GTK+ 2.24.32; x86_64-unknown-linux-gnu)","Mime-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20181213_100129_300594_565B9B17 ","X-CRM114-Status":"GOOD (  28.94  )","X-Spam-Score":"-0.2 (/)","X-Spam-Report":"SpamAssassin version 3.4.2 on bombadil.infradead.org summary:\n\tContent analysis details:   (-0.2 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at 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<linux-mtd.lists.infradead.org>","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-mtd/>","List-Post":"<mailto:linux-mtd@lists.infradead.org>","List-Help":"<mailto:linux-mtd-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>","Cc":"Lucas Stach <dev@lynxeye.de>, Wenyou Yang <wenyou.yang@microchip.com>,\n\tRichard Weinberger <richard@nod.at>, Stefan Agner <stefan@agner.ch>, \n\tMarek Vasut <marek.vasut@gmail.com>, linux-mtd@lists.infradead.org,\n\tJosh Wu <rainyfeeling@outlook.com>,\n\tBrian Norris <computersforpeace@gmail.com>, \n\tDavid Woodhouse <dwmw2@infradead.org>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":2052670,"web_url":"http://patchwork.ozlabs.org/comment/2052670/","msgid":"<20181213193026.3efa0944@bbrezillon>","list_archive_url":null,"date":"2018-12-13T18:30:26","subject":"Re: [v5,04/17] mtd: rawnand: omap2: convert driver to nand_scan()","submitter":{"id":73370,"url":"http://patchwork.ozlabs.org/api/people/73370/","name":"Boris Brezillon","email":"boris.brezillon@bootlin.com"},"content":"On Thu, 13 Dec 2018 19:01:11 +0100\nAlexander Sverdlin <alexander.sverdlin@gmail.com> wrote:\n\n> Hello Miquel, Boris,\n> \n> On Wed, 25 Jul 2018 15:31:39 +0200\n> Miquel Raynal <miquel.raynal@bootlin.com> wrote:\n> \n> > Two helpers have been added to the core to do all kind of controller\n> > side configuration/initialization between the detection phase and the\n> > final NAND scan. Implement these hooks so that we can convert the driver\n> > to just use nand_scan() instead of the nand_scan_ident() +\n> > nand_scan_tail() pair.\n> > \n> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n> > Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>  \n> \n> I've bisected this patch to brake Beagle Bone Black boot\n> (from NAND, at least in DMA mode):\n> \n> [    0.243337] edma 49000000.edma: TI EDMA DMA engine driver\n> \n> ... skipped...\n> \n> [    1.888170] omap-gpmc 50000000.gpmc: GPMC revision 6.0\n> [    1.893597] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000\n> [    1.901776] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda\n> [    1.908589] nand: Micron MT29F2G08ABAEAWP\n> [    1.912807] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64\n> [    1.920802] omap2-nand 8000000.nand: DMA engine request failed\n> \n> ... unrelated...\n> \n> [    1.985544] UBI error: cannot open mtd NAND.root-squashfs2, error -2\n> [    1.992432] UBI error: cannot open mtd NAND.root-ubifs, error -2\n> [    1.998897] UBI: block: can't open volume on ubi0_0, err=-19\n> \n> ... unrelated...\n> \n> [    2.025751] VFS: Cannot open root device \"ubiblock0_0\" or unknown-block(0,0): error -6\n> [    2.034168] Please append a correct \"root=\" boot option; here are the available partitions:\n> [    2.042997] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)\n> \n> EDMA driver is here, yet the channel cannot be obtained after\n> commit e1e6255c31.\n\nCan you provide the full logs before and after this commit?","headers":{"Return-Path":"<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=bootlin.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Eu8ISGkH\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2607:7c80:54:e::133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43G2Ll31lWz9s9G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 14 Dec 2018 05:31:11 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux))\n\tid 1gXVl9-0003uW-4V; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20181213_103049_591487_07943C69 ","X-CRM114-Status":"GOOD (  16.37  )","X-Spam-Score":"-0.0 (/)","X-Spam-Report":"SpamAssassin version 3.4.2 on bombadil.infradead.org summary:\n\tContent analysis details:   (-0.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-mtd/>","List-Post":"<mailto:linux-mtd@lists.infradead.org>","List-Help":"<mailto:linux-mtd-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>","Cc":"Lucas Stach <dev@lynxeye.de>, Wenyou Yang <wenyou.yang@microchip.com>,\n\tRichard Weinberger <richard@nod.at>, Stefan Agner <stefan@agner.ch>, \n\tMarek Vasut <marek.vasut@gmail.com>, linux-mtd@lists.infradead.org,\n\tMiquel Raynal <miquel.raynal@bootlin.com>,\n\tJosh Wu <rainyfeeling@outlook.com>, \n\tBrian Norris <computersforpeace@gmail.com>,\n\tDavid Woodhouse <dwmw2@infradead.org>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":2052671,"web_url":"http://patchwork.ozlabs.org/comment/2052671/","msgid":"<20181213193725.4c1771c5@bbrezillon>","list_archive_url":null,"date":"2018-12-13T18:37:25","subject":"Re: [v5,04/17] mtd: rawnand: omap2: convert driver to nand_scan()","submitter":{"id":73370,"url":"http://patchwork.ozlabs.org/api/people/73370/","name":"Boris Brezillon","email":"boris.brezillon@bootlin.com"},"content":"On Thu, 13 Dec 2018 19:01:11 +0100\nAlexander Sverdlin <alexander.sverdlin@gmail.com> wrote:\n\n> > +\t/* Re-populate low-level callbacks based on xfer modes */\n> > +\tswitch (info->xfer_type) {\n> > +\tcase NAND_OMAP_PREFETCH_POLLED:\n> > +\t\tchip->read_buf = omap_read_buf_pref;\n> > +\t\tchip->write_buf = omap_write_buf_pref;\n> > +\t\tbreak;\n> > +\n> > +\tcase NAND_OMAP_POLLED:\n> > +\t\t/* Use nand_base defaults for {read,write}_buf */\n> > +\t\tbreak;\n> > +\n> > +\tcase NAND_OMAP_PREFETCH_DMA:\n> > +\t\tdma_cap_zero(mask);\n> > +\t\tdma_cap_set(DMA_SLAVE, mask);\n> > +\t\tinfo->dma = dma_request_chan(dev, \"rxtx\");\n> > +\n> > +\t\tif (IS_ERR(info->dma)) {\n> > +\t\t\tdev_err(dev, \"DMA engine request failed\\n\");\n\nCan you print the error code here?","headers":{"Return-Path":"<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20181213_103746_831141_F991D58E ","X-CRM114-Status":"GOOD (  10.02  )","X-Spam-Score":"-0.0 (/)","X-Spam-Report":"SpamAssassin version 3.4.2 on bombadil.infradead.org summary:\n\tContent analysis details:   (-0.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-mtd/>","List-Post":"<mailto:linux-mtd@lists.infradead.org>","List-Help":"<mailto:linux-mtd-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>","Cc":"Lucas Stach <dev@lynxeye.de>, Wenyou Yang <wenyou.yang@microchip.com>,\n\tRichard Weinberger <richard@nod.at>, Stefan Agner <stefan@agner.ch>, \n\tMarek Vasut <marek.vasut@gmail.com>, linux-mtd@lists.infradead.org,\n\tMiquel Raynal <miquel.raynal@bootlin.com>,\n\tJosh Wu <rainyfeeling@outlook.com>, \n\tBrian Norris <computersforpeace@gmail.com>,\n\tDavid Woodhouse <dwmw2@infradead.org>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":2052693,"web_url":"http://patchwork.ozlabs.org/comment/2052693/","msgid":"<20181213200641.7b9f7531@bbrezillon>","list_archive_url":null,"date":"2018-12-13T19:06:41","subject":"Re: [v5,04/17] mtd: rawnand: omap2: convert driver to nand_scan()","submitter":{"id":73370,"url":"http://patchwork.ozlabs.org/api/people/73370/","name":"Boris Brezillon","email":"boris.brezillon@bootlin.com"},"content":"On Thu, 13 Dec 2018 19:01:11 +0100\nAlexander Sverdlin <alexander.sverdlin@gmail.com> wrote:\n\n> > +static int omap_nand_attach_chip(struct nand_chip *chip)\n> > +{\n> > +\tstruct mtd_info *mtd = nand_to_mtd(chip);\n> > +\tstruct omap_nand_info *info = mtd_to_omap(mtd);\n> > +\tstruct device *dev = &info->pdev->dev;\n> > +\tint min_oobbytes = BADBLOCK_MARKER_LENGTH;\n> > +\tint oobbytes_per_step;\n> > +\tdma_cap_mask_t mask;\n> > +\tint err;\n> > +\n> > +\tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n> > +\t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n> > +\telse\n> > +\t\tchip->options |= NAND_SKIP_BBTSCAN;\n> > +\n> > +\t/* Re-populate low-level callbacks based on xfer modes */\n> > +\tswitch (info->xfer_type) {\n> > +\tcase NAND_OMAP_PREFETCH_POLLED:\n> > +\t\tchip->read_buf = omap_read_buf_pref;\n> > +\t\tchip->write_buf = omap_write_buf_pref;\n> > +\t\tbreak;\n> > +\n> > +\tcase NAND_OMAP_POLLED:\n> > +\t\t/* Use nand_base defaults for {read,write}_buf */\n> > +\t\tbreak;\n> > +\n> > +\tcase NAND_OMAP_PREFETCH_DMA:\n> > +\t\tdma_cap_zero(mask);\n> > +\t\tdma_cap_set(DMA_SLAVE, mask);\n> > +\t\tinfo->dma = dma_request_chan(dev, \"rxtx\");\n> > +\n\nCan you try with\n\n\t\tinfo->dma = dma_request_chan(dev->parent, \"rxtx\");\n\n?","headers":{"Return-Path":"<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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