[{"id":1798409,"web_url":"http://patchwork.ozlabs.org/comment/1798409/","msgid":"","list_archive_url":null,"date":"2017-11-03T05:38:57","subject":"Re: [PATCH][AArch64] Set default sched pressure algorithm","submitter":{"id":61210,"url":"http://patchwork.ozlabs.org/api/people/61210/","name":"Andrew Pinski","email":"apinski@cavium.com"},"content":"On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra wrote:\n> The Arm backend sets the default sched-pressure algorithm to\n> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this\n> speeds up floating point performance on SPEC - eg. CactusBSSN improves\n> by ~16%. The gains are mostly due to less spilling, so enable this on AArch64\n> by default.\n>\n> OK for commit?\n\nI am ok with this from my point of view. The rs6000, arm and s390\nback-ends all enable the same way. I suspect all RISC targets should\nenable this way too.\n\nThanks,\nAndrew\n\n>\n> 2017-11-02 Wilco Dijkstra \n>\n> * config/aarch64/aarch64.c (aarch64_override_options_internal):\n> Set PARAM_SCHED_PRESSURE_ALGORITHM to SCHED_PRESSURE_MODEL.\n>\n> --\n> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\n> index 34456e96497ac7b6d2f9931187ff05619e1934a4..750b0bc29c0963742d5d7bb4ae4619d93bec3e4a 100644\n> --- a/gcc/config/aarch64/aarch64.c\n> +++ b/gcc/config/aarch64/aarch64.c\n> @@ -9276,6 +9276,11 @@ aarch64_override_options_internal (struct gcc_options *opts)\n> opts->x_param_values,\n> global_options_set.x_param_values);\n>\n> + /* Use the alternative scheduling-pressure algorithm by default. */\n> + maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,\n> + opts->x_param_values,\n> + global_options_set.x_param_values);\n> +\n> /* Enable sw prefetching at specified optimization level for\n> CPUS that have prefetch. Lower optimization level threshold by 1\n> when profiling is enabled. */\n

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SFP:1101; SCL:1; SRVR:CY4PR07MB3415;\n\tH:mail-ot0-f177.google.com; FPR:; SPF:None; PTR:InfoNoRecords;\n\tMX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"cavium.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"03 Nov 2017 05:39:00.6789\n\t(UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"230f9f17-f849-4dfa-8a2f-08d5227d2f8c","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY4PR07MB3415"}},{"id":1798512,"web_url":"http://patchwork.ozlabs.org/comment/1798512/","msgid":"","list_archive_url":null,"date":"2017-11-03T10:11:13","subject":"Re: [PATCH][AArch64] Set default sched pressure algorithm","submitter":{"id":1765,"url":"http://patchwork.ozlabs.org/api/people/1765/","name":"Richard Biener","email":"richard.guenther@gmail.com"},"content":"On Fri, Nov 3, 2017 at 6:38 AM, Andrew Pinski wrote:\n> On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra wrote:\n>> The Arm backend sets the default sched-pressure algorithm to\n>> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this\n>> speeds up floating point performance on SPEC - eg. CactusBSSN improves\n>> by ~16%. The gains are mostly due to less spilling, so enable this on AArch64\n>> by default.\n>>\n>> OK for commit?\n>\n> I am ok with this from my point of view. The rs6000, arm and s390\n> back-ends all enable the same way. I suspect all RISC targets should\n> enable this way too.\n\nI think all OOO execution capable CPUs should. Ideally this wouldn't be\na choice between two models but the scheduler would take into account\nregister pressure anyways. Or we should always schedule with sched-pressure\nduring first scheduling.\n\nRichard.\n\n> Thanks,\n> Andrew\n>\n>>\n>> 2017-11-02 Wilco Dijkstra \n>>\n>> * config/aarch64/aarch64.c (aarch64_override_options_internal):\n>> Set PARAM_SCHED_PRESSURE_ALGORITHM to SCHED_PRESSURE_MODEL.\n>>\n>> --\n>> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\n>> index 34456e96497ac7b6d2f9931187ff05619e1934a4..750b0bc29c0963742d5d7bb4ae4619d93bec3e4a 100644\n>> --- a/gcc/config/aarch64/aarch64.c\n>> +++ b/gcc/config/aarch64/aarch64.c\n>> @@ -9276,6 +9276,11 @@ aarch64_override_options_internal (struct gcc_options *opts)\n>> opts->x_param_values,\n>> global_options_set.x_param_values);\n>>\n>> + /* Use the alternative scheduling-pressure algorithm by default. */\n>> + maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,\n>> + opts->x_param_values,\n>> + global_options_set.x_param_values);\n>> +\n>> /* Enable sw prefetching at specified optimization level for\n>> CPUS that have prefetch. Lower optimization level threshold by 1\n>> when profiling is enabled. */\n>

\n> \n> \n> \n> \n> \n>
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CactusBSSN improves\n> >> by ~16%.  The gains are mostly due to less spilling, so enable this on AArch64\n> >> by default.\n> >>\n>>> OK for commit?\n> >\n> > I am ok with this from my point of view.  The rs6000, arm and s390\n> > back-ends all enable the same way.  I suspect all RISC targets should\n> > enable this way too.\n>\n> I think all OOO execution capable CPUs should.  Ideally this wouldn't be\n> a choice between two models but the scheduler would take into account\n> register pressure anyways.  Or we should always schedule with sched-pressure\n> during first scheduling.\n\nOf the 6 targets which use -fsched-pressure, 5 prefer SCHED_PRESSURE_MODEL,\nso we could just make that the default (nds32 is the only exception, but it\nhas 32 registers so that should not be an issue).\n\nThis also fits nicely with my patches to improve GCC settings to be more optimal.\n\nWilco","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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b=CcRLCNwnfhYHsnME4kfgawZu7dRq\n\t32P7pl35BxpMBV12Y93+JTmmw7vuxB8AiO/g+4mOaJYvjydIgT5TbWo3YVA2uBA3\n\tYxi3WMY57+SbL0auUmsWNkmDRNO75q5Nb6JDCPvz7dN/p43X70qNqQshektOehoF\n\tUh7gqlzkfp7Q13A=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.7 required=5.0 tests=AWL, BAYES_00,\n\tRCVD_IN_DNSWL_NONE, SPF_HELO_PASS,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"EUR02-AM5-obe.outbound.protection.outlook.com","From":"Wilco Dijkstra ","To":"Richard Biener ,\n\tAndrew Pinski\t","CC":"\"Ellcey, Steve\" ,\n\tGCC Patches\t, nd ,\n\t\"jim.wilson@linaro.org\"\t","Subject":"Re: [PATCH][AArch64] Set default sched pressure algorithm","Date":"Fri, 3 Nov 2017 12:48:53 +0000","Message-ID":"","References":"\n\t,\n\t","In-Reply-To":"","authentication-results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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Benchmarking on AArch64 shows this \n> speeds up floating point performance on SPEC - eg. CactusBSSN improves\n> by ~16%. The gains are mostly due to less spilling, so enable this on AArch64\n> by default.\n> \n> OK for commit?\n\nOK.\n\nReviewed-By: James Greenhalgh \n\nThanks,\nJames\n\n> \n> 2017-11-02 Wilco Dijkstra \n> \n> \t* config/aarch64/aarch64.c (aarch64_override_options_internal):\n> \tSet PARAM_SCHED_PRESSURE_ALGORITHM to SCHED_PRESSURE_MODEL.\n> \n> --\n> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\n> index 34456e96497ac7b6d2f9931187ff05619e1934a4..750b0bc29c0963742d5d7bb4ae4619d93bec3e4a 100644\n> --- a/gcc/config/aarch64/aarch64.c\n> +++ b/gcc/config/aarch64/aarch64.c\n> @@ -9276,6 +9276,11 @@ aarch64_override_options_internal (struct gcc_options *opts)\n> \t\t\t opts->x_param_values,\n> \t\t\t global_options_set.x_param_values);\n> \n> + /* Use the alternative scheduling-pressure algorithm by default. */\n> + maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,\n> +\t\t\t opts->x_param_values,\n> +\t\t\t global_options_set.x_param_values);\n> +\n> /* Enable sw prefetching at specified optimization level for\n> CPUS that have prefetch. Lower optimization level threshold by 1\n> when profiling is enabled. */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-465860-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"toAljhLZ\"; dkim-atps=neutral","sourceware.org; auth=none","spf=pass (sender IP is 217.140.96.140)\n\tsmtp.mailfrom=arm.com; linaro.org;\n\tdkim=none (message not signed) header.d=none; linaro.org;\n\tdmarc=bestguesspass action=none header.from=arm.com; "],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yT52L2Xj8z9sNr\n\tfor ;\n\tSat, 4 Nov 2017 02:08:57 +1100 (AEDT)","(qmail 71004 invoked by alias); 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","X-Forefront-PRVS":"0480A51D4A","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"arm.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"03 Nov 2017 15:08:39.7137\n\t(UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"f6e4379b-ea7c-4fde-840c-08d522ccc3fd","X-MS-Exchange-CrossTenant-Id":"f34e5979-57d9-4aaa-ad4d-b122a662184d","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;\n\tIp=[217.140.96.140]; Helo=[nebula.arm.com]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DB5PR0801MB1525","X-IsSubscribed":"yes"}},{"id":1799552,"web_url":"http://patchwork.ozlabs.org/comment/1799552/","msgid":"<2EE93A11-4394-4CA9-AD9A-54E992F21095@linaro.org>","list_archive_url":null,"date":"2017-11-06T10:31:31","subject":"Re: [PATCH][AArch64] Set default sched pressure algorithm","submitter":{"id":62105,"url":"http://patchwork.ozlabs.org/api/people/62105/","name":"Maxim Kuvyrkov","email":"maxim.kuvyrkov@linaro.org"},"content":"> \n> On Nov 2, 2017, at 9:41 PM, Wilco Dijkstra wrote:\n> \n> The Arm backend sets the default sched-pressure algorithm to\n> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this \n> speeds up floating point performance on SPEC - eg. CactusBSSN improves\n> by ~16%. The gains are mostly due to less spilling, so enable this on AArch64\n> by default.\n\nHi Wilco,\n\nAny notable regressions?\n\n> \n> OK for commit?\n\nLooks good to me.\n\n--\nMaxim Kuvyrkov\nwww.linaro.org\n\n> \n> 2017-11-02 Wilco Dijkstra \n> \n> \t* config/aarch64/aarch64.c (aarch64_override_options_internal):\n> \tSet PARAM_SCHED_PRESSURE_ALGORITHM to SCHED_PRESSURE_MODEL.\n> \n> --\n> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\n> index 34456e96497ac7b6d2f9931187ff05619e1934a4..750b0bc29c0963742d5d7bb4ae4619d93bec3e4a 100644\n> --- a/gcc/config/aarch64/aarch64.c\n> +++ b/gcc/config/aarch64/aarch64.c\n> @@ -9276,6 +9276,11 @@ aarch64_override_options_internal (struct gcc_options *opts)\n> \t\t\t opts->x_param_values,\n> \t\t\t global_options_set.x_param_values);\n> \n> + /* Use the alternative scheduling-pressure algorithm by default. */\n> + maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,\n> +\t\t\t opts->x_param_values,\n> +\t\t\t global_options_set.x_param_values);\n> +\n> /* Enable sw prefetching at specified optimization level for\n> CPUS that have prefetch. Lower optimization level threshold by 1\n> when profiling is enabled. */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-466004-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"drdqfSsn\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yVplD0HqDz9s7c\n\tfor ;\n\tMon, 6 Nov 2017 21:31:51 +1100 (AEDT)","(qmail 15818 invoked by alias); 6 Nov 2017 10:31:43 -0000","(qmail 15262 invoked by uid 89); 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CactusBSSN improves\n> > by ~16%.  The gains are mostly due to less spilling, so enable this on AArch64\n> > by default.\n>\n> Hi Wilco,\n>\n> Any notable regressions?\n\nNo, nothing that stands out. There were a few regressions on Cortex-A57 but none\nreproduced on Cortex-A72, so they are not real regressions. The gains do reproduce\nand instruction counts are lower (most binaries show a significant reduction in spills).\n\nWilco","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-466018-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"Dx6m7Bev\"; dkim-atps=neutral","sourceware.org; auth=none","spf=none (sender IP is )\n\tsmtp.mailfrom=Wilco.Dijkstra@arm.com; "],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yVt8P6t29z9s7h\n\tfor ;\n\tTue, 7 Nov 2017 00:05:24 +1100 (AEDT)","(qmail 26569 invoked by alias); 6 Nov 2017 13:05:17 -0000","(qmail 26558 invoked by uid 89); 6 Nov 2017 13:05:16 -0000","from mail-ve1eur01on0089.outbound.protection.outlook.com (HELO\n\tEUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.89)\n\tby sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with\n\tESMTP; Mon, 06 Nov 2017 13:05:08 +0000","from HE1PR0801MB2058.eurprd08.prod.outlook.com (10.168.95.23) by\n\tHE1PR0801MB2059.eurprd08.prod.outlook.com (10.168.95.135)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.178.6; Mon, 6 Nov 2017 13:05:04 +0000","from HE1PR0801MB2058.eurprd08.prod.outlook.com\n\t([fe80::92d:103c:a7c1:d911]) by\n\tHE1PR0801MB2058.eurprd08.prod.outlook.com\n\t([fe80::92d:103c:a7c1:d911%17]) with mapi id 15.20.0178.012;\n\tMon, 6 Nov 2017 13:05:04 +0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:cc:subject:date:message-id:references:in-reply-to\n\t:content-type:content-transfer-encoding:mime-version; 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Benchmarking on AArch64 shows this\n>> > speeds up floating point performance on SPEC - eg. CactusBSSN improves\n>> > by ~16%. The gains are mostly due to less spilling, so enable this on AArch64\n>> > by default.\n>>\n>> Hi Wilco,\n>>\n>> Any notable regressions?\n>\n> No, nothing that stands out. There were a few regressions on Cortex-A57 but none\n> reproduced on Cortex-A72, so they are not real regressions. The gains do reproduce\n> and instruction counts are lower (most binaries show a significant reduction in spills).\n>\n> Wilco\n\nHi Wilco,\n\nAfter you committed this patch (r254378), I noticed a few regressions:\nFAIL: gcc.target/aarch64/subs_compare_1.c scan-assembler-not\ncmp\\\\tw[0-9]+, w[0-9]+\nFAIL: gcc.target/aarch64/subs_compare_1.c scan-assembler-times\nsubs\\\\tw[0-9]+, w[0-9]+, w[0-9]+ 1 (found 0 times)\nFAIL: gcc.target/aarch64/subs_compare_2.c scan-assembler-times\nsubs\\\\tw[0-9]+, w[0-9]+, #4 1 (found 0 times)\n\nI'm still catching-up, so maybe you already fixed this in a subsequent commit?\n(It's still failing in my most recent validation to date, r254467).\n\nThanks,\n\nChristophe","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-466643-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"raVcrBh7\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ybBbS64V9z9sPr\n\tfor ;\n\tTue, 14 Nov 2017 00:40:19 +1100 (AEDT)","(qmail 8224 invoked by alias); 13 Nov 2017 13:40:11 -0000","(qmail 8207 invoked by uid 89); 13 Nov 2017 13:40:10 -0000","from mail-ua0-f195.google.com (HELO mail-ua0-f195.google.com)\n\t(209.85.217.195) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 13 Nov 2017 13:40:08 +0000","by mail-ua0-f195.google.com with SMTP id s28so5288521uag.4 for\n\t; Mon, 13 Nov 2017 05:40:08 -0800 (PST)","by 10.103.94.66 with HTTP; Mon, 13 Nov 2017 05:40:06 -0800 (PST)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; q=dns; s=default; b=xHHoUpRi2kWXnH7\n\tyLCE2ZhmcueqRFjHir5SnuPGotSakg7Y2/AdIfurF55gDXNvk31Qb486izZ9VaN7\n\tGJZbbdYRNuGH7AaM61FwiASsiIHlGE9RSbdxBRp5lj0iXoLGJcla4KDVPNHMuAK3\n\tNWwNeUqKsNyFVNWb5LvYAbfg3vb4=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; s=default; bh=4jEw0iebqjtFw2TFqDO2D\n\tiy30c4=; b=raVcrBh71Nz+pzHkK/6hCqHkVTr2pKL3yfN70lCVL7mCoKwibV5Gm\n\t8vpnB6wWxVzsYIMbjI4PszFtxJcuzCNvZXM5ImAqrvuvZWHWVYpyniw+AjEIG4z4\n\tTu49NOCIvGdPij42PaW1LkiZ/YLrsnyKtiOt3oxkwCvV4o8IN0+H8k=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.3 required=5.0 tests=AWL, BAYES_00,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=no version=3.3.2 spammy=speeds, reproduced","X-HELO":"mail-ua0-f195.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=IOrotT1rGA3Hm5V6NnZn0obDTQq3rfut8hYLwUY4mSc=;\n\tb=P5EE0uUyzbuPsFtDBbXWio+YUU5vXDEM5bxMeWs4XRn9H8I6RReg2t8MOLqEC/q6w4\n\t70fO9mC8bpfIO/Dd8BPiucYfa4K8LhWBIpwkDW2otYE6Er0mQPI3Xfx4St1lhFy3HfUr\n\tD8H0D1vZVe6b9lWfUHLbb5jU/HjmEq79c2wBQRjPUY0knLJrfpy54TkJJ8PcNdSjuibX\n\trKJ4R8/2mWm0flct96mdtfJGsFYceDu+UWpM6XEeLKLJFJ5gNq4AUf3xeby5TiHksBnj\n\tBEjOlUtlIofpypbW5yDRKFqVIm6ynxyZINBo0u1XbNC0qn7ybCi+U+fn25pfxStHABBk\n\tHsWQ==","X-Gm-Message-State":"AJaThX6jWk5tgla65b0dAQdppM9CLbSUS0Oa67CVcWLKwWe1N/REWOb8\tvobSrLZV1TRd2z3d2Gd7bxFKSGGfPoTl/JHhGmXYuw==","X-Google-Smtp-Source":"AGs4zMYVRmngHE/Fx+xnwQv0x2AOe2C9AAy3vFaLIRF75hHYyng9hDPgM/v4uQTOzqC/Fm/dXFJAw2HcNsKyw7rLPCk=","X-Received":"by 10.176.81.181 with SMTP id g50mr960625uaa.46.1510580406819;\n\tMon, 13 Nov 2017 05:40:06 -0800 (PST)","MIME-Version":"1.0","In-Reply-To":"","References":"\n\t<2EE93A11-4394-4CA9-AD9A-54E992F21095@linaro.org>\n\t","From":"Christophe Lyon ","Date":"Mon, 13 Nov 2017 14:40:06 +0100","Message-ID":"","Subject":"Re: [PATCH][AArch64] Set default sched pressure algorithm","To":"Wilco Dijkstra ","Cc":"Maxim Kuvyrkov ,\n\tGCC Patches , nd ,\n\t\"Andrew.pinski@cavium.com\" ","Content-Type":"text/plain; charset=\"UTF-8\"","X-IsSubscribed":"yes"}}]