[{"id":1797837,"web_url":"http://patchwork.ozlabs.org/comment/1797837/","msgid":"","list_archive_url":null,"date":"2017-11-02T11:43:46","subject":"Re: [Qemu-devel] [PATCH v2] translate.c: Fix usermode big-endian\n\tAArch32 LDREXD and STREXD","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 11/02/2017 12:33 PM, Peter Maydell wrote:\n> For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the\n> lowest address is always Rt and the one at addr+4 is Rt2, even if the\n> CPU is big-endian. Our implementation does these with a single\n> 64-bit store, so if we're big-endian then we need to put the two\n> 32-bit halves together in the opposite order to little-endian,\n> so that they end up in the right places. We were trying to do\n> this with the gen_aa32_frob64() function, but that is not correct\n> for the usermode emulator, because there there is a distinction\n> between \"load a 64 bit value\" (which does a BE 64-bit access\n> and doesn't need swapping) and \"load two 32 bit values as one\n> 64 bit access\" (where we still need to do the swapping, like\n> system mode BE32).\n> \n> Fixes: https://bugs.launchpad.net/qemu/+bug/1725267\n> Cc: qemu-stable@nongnu.org\n> Signed-off-by: Peter Maydell \n> ---\n> Changes v1->v2:\n> * use correct \"s->be_data == MO_BE\" check for bigendian\n> * don't mangle the data from the atomic-cmpxchg before\n> comparing against expected value\n> * tcg_temp_free() the TCGv from gen_aa32_addr()\n> * name that TCGv \"taddr\" rather than \"a\"...\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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