[{"id":1799460,"web_url":"http://patchwork.ozlabs.org/comment/1799460/","msgid":"<20171106061639.GA7813@umbus.fritz.box>","list_archive_url":null,"date":"2017-11-06T06:16:39","subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Thu, Nov 02, 2017 at 11:35:59AM +0100, Luc MICHEL wrote:\n> When overwritting a valid TLB entry with a new one, the previous page\n> were not flushed in QEMU TLB, leading to incoherent mapping. This commit\n> fixes this.\n\nI don't think this is right. As a rule, overwriting a TLB entry\ndoesn't necessarily invalidate the previous entry, even on real\nhardware. I don't know exactly what the situation is on the various\nFSL BookE chips, but I know various other models have other caches\nahead of the main TLB which can cache mappings that have been removed\nfrom it (e.g. the ERAT on server chips and the shadow TLBs on 4xx).\n\nTo invalidate those other caches requires something other than simply\na tlbwe (tlbie for the ERAT and an isync for the shadow TLBs).\n\nThe current behaviour won't exactly match what hardware does (and it's\nprobably not practical to do so), but it should be within what's\npermitted by the architecture - and therefore good enough for correct\nguests.\n\nIt's possible that we do need this for the BookE chips, but it'll need\na more detailed rationale.\n\n> \n> Signed-off-by: Luc MICHEL \n> ---\n> target/ppc/mmu_helper.c | 23 ++++++++++++++++++-----\n> 1 file changed, 18 insertions(+), 5 deletions(-)\n> \n> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c\n> index 2a1f9902c9..c2c89239b4 100644\n> --- a/target/ppc/mmu_helper.c\n> +++ b/target/ppc/mmu_helper.c\n> @@ -2570,6 +2570,17 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)\n> tlb_flush(CPU(cpu));\n> }\n> \n> +static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)\n> +{\n> + PowerPCCPU *cpu = ppc_env_get_cpu(env);\n> +\n> + if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {\n> + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);\n> + } else {\n> + tlb_flush(CPU(cpu));\n> + }\n> +}\n> +\n> void helper_booke206_tlbwe(CPUPPCState *env)\n> {\n> PowerPCCPU *cpu = ppc_env_get_cpu(env);\n> @@ -2628,6 +2639,12 @@ void helper_booke206_tlbwe(CPUPPCState *env)\n> if (msr_gs) {\n> cpu_abort(CPU(cpu), \"missing HV implementation\\n\");\n> }\n> +\n> + if (tlb->mas1 & MAS1_VALID) {\n> + /* Invalidate the page in QEMU TLB if it was a valid entry */\n> + flush_page(env, tlb);\n> + }\n> +\n> tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |\n> env->spr[SPR_BOOKE_MAS3];\n> tlb->mas1 = env->spr[SPR_BOOKE_MAS1];\n> @@ -2663,11 +2680,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)\n> tlb->mas1 &= ~MAS1_IPROT;\n> }\n> \n> - if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {\n> - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);\n> - } else {\n> - tlb_flush(CPU(cpu));\n> - }\n> + flush_page(env, tlb);\n> }\n> \n> static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"SKZ7sxXI\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yVj5c36jmz9s7m\n\tfor ;\n\tMon, 6 Nov 2017 17:17:23 +1100 (AEDT)","from localhost ([::1]:46630 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1eBail-0007Sy-Pd\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Nov 2017 01:17:19 -0500","from eggs.gnu.org ([2001:4830:134:3::10]:40627)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1eBaiO-0007Sq-IZ\n\tfor qemu-devel@nongnu.org; Mon, 06 Nov 2017 01:16:57 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1eBaiN-0001Sn-3q\n\tfor qemu-devel@nongnu.org; Mon, 06 Nov 2017 01:16:56 -0500","from ozlabs.org ([2401:3900:2:1::2]:42301)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1eBaiM-0001FL-Kk; Mon, 06 Nov 2017 01:16:55 -0500","by ozlabs.org (Postfix, from userid 1007)\n\tid 3yVj4s0p1Yz9s7p; Mon, 6 Nov 2017 17:16:45 +1100 (AEDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1509949005;\n\tbh=zBPQ4Qkp8f3d5h1Uw1Kba9kueoq1ROErTRcF8d/uPIA=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=SKZ7sxXIHhxej8QPnVXpdBPQMF7xH4zuE7nFmFyHiTba8U2/tTTVQeFjsY/iQt0mn\n\tr533ZJ23nK1+Ost1+srnm94caT1Sla96ej/sdOdFM6fRoRIX7d+DD57lH6lZoCQiU6\n\t9LBg7EegEHrLT0FOyJnGw+21Yec0a+Pl2FKzdHCE=","Date":"Mon, 6 Nov 2017 17:16:39 +1100","From":"David Gibson ","To":"Luc MICHEL ","Message-ID":"<20171106061639.GA7813@umbus.fritz.box>","References":"<20171102103559.7382-1-luc.michel@git.antfield.fr>\n\t<20171102103559.7382-2-luc.michel@git.antfield.fr>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"BOKacYhQ+x31HxR3\"","Content-Disposition":"inline","In-Reply-To":"<20171102103559.7382-2-luc.michel@git.antfield.fr>","User-Agent":"Mutt/1.9.1 (2017-09-22)","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tAlexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1804508,"web_url":"http://patchwork.ozlabs.org/comment/1804508/","msgid":"<2f6bae4a-3489-5cb9-766c-5b8c6c447ac8@antfield.fr>","list_archive_url":null,"date":"2017-11-14T16:28:48","subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","submitter":{"id":72813,"url":"http://patchwork.ozlabs.org/api/people/72813/","name":"Luc Michel","email":"luc.michel@antfield.fr"},"content":"On 11/06/2017 07:16 AM, David Gibson wrote:\n> On Thu, Nov 02, 2017 at 11:35:59AM +0100, Luc MICHEL wrote:\n>> When overwritting a valid TLB entry with a new one, the previous page\n>> were not flushed in QEMU TLB, leading to incoherent mapping. This commit\n>> fixes this.\n> \n> I don't think this is right. As a rule, overwriting a TLB entry\n> doesn't necessarily invalidate the previous entry, even on real\n> hardware. I don't know exactly what the situation is on the various\n> FSL BookE chips, but I know various other models have other caches\n> ahead of the main TLB which can cache mappings that have been removed\n> from it (e.g. the ERAT on server chips and the shadow TLBs on 4xx).\nIndeed, e500 cores have a two-level TLB. tlbwe writes in L2, and L1 is\nhandled by the hardware and not visible to the user.\n\n> \n> To invalidate those other caches requires something other than simply\n> a tlbwe (tlbie for the ERAT and an isync for the shadow TLBs).\nYes you are right. From \"EREF 2.0: A Programmer’s Reference Manual for\nFreescale Power Architecture Processors, Rev. 0\":\n\n\"A context synchronizing instruction is required after a tlbwe\ninstruction to ensure any subsequent instructions that will use the\nupdated TLB values execute in the new context.\"\n\nLinux executes a msync followed by a isync after a tlbwe for BookE MMU\nmachines.\n\n> \n> The current behaviour won't exactly match what hardware does (and it's\n> probably not practical to do so), but it should be within what's\n> permitted by the architecture - and therefore good enough for correct\n> guests.\n> \n> It's possible that we do need this for the BookE chips, but it'll need\n> a more detailed rationale.\nThe one sentence from the \"PowerPC e500 Core Family Reference Manual,\nRev. 1\" document that makes my fix kind of correct is this one:\n\nIn 12.4.2 TLB Write Entry (tlbwe) Instruction:\n\n\"Note that when an L2 TLB entry is written, it may be displacing an\nalready valid entry in the same L2 TLB location (a victim). If a valid\nL1 TLB entry corresponds to the L2 MMU victim entry, that L1 TLB entry\nis automatically invalidated.\"\n\nAt least, it is as correct as the current tlb_flush in\n\"helper_booke206_tlbwe\" function, since it does not wait for isync to\neffectively invalidate the page.\n\n> \n>>\n>> Signed-off-by: Luc MICHEL \n>> ---\n>> target/ppc/mmu_helper.c | 23 ++++++++++++++++++-----\n>> 1 file changed, 18 insertions(+), 5 deletions(-)\n>>\n>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c\n>> index 2a1f9902c9..c2c89239b4 100644\n>> --- a/target/ppc/mmu_helper.c\n>> +++ b/target/ppc/mmu_helper.c\n>> @@ -2570,6 +2570,17 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)\n>> tlb_flush(CPU(cpu));\n>> }\n>> \n>> +static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)\n>> +{\n>> + PowerPCCPU *cpu = ppc_env_get_cpu(env);\n>> +\n>> + if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {\n>> + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);\n>> + } else {\n>> + tlb_flush(CPU(cpu));\n>> + }\n>> +}\n>> +\n>> void helper_booke206_tlbwe(CPUPPCState *env)\n>> {\n>> PowerPCCPU *cpu = ppc_env_get_cpu(env);\n>> @@ -2628,6 +2639,12 @@ void helper_booke206_tlbwe(CPUPPCState *env)\n>> if (msr_gs) {\n>> cpu_abort(CPU(cpu), \"missing HV implementation\\n\");\n>> }\n>> +\n>> + if (tlb->mas1 & MAS1_VALID) {\n>> + /* Invalidate the page in QEMU TLB if it was a valid entry */\n>> + flush_page(env, tlb);\n>> + }\n>> +\n>> tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |\n>> env->spr[SPR_BOOKE_MAS3];\n>> tlb->mas1 = env->spr[SPR_BOOKE_MAS1];\n>> @@ -2663,11 +2680,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)\n>> tlb->mas1 &= ~MAS1_IPROT;\n>> }\n>> \n>> - if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {\n>> - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);\n>> - } else {\n>> - tlb_flush(CPU(cpu));\n>> - }\n>> + flush_page(env, tlb);\n>> }\n>> \n>> static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Tue, 14 Nov 2017 11:27:17 -0500","from bee.antfield.fr ([188.165.75.195]:46652)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1eEe3M-0003yv-Qw; Tue, 14 Nov 2017 11:27:13 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=simple/simple; d=antfield.fr; s=mail;\n\tt=1510676829; bh=BhOHIN+tOmO0d/3Wp3SZ3dcEhA6/HwalNi62xnnYH64=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=ZfBjJeIy1oFKJDyuqfgExAeHwTTrJjBLbKO39GkgtN2io3hawKW/h3C8GzN+Vki0g\n\tnAU02h7tr0ZExMiaqIQ7bxWRNtNWwkJvEVE+frr0WRoVzgM4h0Rzp+zQU3rgNu7omi\n\tqLBCXLd56yO0w3Ns7E3tGi9mOv7d7OOeEm64vVMQ=","To":"David Gibson ,\n\tLuc MICHEL ","References":"<20171102103559.7382-1-luc.michel@git.antfield.fr>\n\t<20171102103559.7382-2-luc.michel@git.antfield.fr>\n\t<20171106061639.GA7813@umbus.fritz.box>","From":"Luc Michel ","Message-ID":"<2f6bae4a-3489-5cb9-766c-5b8c6c447ac8@antfield.fr>","Date":"Tue, 14 Nov 2017 17:28:48 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<20171106061639.GA7813@umbus.fritz.box>","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"Hb4n75hCEVwgJqaT6TqBiVHCs1qjGgsqi\"","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"188.165.75.195","X-Mailman-Approved-At":"Tue, 14 Nov 2017 11:50:21 -0500","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tAlexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1823081,"web_url":"http://patchwork.ozlabs.org/comment/1823081/","msgid":"<20171215124657.GH7753@umbus.fritz.box>","list_archive_url":null,"date":"2017-12-15T12:46:57","subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Tue, Nov 14, 2017 at 05:28:48PM +0100, Luc Michel wrote:\n> On 11/06/2017 07:16 AM, David Gibson wrote:\n> > On Thu, Nov 02, 2017 at 11:35:59AM +0100, Luc MICHEL wrote:\n> >> When overwritting a valid TLB entry with a new one, the previous page\n> >> were not flushed in QEMU TLB, leading to incoherent mapping. This commit\n> >> fixes this.\n> > \n> > I don't think this is right. As a rule, overwriting a TLB entry\n> > doesn't necessarily invalidate the previous entry, even on real\n> > hardware. I don't know exactly what the situation is on the various\n> > FSL BookE chips, but I know various other models have other caches\n> > ahead of the main TLB which can cache mappings that have been removed\n> > from it (e.g. the ERAT on server chips and the shadow TLBs on 4xx).\n> Indeed, e500 cores have a two-level TLB. tlbwe writes in L2, and L1 is\n> handled by the hardware and not visible to the user.\n> \n> > \n> > To invalidate those other caches requires something other than simply\n> > a tlbwe (tlbie for the ERAT and an isync for the shadow TLBs).\n> Yes you are right. From \"EREF 2.0: A Programmer’s Reference Manual for\n> Freescale Power Architecture Processors, Rev. 0\":\n> \n> \"A context synchronizing instruction is required after a tlbwe\n> instruction to ensure any subsequent instructions that will use the\n> updated TLB values execute in the new context.\"\n> \n> Linux executes a msync followed by a isync after a tlbwe for BookE MMU\n> machines.\n> \n> > \n> > The current behaviour won't exactly match what hardware does (and it's\n> > probably not practical to do so), but it should be within what's\n> > permitted by the architecture - and therefore good enough for correct\n> > guests.\n> > \n> > It's possible that we do need this for the BookE chips, but it'll need\n> > a more detailed rationale.\n> The one sentence from the \"PowerPC e500 Core Family Reference Manual,\n> Rev. 1\" document that makes my fix kind of correct is this one:\n> \n> In 12.4.2 TLB Write Entry (tlbwe) Instruction:\n> \n> \"Note that when an L2 TLB entry is written, it may be displacing an\n> already valid entry in the same L2 TLB location (a victim). If a valid\n> L1 TLB entry corresponds to the L2 MMU victim entry, that L1 TLB entry\n> is automatically invalidated.\"\n\nThat does seem fairly clear. If you resend the patch with that\nparagraph cited in a comment, I'll apply it. A link to the reference\nmanual would also be appreciated.\n\n> At least, it is as correct as the current tlb_flush in\n> \"helper_booke206_tlbwe\" function, since it does not wait for isync to\n> effectively invalidate the page.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"A7ooWmPg\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yyqw34tVbz9t1t\n\tfor ;\n\tFri, 15 Dec 2017 23:47:47 +1100 (AEDT)","from localhost ([::1]:46033 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1ePpOz-0006tl-2w\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Dec 2017 07:47:45 -0500","from eggs.gnu.org ([2001:4830:134:3::10]:53812)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1ePpOR-0006mG-Ik\n\tfor qemu-devel@nongnu.org; Fri, 15 Dec 2017 07:47:12 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1ePpOQ-0004pk-GD\n\tfor qemu-devel@nongnu.org; Fri, 15 Dec 2017 07:47:11 -0500","from ozlabs.org ([2401:3900:2:1::2]:33733)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1ePpOQ-0004hu-05; Fri, 15 Dec 2017 07:47:10 -0500","by ozlabs.org (Postfix, from userid 1007)\n\tid 3yyqvG6kpqz9t2Z; Fri, 15 Dec 2017 23:47:06 +1100 (AEDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1513342026;\n\tbh=w61tZ4CSNv5BLmIB8UPU8TiYh7MpwcNtr/z0mZlUm70=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=A7ooWmPgP4tmdO3jhqjyrOhmoazDee9ukd3qErdYnFBzl+8ZMM3tuqSU+g0dDVN3e\n\tY8dkEaGZRPlaHCleKUOSgBAkO/rT3X4hQx/XDqqaXR/qkbmW8mf9Wdd+wlSfpyjadn\n\tJOm4q4LYIcBpHkP3D/RtZRRPUrtZeWDZgUluTj1g=","Date":"Fri, 15 Dec 2017 23:46:57 +1100","From":"David Gibson ","To":"Luc Michel ","Message-ID":"<20171215124657.GH7753@umbus.fritz.box>","References":"<20171102103559.7382-1-luc.michel@git.antfield.fr>\n\t<20171102103559.7382-2-luc.michel@git.antfield.fr>\n\t<20171106061639.GA7813@umbus.fritz.box>\n\t<2f6bae4a-3489-5cb9-766c-5b8c6c447ac8@antfield.fr>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"smOfPzt+Qjm5bNGJ\"","Content-Disposition":"inline","In-Reply-To":"<2f6bae4a-3489-5cb9-766c-5b8c6c447ac8@antfield.fr>","User-Agent":"Mutt/1.9.1 (2017-09-22)","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"Re: [Qemu-devel] [PATCH 1/1] target-ppc: Fix booke206 tlbwe TLB\n\tinstruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexander Graf , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Luc MICHEL ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]