[{"id":1799849,"web_url":"http://patchwork.ozlabs.org/comment/1799849/","msgid":"<20171106171519.xomnca72adqtzm2n@rob-hp-laptop>","list_archive_url":null,"date":"2017-11-06T17:15:19","subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Nov 02, 2017 at 02:56:17PM +0800, Chunyan Zhang wrote:\n> Introduce a new binding with its documentation for Spreadtrum clock\n> sub-framework.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> Documentation/devicetree/bindings/clock/sprd.txt | 55 ++++++++++++++++++++++++\n> 1 file changed, 55 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt\n> \n> diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt\n> new file mode 100644\n> index 0000000..5c09529\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/sprd.txt\n> @@ -0,0 +1,55 @@\n> +Spreadtrum Clock Binding\n> +------------------------\n> +\n> +Required properties:\n> +- compatible: should contain the following compatible strings:\n> +\t- \"sprd,sc9860-pmu-gate\"\n> +\t- \"sprd,sc9860-pll\"\n> +\t- \"sprd,sc9860-ap-clk\"\n> +\t- \"sprd,sc9860-aon-prediv\"\n> +\t- \"sprd,sc9860-apahb-gate\"\n> +\t- \"sprd,sc9860-aon-gate\"\n> +\t- \"sprd,sc9860-aonsecure-clk\"\n> +\t- \"sprd,sc9860-agcp-gate\"\n> +\t- \"sprd,sc9860-gpu-clk\"\n> +\t- \"sprd,sc9860-vsp-clk\"\n> +\t- \"sprd,sc9860-vsp-gate\"\n> +\t- \"sprd,sc9860-cam-clk\"\n> +\t- \"sprd,sc9860-cam-gate\"\n> +\t- \"sprd,sc9860-disp-clk\"\n> +\t- \"sprd,sc9860-disp-gate\"\n> +\t- \"sprd,sc9860-apapb-gate\"\n> +\n> +- #clock-cells: must be 1\n> +\n> +- clocks : shall be the input parent clock(s) phandle for the clock.\n\nYou need to document how many clocks for each block.\n\n> +\n> +Optional properties:\n> +\n> +- reg:\tContain the registers base address and length. It must be configured only if no 'sprd,syscon' under the node.\n> +\n> +- sprd,syscon: phandle to the syscon which is in the same address area with the clock.\n> +\n> +Example:\n> +\n> +\tpmu_gate: pmu-gate {\n> +\t\tcompatible = \"sprd,sc9860-pmu-gate\";\n> +\t\tsprd,syscon = <&pmu_apb>;\n\nIdeally, the pmu-gate node would be a child of pmu_apb and use the reg \nproperty if clock registers are a contiguous range. Then you don't need \nthis phandle.\n\n> +\t\tclocks = <&ext_26m>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tpll: pll {\n> +\t\tcompatible = \"sprd,sc9860-pll\";\n> +\t\tsprd,syscon = <&ana_apb>;\n\nSame here.\n\n> +\t\tclocks = <&pmu_gate 0>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tap_clk: clock-controller@20000000 {\n> +\t\tcompatible = \"sprd,sc9860-ap-clk\";\n> +\t\treg = <0 0x20000000 0 0x400>;\n> +\t\tclocks = <&ext_26m>, <&pll 0>,\n> +\t\t\t <&pmu_gate 0>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> -- \n> 2.7.4\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yVzhr5hfkz9s7C\n\tfor ;\n\tTue, 7 Nov 2017 04:15:24 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752496AbdKFRPW (ORCPT\n\t);\n\tMon, 6 Nov 2017 12:15:22 -0500","from mail-ot0-f196.google.com ([74.125.82.196]:47256 \"EHLO\n\tmail-ot0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751976AbdKFRPV (ORCPT\n\t); Mon, 6 Nov 2017 12:15:21 -0500","by mail-ot0-f196.google.com with SMTP id s88so9629842ota.4;\n\tMon, 06 Nov 2017 09:15:21 -0800 (PST)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\te6sm6312976otd.1.2017.11.06.09.15.19\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 06 Nov 2017 09:15:20 -0800 (PST)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=Am7fpYFxyzfHm7X3gFPcjnY8lc4XpLOVIwtLo1RCvHE=;\n\tb=NUmF9wvDPZR0as6rj1LJ90mGDOmGoz9KZPOvfICtCQzMG9g8KVlEK8OJQDH4UyY+cU\n\tXyepMJ0AvsRqC21Y26+Y29HveCaMN74YsOo2cmX13dD2pmoI+Sw39bVGgls5GPvTddNY\n\tcEAKT4BruDoCW6ZqSMrmxTLxVoBF9JrIqO3ccrq2HRY/aZE0uct4arAHzb149JMkBIs6\n\tawXbgcRmRbIRpfv0YEomdtxAtTNubBbAgDPYkhT9f+PXwrSiqDIw0IPtjeejF7XSn7es\n\txIUE6BWhtioRM7DOfK35HNuPwct5zMCz3A2P/+VhZosCZ7GIpJPe1x2xRTrRuoRpBKYA\n\tjAMw==","X-Gm-Message-State":"AJaThX5UtJFpnNvpV2BvsSfmPhsvIAEIuzlgBzKrKIwMzmfNC0XSiC3c\n\tybLbsGCoiamEXNJomyWIQw==","X-Google-Smtp-Source":"ABhQp+QumlSDDVwgk+YibvtteyZSoNPn7cU4opEGGZXhxx4/Y8WyzSILYbIYm3SvBCpt0w7D2yRJrA==","X-Received":"by 10.157.22.187 with SMTP id c56mr10465764ote.364.1509988520738;\n\tMon, 06 Nov 2017 09:15:20 -0800 (PST)","Date":"Mon, 6 Nov 2017 11:15:19 -0600","From":"Rob Herring ","To":"Chunyan Zhang ","Cc":"Stephen Boyd ,\n\tMichael Turquette ,\n\tMark Rutland ,\n\tCatalin Marinas ,\n\tWill Deacon , linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Arnd Bergmann ,\n\tMark Brown ,\n\tXiaolong Zhang ,\n\tBen Li ,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tOrson Zhai ,\n\tChunyan Zhang ","Subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","Message-ID":"<20171106171519.xomnca72adqtzm2n@rob-hp-laptop>","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-3-chunyan.zhang@spreadtrum.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171102065626.21835-3-chunyan.zhang@spreadtrum.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1800262,"web_url":"http://patchwork.ozlabs.org/comment/1800262/","msgid":"","list_archive_url":null,"date":"2017-11-07T07:01:09","subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Rob,\n\nOn 7 November 2017 at 01:15, Rob Herring wrote:\n> On Thu, Nov 02, 2017 at 02:56:17PM +0800, Chunyan Zhang wrote:\n>> Introduce a new binding with its documentation for Spreadtrum clock\n>> sub-framework.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> Documentation/devicetree/bindings/clock/sprd.txt | 55 ++++++++++++++++++++++++\n>> 1 file changed, 55 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt\n>>\n>> diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt\n>> new file mode 100644\n>> index 0000000..5c09529\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/clock/sprd.txt\n>> @@ -0,0 +1,55 @@\n>> +Spreadtrum Clock Binding\n>> +------------------------\n>> +\n>> +Required properties:\n>> +- compatible: should contain the following compatible strings:\n>> + - \"sprd,sc9860-pmu-gate\"\n>> + - \"sprd,sc9860-pll\"\n>> + - \"sprd,sc9860-ap-clk\"\n>> + - \"sprd,sc9860-aon-prediv\"\n>> + - \"sprd,sc9860-apahb-gate\"\n>> + - \"sprd,sc9860-aon-gate\"\n>> + - \"sprd,sc9860-aonsecure-clk\"\n>> + - \"sprd,sc9860-agcp-gate\"\n>> + - \"sprd,sc9860-gpu-clk\"\n>> + - \"sprd,sc9860-vsp-clk\"\n>> + - \"sprd,sc9860-vsp-gate\"\n>> + - \"sprd,sc9860-cam-clk\"\n>> + - \"sprd,sc9860-cam-gate\"\n>> + - \"sprd,sc9860-disp-clk\"\n>> + - \"sprd,sc9860-disp-gate\"\n>> + - \"sprd,sc9860-apapb-gate\"\n>> +\n>> +- #clock-cells: must be 1\n>> +\n>> +- clocks : shall be the input parent clock(s) phandle for the clock.\n>\n> You need to document how many clocks for each block.\n\nIt depends, \"clocks\" property here just simply shows which clock group\nthe clock's parents are in.\nThe detailed dependency relationship (i.e. how many parents and which\nare the parents) are implemented in driver code.\n\nOk, I should address more, will do in the next version.\n\n>\n>> +\n>> +Optional properties:\n>> +\n>> +- reg: Contain the registers base address and length. It must be configured only if no 'sprd,syscon' under the node.\n>> +\n>> +- sprd,syscon: phandle to the syscon which is in the same address area with the clock.\n>> +\n>> +Example:\n>> +\n>> + pmu_gate: pmu-gate {\n>> + compatible = \"sprd,sc9860-pmu-gate\";\n>> + sprd,syscon = <&pmu_apb>;\n>\n> Ideally, the pmu-gate node would be a child of pmu_apb and use the reg\n> property if clock registers are a contiguous range. Then you don't need\n> this phandle.\n\nThe pmu-gate is actually a clock independent from the 'pmu_apb' syscon\ndevice, using a reference to syscon node instead of a reg property is\njust to avoid mapping the same address areas repeatedly. Spreadtrum's\nclock h/w design is a little complicated, after discussing with Arnd\nand Stephen, I then chose to implement in this way.\n\nI guess the name of 'pmu_apb' might be confused, it's actually not a\nbus, but a global address area stored a lot of registers shared by a\nfew devices including some clocks. I think I'd better use another\nname instead of pmu_apb :)\n\nPlease let me know if I'm missing something here.\n\nThanks,\nChunyan\n\n>\n>> + clocks = <&ext_26m>;\n>> + #clock-cells = <1>;\n>> + };\n>> +\n>> + pll: pll {\n>> + compatible = \"sprd,sc9860-pll\";\n>> + sprd,syscon = <&ana_apb>;\n>\n> Same here.\n>\n>> + clocks = <&pmu_gate 0>;\n>> + #clock-cells = <1>;\n>> + };\n>> +\n>> + ap_clk: clock-controller@20000000 {\n>> + compatible = \"sprd,sc9860-ap-clk\";\n>> + reg = <0 0x20000000 0 0x400>;\n>> + clocks = <&ext_26m>, <&pll 0>,\n>> + <&pmu_gate 0>;\n>> + #clock-cells = <1>;\n>> + };\n>> --\n>> 2.7.4\n>>\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"j8tD3Wyh\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yWL2m0MJLz9t3k\n\tfor ;\n\tTue, 7 Nov 2017 18:02:07 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755014AbdKGHBx (ORCPT\n\t);\n\tTue, 7 Nov 2017 02:01:53 -0500","from mail-lf0-f66.google.com ([209.85.215.66]:50608 \"EHLO\n\tmail-lf0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755009AbdKGHBv (ORCPT\n\t); Tue, 7 Nov 2017 02:01:51 -0500","by mail-lf0-f66.google.com with SMTP id a132so13221393lfa.7;\n\tMon, 06 Nov 2017 23:01:50 -0800 (PST)","by 10.179.65.130 with HTTP; Mon, 6 Nov 2017 23:01:09 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=bHhgvXJ9X+P9p+qcAXO89OcNQgwoSIDSsGVpJE3L+Ug=;\n\tb=j8tD3WyhCMQ2wtzCdn7H9ap/5hFkCFMZCnmyQCYN7pvB5LDI7qqjmvsaqa6rrsyCql\n\tmXxzaRPe7eYl+Q/vhyliWAmPtw7Hpm+jXz+G+eYncDhAb66VTTydeTHhivCEi9xSN7P0\n\tEDgcuSCh8aPtyT53nEWaO2qp3IAJqhiDAxm0eTwNbDKBYiJ8+31hYXN58pTJQuREwk5w\n\tOOwkVKbtjfah8voZPOjEjMd0zp7nJ3AD+KboaLcHZduNtJzCy7Me22ptG8tpZ4mCYFGC\n\t84x632tMwU9nXNzV/3jchuH9tT92dQf0GLVoAkUG35qdUzVg39zWNoppfzIWKweJy9Qf\n\t708A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=bHhgvXJ9X+P9p+qcAXO89OcNQgwoSIDSsGVpJE3L+Ug=;\n\tb=SbMxrKP6zxEnJU/28hJ8GblE9TEASn+Drs5iHChpKfrFdfdJrMxV0PjLGkVxyJgSLA\n\tKH7qXZEsuFYuiytiyq7pNdvgIAhntkn2nmbVLOHvU0eSZRN5qwMwHi/KSbOHCz+c38HW\n\tAhj00+Znr0eooQ+ATRpmhWLRPEmIHoCoEbZMsmRYEItYyl23ASOCnno8akVqNTBd7FgJ\n\tzVf3lGeW7g4Lry4+4wfKZOkIxCZ1wj1gK0HkvZpg/tyd4REkpxF6tmDLZkk0C5kc9v1v\n\tnrIX+vcNBymVbk3UJHmUHZGVTSBvTvJDQ42NLPpkorwMR+xKl0hSyr2+WX8DBtyEiS+o\n\t2tuw==","X-Gm-Message-State":"AMCzsaX2ciORUPKNAIme8gjDWjQR+jfdYBKBzkAm1ZbdTJ9jFicxAHcF\n\t4AX93xrEZxVH1/9a1c/ELoRcpZ9h9ndBt8eC1S8k9w==","X-Google-Smtp-Source":"ABhQp+Rs36i06ppVxXAFRe+n0Z/d7R8pa+uyqE5ulZ2auQaS6VUl5HWO6flEtT8Rl3VVVZDNK1OAi3/l6dPSNUVAYYc=","X-Received":"by 10.46.43.69 with SMTP id q66mr6735445lje.104.1510038109867;\n\tMon, 06 Nov 2017 23:01:49 -0800 (PST)","MIME-Version":"1.0","In-Reply-To":"<20171106171519.xomnca72adqtzm2n@rob-hp-laptop>","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-3-chunyan.zhang@spreadtrum.com>\n\t<20171106171519.xomnca72adqtzm2n@rob-hp-laptop>","From":"Chunyan Zhang ","Date":"Tue, 7 Nov 2017 15:01:09 +0800","Message-ID":"","Subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","To":"Rob Herring ","Cc":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette ,\n\tMark Rutland ,\n\tCatalin Marinas ,\n\tWill Deacon ,\n\tlinux-clk , \n\t\"devicetree@vger.kernel.org\" ,\n\tArnd Bergmann , Mark Brown ,\n\tXiaolong Zhang ,\n\tBen Li , \"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tOrson Zhai ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]