[{"id":1794835,"web_url":"http://patchwork.ozlabs.org/comment/1794835/","msgid":"<20171027125622.75rqvb2kyr4wqhr4@armageddon.cambridge.arm.com>","list_archive_url":null,"date":"2017-10-27T12:56:22","subject":"Re: [PATCH v4 16/28] arm64/sve: Probe SVE capabilities and usable\n\tvector lengths","submitter":{"id":938,"url":"http://patchwork.ozlabs.org/api/people/938/","name":"Catalin Marinas","email":"catalin.marinas@arm.com"},"content":"On Fri, Oct 27, 2017 at 11:50:58AM +0100, Dave P Martin wrote:\n> This patch uses the cpufeatures framework to determine common SVE\n> capabilities and vector lengths, and configures the runtime SVE\n> support code appropriately.\n> \n> ZCR_ELx is not really a feature register, but it is convenient to\n> use it as a template for recording the maximum vector length\n> supported by a CPU, using the LEN field.  This field is similar to\n> a feature field in that it is a contiguous bitfield for which we\n> want to determine the minimum system-wide value.  This patch adds\n> ZCR as a pseudo-register in cpuinfo/cpufeatures, with appropriate\n> custom code to populate it.  Finding the minimum supported value of\n> the LEN field is left to the cpufeatures framework in the usual\n> way.\n> \n> The meaning of ID_AA64ZFR0_EL1 is not architecturally defined yet,\n> so for now we just require it to be zero.\n> \n> Note that much of this code is dormant and SVE still won't be used\n> yet, since system_supports_sve() remains hardwired to false.\n> \n> Signed-off-by: Dave Martin <Dave.Martin@arm.com>\n> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>\n> Cc: Alex Bennée <alex.bennee@linaro.org>\n> Cc: Catalin Marinas <catalin.marinas@arm.com>\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>","headers":{"Return-Path":"<libc-alpha-return-86473-incoming=patchwork.ozlabs.org@sourceware.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86473-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"SMje1sko\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNkQr74ySz9ryk\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 23:56:36 +1100 (AEDT)","(qmail 67942 invoked by alias); 27 Oct 2017 12:56:30 -0000","(qmail 67931 invoked by uid 89); 27 Oct 2017 12:56:29 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:content-transfer-encoding\n\t:in-reply-to; q=dns; s=default; b=hDzBnSq+qirltUzubOi3kMXkRsFnas\n\tmgIwC97v8/oG+zO14ZYLJ8tH36SWDUSVIA4rliqS2yfB6a5GhPrc6ShqD+qStK+l\n\to6qlZxv7arr2YplCrPF8divS7iDyrcIaLGs908BKIVjOXqKKtVEdF/EDgvRj3K6j\n\tgq09abO9aty1w=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:content-transfer-encoding\n\t:in-reply-to; s=default; bh=NPtfsj9WC6FqKB2M9CfwZLhvK0U=; b=SMje\n\t1skoBRMj8gmroaq3tb7rnrc9kg/jA04phsIfq4qWTRZWk6N5n6gHlYmnj1uHMr/p\n\tfW4s9+0NZQGWEtxEwtomrqaSHADr/p4Dv22ROnNDBhA8M/mfYyu86v3GIx0kQc3G\n\tIxJIDAacxjQ7BvjD9CiqQES462gVyrRcqGX2twg=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"<libc-alpha.sourceware.org>","List-Unsubscribe":"<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>","List-Subscribe":"<mailto:libc-alpha-subscribe@sourceware.org>","List-Archive":"<http://sourceware.org/ml/libc-alpha/>","List-Post":"<mailto:libc-alpha@sourceware.org>","List-Help":"<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-1.9 required=5.0 tests=BAYES_00,\n\tRP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Date":"Fri, 27 Oct 2017 13:56:22 +0100","From":"Catalin Marinas <catalin.marinas@arm.com>","To":"Dave Martin <Dave.Martin@arm.com>","Cc":"linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org,\n\tOkamoto Takayuki <tokamoto@jp.fujitsu.com>, \tlibc-alpha@sourceware.org,\n\tArd Biesheuvel <ard.biesheuvel@linaro.org>, Szabolcs Nagy\n\t<szabolcs.nagy@arm.com>, \tWill Deacon <will.deacon@arm.com>, Alex\n\t=?iso-8859-1?q?Benn=E9e?= <alex.bennee@linaro.org>,\n\tkvmarm@lists.cs.columbia.edu","Subject":"Re: [PATCH v4 16/28] arm64/sve: Probe SVE capabilities and usable\n\tvector lengths","Message-ID":"<20171027125622.75rqvb2kyr4wqhr4@armageddon.cambridge.arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>\n\t<1509101470-7881-17-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<1509101470-7881-17-git-send-email-Dave.Martin@arm.com>","User-Agent":"NeoMutt/20170113 (1.7.2)"}}]