[{"id":1795117,"web_url":"http://patchwork.ozlabs.org/comment/1795117/","msgid":"<20171027204513.GA105121@google.com>","list_archive_url":null,"date":"2017-10-27T20:45:17","subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","submitter":{"id":67074,"url":"http://patchwork.ozlabs.org/api/people/67074/","name":"Brian Norris","email":"briannorris@chromium.org"},"content":"Hi,\n\nOn Fri, Oct 27, 2017 at 03:26:06PM +0800, Jeffy Chen wrote:\n> We are going to handle PCIe WAKE# pin for PCI bus bridges and PCI\n> devices in the pci core, so add definitions of the optional PCIe\n> WAKE# pin for PCI bus bridges and PCI devices.\n> \n> Also add an definition of the optional PCI interrupt pin for PCI\n> devices to distinguish it from the PCIe WAKE# pin.\n> \n> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>\n> ---\n> \n> Changes in v10: None\n> Changes in v9:\n> Add section for PCI devices and rewrite the commit message.\n> \n> Changes in v8:\n> Add optional \"pci\", and rewrite commit message.\n> \n> Changes in v7: None\n> Changes in v6: None\n> Changes in v5:\n> Move to pci.txt\n> \n> Changes in v3: None\n> Changes in v2: None\n> \n>  Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++\n>  1 file changed, 8 insertions(+)\n> \n> diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt\n> index c77981c5dd18..d4406d4e15ad 100644\n> --- a/Documentation/devicetree/bindings/pci/pci.txt\n> +++ b/Documentation/devicetree/bindings/pci/pci.txt\n> @@ -24,3 +24,11 @@ driver implementation may support the following properties:\n>     unsupported link speed, for instance, trying to do training for\n>     unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'\n>     for gen2, and '1' for gen1. Any other values are invalid.\n> +- interrupts: Interrupt specifier for each name in interrupt-names.\n> +- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt.\n\ns/contains/contain/\n\n> +\n> +PCI devices have standardized Device Tree bindings:\n\nThis line is a little unclear, especially since there *is* an old\ndocumented standard, yet the following text is actually introducing new,\nnon-standard additions.\n\n> +\n> +- interrupts: Interrupt specifier for each name in interrupt-names.\n> +- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt and \"pci\" for\n\ns/contains/contain/\n\n> +  PCI interrupt.\n\nIMO, since you're trying to augment a standardized binding, you need to\nbe a lot clearer here. I expect you should mention the existing standard\n(that devices may optionally include an 'interrupts' property that\nrepresents the legacy PCI interrupt) and how you're augmenting it (that\nadditional interrupts can be supported optionally, but they require a\ncorresponding 'interrupt-names' property).\n\nAlso, is this binding only applying either to a host bridge or to\ndevices? No intermediate bridges or ports? It seems so, but I wanted to\nbe clear. (And it probably could be extended if needed. Notably, ACPI\nhas a tree-walk implementation, so if the device itself doesn't have\na wakeup config, it can look into any of its parents.)\n\nOnce you fix up the documentation...I suppose this looks like a sane\nidea. But I'd like 2nd opinions on this.\n\nBrian","headers":{"Return-Path":"<linux-pci-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=chromium.org header.i=@chromium.org\n\theader.b=\"RVOnM10H\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yNwr21BB7z9t48\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 28 Oct 2017 07:45:38 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932531AbdJ0UpW (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 27 Oct 2017 16:45:22 -0400","from mail-io0-f173.google.com ([209.85.223.173]:50814 \"EHLO\n\tmail-io0-f173.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932522AbdJ0UpV (ORCPT\n\t<rfc822; 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\n\tFri, 27 Oct 2017 13:45:20 -0700 (PDT)","Date":"Fri, 27 Oct 2017 13:45:17 -0700","From":"Brian Norris <briannorris@chromium.org>","To":"Jeffy Chen <jeffy.chen@rock-chips.com>","Cc":"linux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tlinux-pm@vger.kernel.org, tony@atomide.com,\n\tshawn.lin@rock-chips.com, rjw@rjwysocki.net, dianders@chromium.org,\n\tdevicetree@vger.kernel.org, linux-pci@vger.kernel.org,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>","Subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","Message-ID":"<20171027204513.GA105121@google.com>","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>\n\t<20171027072612.26565-2-jeffy.chen@rock-chips.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171027072612.26565-2-jeffy.chen@rock-chips.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-pci.vger.kernel.org>","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1797477,"web_url":"http://patchwork.ozlabs.org/comment/1797477/","msgid":"<20171101210541.vacfufnn2ms65xrw@rob-hp-laptop>","list_archive_url":null,"date":"2017-11-01T21:05:41","subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Oct 27, 2017 at 01:45:17PM -0700, Brian Norris wrote:\n> Hi,\n> \n> On Fri, Oct 27, 2017 at 03:26:06PM +0800, Jeffy Chen wrote:\n> > We are going to handle PCIe WAKE# pin for PCI bus bridges and PCI\n> > devices in the pci core, so add definitions of the optional PCIe\n> > WAKE# pin for PCI bus bridges and PCI devices.\n> > \n> > Also add an definition of the optional PCI interrupt pin for PCI\n> > devices to distinguish it from the PCIe WAKE# pin.\n> > \n> > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>\n> > ---\n> > \n> > Changes in v10: None\n> > Changes in v9:\n> > Add section for PCI devices and rewrite the commit message.\n> > \n> > Changes in v8:\n> > Add optional \"pci\", and rewrite commit message.\n> > \n> > Changes in v7: None\n> > Changes in v6: None\n> > Changes in v5:\n> > Move to pci.txt\n> > \n> > Changes in v3: None\n> > Changes in v2: None\n> > \n> >  Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++\n> >  1 file changed, 8 insertions(+)\n> > \n> > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt\n> > index c77981c5dd18..d4406d4e15ad 100644\n> > --- a/Documentation/devicetree/bindings/pci/pci.txt\n> > +++ b/Documentation/devicetree/bindings/pci/pci.txt\n> > @@ -24,3 +24,11 @@ driver implementation may support the following properties:\n> >     unsupported link speed, for instance, trying to do training for\n> >     unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'\n> >     for gen2, and '1' for gen1. Any other values are invalid.\n> > +- interrupts: Interrupt specifier for each name in interrupt-names.\n> > +- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt.\n> \n> s/contains/contain/\n> \n> > +\n> > +PCI devices have standardized Device Tree bindings:\n> \n> This line is a little unclear, especially since there *is* an old\n> documented standard, yet the following text is actually introducing new,\n> non-standard additions.\n> \n> > +\n> > +- interrupts: Interrupt specifier for each name in interrupt-names.\n> > +- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt and \"pci\" for\n> \n> s/contains/contain/\n> \n> > +  PCI interrupt.\n> \n> IMO, since you're trying to augment a standardized binding, you need to\n> be a lot clearer here. I expect you should mention the existing standard\n> (that devices may optionally include an 'interrupts' property that\n> represents the legacy PCI interrupt) and how you're augmenting it (that\n> additional interrupts can be supported optionally, but they require a\n> corresponding 'interrupt-names' property).\n\nThere's an additional complication that I'd guess the wakeup is \ntypically a GPIO line and hence a different parent. We have 2 options \nthere. The first is interrupts-extended which is generally implicitly \nsupported (i.e. we only document interrupts). The second is we already \nhave interrupt-map if we have legacy interrupts and can map to different \nparents. For this to work, we'd have to use a number >4 for the wakeup \ninterrupts.\n\nRob","headers":{"Return-Path":"<linux-pci-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yS13138RNz9t3v\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu,  2 Nov 2017 08:05:49 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933291AbdKAVFq (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 1 Nov 2017 17:05:46 -0400","from mail-oi0-f68.google.com ([209.85.218.68]:56347 \"EHLO\n\tmail-oi0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S933288AbdKAVFo (ORCPT\n\t<rfc822;linux-pci@vger.kernel.org>); Wed, 1 Nov 2017 17:05:44 -0400","by mail-oi0-f68.google.com with SMTP id v9so6479562oif.13;\n\tWed, 01 Nov 2017 14:05:43 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tl32sm711049otb.17.2017.11.01.14.05.42\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 01 Nov 2017 14:05:42 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=luXypYrY92iAiwfQ3fEAV9W5vxrlltJC2n4I4XykoYU=;\n\tb=SEXIbk0XwMhFUseMY9SiGOHliv98wyh+vAKWzrgta9UQjokLBPGKbgsoKyx/c0N11P\n\tPY0fOE8TWNQM5ZSgPncVoNvBDe+zMQBqJ8iPz7Rt85rA6lr9T8IWI7PlHtI0WEIMC3CC\n\tkYPHX9eJzrRlU30utCFAkJ+Lt/nkS/rOG35csVV2BlJs9O3fuzz+C071Ts4LU8N0F2Q6\n\tK+xzgjYxGSCjClBi01Eo+Esv79xOA5WUazMVJcyHN08SfOWTYqvXUact9HAKt0Bx2xyu\n\tN4wvrRIc3sLGtnznywAQ4r+OU/EYStlF8xpLN6DyvBiiMU75AhibmFJqsj9C4vL4mAQz\n\tTnmg==","X-Gm-Message-State":"AJaThX6yspxjj0SmmINZJ6G/v35m+3olq7zLOwH/mbn0xk5f1claQUSJ\n\t5UP0rWACPm2s0g0i1yPEpg==","X-Google-Smtp-Source":"ABhQp+Qka+k7DOg2dOfUiyfhu+f689AVyIbAzPtiG/T6vcbGBKrhxnUzN9cx1AWVeWRHjVkEsik9rg==","X-Received":"by 10.157.58.36 with SMTP id j33mr684919otc.75.1509570343340;\n\tWed, 01 Nov 2017 14:05:43 -0700 (PDT)","Date":"Wed, 1 Nov 2017 16:05:41 -0500","From":"Rob Herring <robh@kernel.org>","To":"Brian Norris <briannorris@chromium.org>","Cc":"Jeffy Chen <jeffy.chen@rock-chips.com>,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tlinux-pm@vger.kernel.org, tony@atomide.com,\n\tshawn.lin@rock-chips.com, rjw@rjwysocki.net, dianders@chromium.org,\n\tdevicetree@vger.kernel.org, linux-pci@vger.kernel.org,\n\tMark Rutland <mark.rutland@arm.com>","Subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","Message-ID":"<20171101210541.vacfufnn2ms65xrw@rob-hp-laptop>","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>\n\t<20171027072612.26565-2-jeffy.chen@rock-chips.com>\n\t<20171027204513.GA105121@google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171027204513.GA105121@google.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-pci.vger.kernel.org>","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1798301,"web_url":"http://patchwork.ozlabs.org/comment/1798301/","msgid":"<20171102215501.GD28152@atomide.com>","list_archive_url":null,"date":"2017-11-02T21:55:01","subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Rob Herring <robh@kernel.org> [171101 21:07]:\n> On Fri, Oct 27, 2017 at 01:45:17PM -0700, Brian Norris wrote:\n> > IMO, since you're trying to augment a standardized binding, you need to\n> > be a lot clearer here. I expect you should mention the existing standard\n> > (that devices may optionally include an 'interrupts' property that\n> > represents the legacy PCI interrupt) and how you're augmenting it (that\n> > additional interrupts can be supported optionally, but they require a\n> > corresponding 'interrupt-names' property).\n> \n> There's an additional complication that I'd guess the wakeup is \n> typically a GPIO line and hence a different parent. We have 2 options \n> there. The first is interrupts-extended which is generally implicitly \n> supported (i.e. we only document interrupts). The second is we already \n> have interrupt-map if we have legacy interrupts and can map to different \n> parents. For this to work, we'd have to use a number >4 for the wakeup \n> interrupts.\n\nThe wakeup interrupt can also be a separate always on interrupt\ncontroller in addition to GPIOs. Anyways, the interrupts-extended\nbinding works well for these. And the interrupt-names we seem\nto have standardized on are \"irq\" and \"wakeup\".\n\nRegards,\n\nTony","headers":{"Return-Path":"<linux-pci-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySf5S5Ngnz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri,  3 Nov 2017 08:55:08 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S964842AbdKBVzH (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 2 Nov 2017 17:55:07 -0400","from muru.com ([72.249.23.125]:46442 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S932201AbdKBVzG (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tThu, 2 Nov 2017 17:55:06 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 33FCA80F0;\n\tThu,  2 Nov 2017 21:56:40 +0000 (UTC)"],"Date":"Thu, 2 Nov 2017 14:55:01 -0700","From":"Tony Lindgren <tony@atomide.com>","To":"Rob Herring <robh@kernel.org>","Cc":"Brian Norris <briannorris@chromium.org>,\n\tJeffy Chen <jeffy.chen@rock-chips.com>,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tlinux-pm@vger.kernel.org, shawn.lin@rock-chips.com,\n\trjw@rjwysocki.net, dianders@chromium.org,\n\tdevicetree@vger.kernel.org, linux-pci@vger.kernel.org,\n\tMark Rutland <mark.rutland@arm.com>","Subject":"Re: [RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe\n\tWAKE# irq and PCI irq","Message-ID":"<20171102215501.GD28152@atomide.com>","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>\n\t<20171027072612.26565-2-jeffy.chen@rock-chips.com>\n\t<20171027204513.GA105121@google.com>\n\t<20171101210541.vacfufnn2ms65xrw@rob-hp-laptop>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171101210541.vacfufnn2ms65xrw@rob-hp-laptop>","User-Agent":"Mutt/1.9.1 (2017-09-22)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-pci.vger.kernel.org>","X-Mailing-List":"linux-pci@vger.kernel.org"}}]