[{"id":1777851,"web_url":"http://patchwork.ozlabs.org/comment/1777851/","msgid":"<0e8d5867-f689-a4fe-9460-cf3642e90545@gmail.com>","list_archive_url":null,"date":"2017-09-30T02:44:13","subject":"Re: [PATCH v3 4/6] gpu: host1x: Disassemble more instructions","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 28.09.2017 15:50, Mikko Perttunen wrote:\n> The disassembler for debug dumps was missing some newer host1x opcodes.\n> Add disassembly support for these.\n> \n> Signed-off-by: Mikko Perttunen \n> ---\n\nReviewed-by: Dmitry Osipenko \n\nAnd for older Tegra's:\n\nTested-by: Dmitry Osipenko \n\n\n> drivers/gpu/host1x/hw/debug_hw.c | 59 ++++++++++++++++++++++++++++++++---\n> drivers/gpu/host1x/hw/debug_hw_1x01.c | 2 +-\n> drivers/gpu/host1x/hw/debug_hw_1x06.c | 3 +-\n> 3 files changed, 58 insertions(+), 6 deletions(-)\n> \n> diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c\n> index 1e67667e308c..989476801f9d 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw.c\n> @@ -30,6 +30,13 @@ enum {\n> \tHOST1X_OPCODE_IMM\t= 0x04,\n> \tHOST1X_OPCODE_RESTART\t= 0x05,\n> \tHOST1X_OPCODE_GATHER\t= 0x06,\n> +\tHOST1X_OPCODE_SETSTRMID = 0x07,\n> +\tHOST1X_OPCODE_SETAPPID = 0x08,\n> +\tHOST1X_OPCODE_SETPYLD = 0x09,\n> +\tHOST1X_OPCODE_INCR_W = 0x0a,\n> +\tHOST1X_OPCODE_NONINCR_W = 0x0b,\n> +\tHOST1X_OPCODE_GATHER_W = 0x0c,\n> +\tHOST1X_OPCODE_RESTART_W = 0x0d,\n> \tHOST1X_OPCODE_EXTEND\t= 0x0e,\n> };\n> \n> @@ -38,11 +45,16 @@ enum {\n> \tHOST1X_OPCODE_EXTEND_RELEASE_MLOCK\t= 0x01,\n> };\n> \n> -static unsigned int show_channel_command(struct output *o, u32 val)\n> +#define INVALID_PAYLOAD\t\t\t\t0xffffffff\n> +\n> +static unsigned int show_channel_command(struct output *o, u32 val,\n> +\t\t\t\t\t u32 *payload)\n> {\n> -\tunsigned int mask, subop, num;\n> +\tunsigned int mask, subop, num, opcode;\n> +\n> +\topcode = val >> 28;\n> \n> -\tswitch (val >> 28) {\n> +\tswitch (opcode) {\n> \tcase HOST1X_OPCODE_SETCLASS:\n> \t\tmask = val & 0x3f;\n> \t\tif (mask) {\n> @@ -97,6 +109,44 @@ static unsigned int show_channel_command(struct output *o, u32 val)\n> \t\t\t\t val >> 14 & 0x1, val & 0x3fff);\n> \t\treturn 1;\n> \n> +#if HOST1X_HW >= 6\n> +\tcase HOST1X_OPCODE_SETSTRMID:\n> +\t\thost1x_debug_cont(o, \"SETSTRMID(offset=%06x)\\n\",\n> +\t\t\t\t val & 0x3fffff);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_SETAPPID:\n> +\t\thost1x_debug_cont(o, \"SETAPPID(appid=%02x)\\n\", val & 0xff);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_SETPYLD:\n> +\t\t*payload = val & 0xffff;\n> +\t\thost1x_debug_cont(o, \"SETPYLD(data=%04x)\\n\", *payload);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_INCR_W:\n> +\tcase HOST1X_OPCODE_NONINCR_W:\n> +\t\thost1x_debug_cont(o, \"%s(offset=%06x, \",\n> +\t\t\t\t opcode == HOST1X_OPCODE_INCR_W ?\n> +\t\t\t\t\t\"INCR_W\" : \"NONINCR_W\",\n> +\t\t\t\t val & 0x3fffff);\n> +\t\tif (*payload == 0) {\n> +\t\t\thost1x_debug_cont(o, \"[])\\n\");\n> +\t\t\treturn 0;\n> +\t\t} else if (*payload == INVALID_PAYLOAD) {\n> +\t\t\thost1x_debug_cont(o, \"unknown)\\n\");\n> +\t\t\treturn 0;\n> +\t\t} else {\n> +\t\t\thost1x_debug_cont(o, \"[\");\n> +\t\t\treturn *payload;\n> +\t\t}\n> +\n> +\tcase HOST1X_OPCODE_GATHER_W:\n> +\t\thost1x_debug_cont(o, \"GATHER_W(count=%04x, addr=[\",\n> +\t\t\t\t val & 0x3fff);\n> +\t\treturn 2;\n> +#endif\n> +\n> \tcase HOST1X_OPCODE_EXTEND:\n> \t\tsubop = val >> 24 & 0xf;\n> \t\tif (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)\n> @@ -122,6 +172,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n> \t/* Map dmaget cursor to corresponding mem handle */\n> \tu32 offset = phys_addr - pin_addr;\n> \tunsigned int data_count = 0, i;\n> +\tu32 payload = INVALID_PAYLOAD;\n> \n> \t/*\n> \t * Sometimes we're given different hardware address to the same\n> @@ -139,7 +190,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n> \n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%08x: %08x: \", addr, val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, &payload);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n> diff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> index 09e1aa7bb5dd..8790d5fd5f20 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> @@ -112,7 +112,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%08x: \", val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, NULL);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n> diff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> index bd89da5dc64c..b503c740c022 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> @@ -63,6 +63,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \t\t\t\t\t struct output *o)\n> {\n> \tu32 val, rd_ptr, wr_ptr, start, end;\n> +\tu32 payload = INVALID_PAYLOAD;\n> \tunsigned int data_count = 0;\n> \n> \thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n> @@ -107,7 +108,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%03x 0x%08x: \",\n> \t\t\t\t\t rd_ptr - start, val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, &payload);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? 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