[{"id":1779444,"web_url":"http://patchwork.ozlabs.org/comment/1779444/","msgid":"<1507094931.5452.20.camel@aj.id.au>","list_archive_url":null,"date":"2017-10-04T05:28:51","subject":"Re: [PATCH 8/8] ARM: dts: aspeed: Clean up UART nodes","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote:\n>  - Shorten size of reg property so it covers only the implemented\n>  registers\n> \n>  - Add VUART compatible\n> \n>  - Move stray uart1 in g5 definition\n> \n>  - Remove outdated current-speed property. Different bootloaders use\n>  different speeds, so this is no longer helpful\n> \n> Signed-off-by: Joel Stanley <joel@jms.id.au>\n> ---\n>  arch/arm/boot/dts/aspeed-g4.dtsi | 17 +++++++++--------\n>  arch/arm/boot/dts/aspeed-g5.dtsi | 36 ++++++++++++++++++------------------\n>  2 files changed, 27 insertions(+), 26 deletions(-)\n> \n> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi\n> index 191c33d18122..7a4a53666d70 100644\n> --- a/arch/arm/boot/dts/aspeed-g4.dtsi\n> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi\n> @@ -27,6 +27,7 @@\n>  \t\tserial2 = &uart3;\n>  \t\tserial3 = &uart4;\n>  \t\tserial4 = &uart5;\n> +\t\tserial5 = &vuart;\n>  \t};\n>  \n>  \tcpus {\n> @@ -199,7 +200,7 @@\n>  \n>  \t\t\tuart1: serial@1e783000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e783000 0x1000>;\n> +\t\t\t\treg = <0x1e783000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <9>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -209,7 +210,7 @@\n>  \n>  \t\t\tuart2: serial@1e78d000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78d000 0x1000>;\n> +\t\t\t\treg = <0x1e78d000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <32>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -219,7 +220,7 @@\n>  \n>  \t\t\tuart3: serial@1e78e000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78e000 0x1000>;\n> +\t\t\t\treg = <0x1e78e000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <33>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -229,7 +230,7 @@\n>  \n>  \t\t\tuart4: serial@1e78f000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78f000 0x1000>;\n> +\t\t\t\treg = <0x1e78f000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <34>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -239,7 +240,7 @@\n>  \n>  \t\t\tuart5: serial@1e784000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e784000 0x1000>;\n> +\t\t\t\treg = <0x1e784000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <10>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -248,9 +249,9 @@\n>  \t\t\t\tstatus = \"disabled\";\n>  \t\t\t};\n>  \n> -\t\t\tuart6: serial@1e787000 {\n> -\t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e787000 0x1000>;\n> +\t\t\tvuart: vuart@1e787000 {\n\nBit of a nit, but arguably this should be `vuart: serial@...`?\n\n> +\t\t\t\tcompatible = \"aspeed,ast2400-vuart\";\n> +\t\t\t\treg = <0x1e787000 0x40>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <10>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi\n> index 251fc9f4637e..0b793305120a 100644\n> --- a/arch/arm/boot/dts/aspeed-g5.dtsi\n> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n> @@ -27,6 +27,7 @@\n>  \t\tserial2 = &uart3;\n>  \t\tserial3 = &uart4;\n>  \t\tserial4 = &uart5;\n> +\t\tserial5 = &vuart;\n>  \t};\n>  \n>  \tcpus {\n> @@ -247,16 +248,6 @@\n>  \t\t\t\tstatus = \"disabled\";\n>  \t\t\t};\n>  \n> -\t\t\tuart1: serial@1e783000 {\n> -\t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e783000 0x1000>;\n> -\t\t\t\treg-shift = <2>;\n> -\t\t\t\tinterrupts = <9>;\n> -\t\t\t\tclocks = <&clk_uart>;\n> -\t\t\t\tno-loopback-test;\n> -\t\t\t\tstatus = \"disabled\";\n> -\t\t\t};\n> -\n>  \t\t\tlpc: lpc@1e789000 {\n>  \t\t\t\tcompatible = \"aspeed,ast2500-lpc\", \"simple-mfd\";\n>  \t\t\t\treg = <0x1e789000 0x1000>;\n> @@ -287,9 +278,19 @@\n>  \t\t\t\t};\n>  \t\t\t};\n>  \n> +\t\t\tuart1: serial@1e783000 {\n\nEarlier in the series you had a patch moving the ADC node to be in\naddress-order with respect to the rest of the nodes but this change puts uart1\nout of address-order. As it turns out the uarts blocks are sprayed around in\nthe address-space: uart1 and uart5 are together, the vuart is elsewhere, then\nuarts 2-4 are lumped together in another spot. I think it makes sense to\nconsolidate them, but it is inconsistent. Thoughts?\n\n> +\t\t\t\tcompatible = \"ns16550a\";\n> +\t\t\t\treg = <0x1e783000 0x20>;\n> +\t\t\t\treg-shift = <2>;\n> +\t\t\t\tinterrupts = <9>;\n> +\t\t\t\tclocks = <&clk_uart>;\n> +\t\t\t\tno-loopback-test;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t};\n> +\n>  \t\t\tuart2: serial@1e78d000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78d000 0x1000>;\n> +\t\t\t\treg = <0x1e78d000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <32>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -299,7 +300,7 @@\n>  \n>  \t\t\tuart3: serial@1e78e000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78e000 0x1000>;\n> +\t\t\t\treg = <0x1e78e000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <33>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -309,7 +310,7 @@\n>  \n>  \t\t\tuart4: serial@1e78f000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e78f000 0x1000>;\n> +\t\t\t\treg = <0x1e78f000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <34>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> @@ -319,18 +320,17 @@\n>  \n>  \t\t\tuart5: serial@1e784000 {\n>  \t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e784000 0x1000>;\n> +\t\t\t\treg = <0x1e784000 0x20>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <10>;\n>  \t\t\t\tclocks = <&clk_uart>;\n> -\t\t\t\tcurrent-speed = <38400>;\n>  \t\t\t\tno-loopback-test;\n>  \t\t\t\tstatus = \"disabled\";\n>  \t\t\t};\n>  \n> -\t\t\tuart6: serial@1e787000 {\n> -\t\t\t\tcompatible = \"ns16550a\";\n> -\t\t\t\treg = <0x1e787000 0x1000>;\n> +\t\t\tvuart: vuart@1e787000 {\n\nSee serial@ comment above.\n\nCheers,\n\nAndrew\n\n> +\t\t\t\tcompatible = \"aspeed,ast2500-vuart\";\n> +\t\t\t\treg = <0x1e787000 0x40>;\n>  \t\t\t\treg-shift = <2>;\n>  \t\t\t\tinterrupts = <10>;\n>  \t\t\t\tclocks = <&clk_uart>;","headers":{"Return-Path":"<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6Pb4690jz9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed,  4 Oct 2017 16:29:04 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3y6Pb44wqYzDqlM\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed,  4 Oct 2017 16:29:04 +1100 (AEDT)","from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com\n\t[66.111.4.25])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3y6Pb14clRzDqlM\n\tfor <linux-aspeed@lists.ozlabs.org>;\n\tWed,  4 Oct 2017 16:29:01 +1100 (AEDT)","from compute4.internal (compute4.nyi.internal [10.202.2.44])\n\tby mailout.nyi.internal (Postfix) with ESMTP id 943D2210D7;\n\tWed,  4 Oct 2017 01:28:59 -0400 (EDT)","from frontend2 ([10.202.2.161])\n\tby compute4.internal (MEProxy); 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micalg=\"pgp-sha512\";\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"=-kijKAuAMDPqSYXCkz2l6\"","X-Mailer":"Evolution 3.22.6-1ubuntu1 ","Mime-Version":"1.0","X-BeenThere":"linux-aspeed@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>","List-Unsubscribe":"<https://lists.ozlabs.org/options/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>","List-Archive":"<http://lists.ozlabs.org/pipermail/linux-aspeed/>","List-Post":"<mailto:linux-aspeed@lists.ozlabs.org>","List-Help":"<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>","List-Subscribe":"<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org,\n\tBrendan Higgins <brendanhiggins@google.com>,\n\tRussell King <linux@armlinux.org.uk>, linux-kernel@vger.kernel.org,\n\tRick Altherr <raltherr@google.com>, linux-arm-kernel@lists.infradead.org","Errors-To":"linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Linux-aspeed\"\n\t<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>"}},{"id":1779453,"web_url":"http://patchwork.ozlabs.org/comment/1779453/","msgid":"<CACPK8Xe6eftZvZzuXChUr3+Nd+Hj5nDB723d-9QwrMszxto6-A@mail.gmail.com>","list_archive_url":null,"date":"2017-10-04T06:00:10","subject":"Re: [PATCH 8/8] ARM: dts: aspeed: Clean up UART nodes","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Wed, Oct 4, 2017 at 2:58 PM, Andrew Jeffery <andrew@aj.id.au> wrote:\n> On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote:\n\n>> -                     uart6: serial@1e787000 {\n>> -                             compatible = \"ns16550a\";\n>> -                             reg = <0x1e787000 0x1000>;\n>> +                     vuart: vuart@1e787000 {\n>\n> Bit of a nit, but arguably this should be `vuart: serial@...`?\n\nYep, that makes sense.\n\n>\n>> +                             compatible = \"aspeed,ast2400-vuart\";\n>> +                             reg = <0x1e787000 0x40>;\n>>                               reg-shift = <2>;\n>>                               interrupts = <10>;\n>>                               clocks = <&clk_uart>;\n>> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi\n>> index 251fc9f4637e..0b793305120a 100644\n>> --- a/arch/arm/boot/dts/aspeed-g5.dtsi\n>> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n\n>> @@ -287,9 +278,19 @@\n>>                               };\n>>                       };\n>>\n>> +                     uart1: serial@1e783000 {\n>\n> Earlier in the series you had a patch moving the ADC node to be in\n> address-order with respect to the rest of the nodes but this change puts uart1\n> out of address-order. As it turns out the uarts blocks are sprayed around in\n> the address-space: uart1 and uart5 are together, the vuart is elsewhere, then\n> uarts 2-4 are lumped together in another spot. I think it makes sense to\n> consolidate them, but it is inconsistent. Thoughts?\n\nYeah. I'll move them to where they should be.\n\nCheers,\n\nJoel","headers":{"Return-Path":"<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6QHW4bh2z9t2M\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed,  4 Oct 2017 17:00:39 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3y6QHW3BPYzDqks\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed,  4 Oct 2017 17:00:39 +1100 (AEDT)","from mail-lf0-x243.google.com (mail-lf0-x243.google.com\n\t[IPv6:2a00:1450:4010:c07::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3y6QHQ6GspzDqks\n\tfor <linux-aspeed@lists.ozlabs.org>;\n\tWed,  4 Oct 2017 17:00:34 +1100 (AEDT)","by mail-lf0-x243.google.com with SMTP id l196so4391299lfl.3\n\tfor <linux-aspeed@lists.ozlabs.org>;\n\tTue, 03 Oct 2017 23:00:34 -0700 (PDT)","by 10.25.195.6 with HTTP; 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charset=\"UTF-8\"","X-BeenThere":"linux-aspeed@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>","List-Unsubscribe":"<https://lists.ozlabs.org/options/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>","List-Archive":"<http://lists.ozlabs.org/pipermail/linux-aspeed/>","List-Post":"<mailto:linux-aspeed@lists.ozlabs.org>","List-Help":"<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>","List-Subscribe":"<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>","Cc":"Mark Rutland <mark.rutland@arm.com>,\n\tdevicetree <devicetree@vger.kernel.org>, linux-aspeed@lists.ozlabs.org,\n\tBrendan Higgins <brendanhiggins@google.com>,\n\tRussell King <linux@armlinux.org.uk>,\n\tLinux Kernel Mailing List <linux-kernel@vger.kernel.org>,\n\tRob Herring <robh+dt@kernel.org>, Rick Altherr <raltherr@google.com>, \n\tLinux ARM <linux-arm-kernel@lists.infradead.org>","Errors-To":"linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Linux-aspeed\"\n\t<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>"}}]