[{"id":1779431,"web_url":"http://patchwork.ozlabs.org/comment/1779431/","msgid":"<1507093999.5452.16.camel@aj.id.au>","list_archive_url":null,"date":"2017-10-04T05:13:19","subject":"Re: [PATCH 7/8] ARM: dts: aspeed: Add aliases for UARTs","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote:\n> Existing userspace expects the console (UART5) to be at /dev/ttyS4.  To\n> ensure the UARTs show up where users expect them, we give them fixed\n> aliases starting at 0.\n> \n> Signed-off-by: Joel Stanley \n\nReviewed-by: Andrew Jeffery \n\n> ---\n>  arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 4 ----\n>  arch/arm/boot/dts/aspeed-g4.dtsi              | 5 +++++\n>  arch/arm/boot/dts/aspeed-g5.dtsi              | 5 +++++\n>  3 files changed, 10 insertions(+), 4 deletions(-)\n> \n> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\n> index e387c80b7f4f..be51be5a5f39 100644\n> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\n> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\n> @@ -6,10 +6,6 @@\n>  \tmodel = \"Palmetto BMC\";\n>  \tcompatible = \"tyan,palmetto-bmc\", \"aspeed,ast2400\";\n>  \n> -\taliases {\n> -\t\tserial4 = &uart5;\n> -\t};\n> -\n>  \tchosen {\n>  \t\tstdout-path = &uart5;\n>  \t\tbootargs = \"console=ttyS4,115200 earlyprintk\";\n> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi\n> index f8611d5a6465..191c33d18122 100644\n> --- a/arch/arm/boot/dts/aspeed-g4.dtsi\n> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi\n> @@ -22,6 +22,11 @@\n>  \t\ti2c11 = &i2c11;\n>  \t\ti2c12 = &i2c12;\n>  \t\ti2c13 = &i2c13;\n> +\t\tserial0 = &uart1;\n> +\t\tserial1 = &uart2;\n> +\t\tserial2 = &uart3;\n> +\t\tserial3 = &uart4;\n> +\t\tserial4 = &uart5;\n>  \t};\n>  \n>  \tcpus {\n> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi\n> index de127370131d..251fc9f4637e 100644\n> --- a/arch/arm/boot/dts/aspeed-g5.dtsi\n> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n> @@ -22,6 +22,11 @@\n>  \t\ti2c11 = &i2c11;\n>  \t\ti2c12 = &i2c12;\n>  \t\ti2c13 = &i2c13;\n> +\t\tserial0 = &uart1;\n> +\t\tserial1 = &uart2;\n> +\t\tserial2 = &uart3;\n> +\t\tserial3 = &uart4;\n> +\t\tserial4 = &uart5;\n>  \t};\n>  \n>  \tcpus {","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6PF84dChz9sRV\n\tfor ;\n\tWed, 4 Oct 2017 16:13:32 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3y6PF82Xk8zDqlM\n\tfor ;\n\tWed, 4 Oct 2017 16:13:32 +1100 (AEDT)","from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com\n\t[66.111.4.25])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3y6PF60MCFzDqlM\n\tfor ;\n\tWed, 4 Oct 2017 16:13:30 +1100 (AEDT)","from compute4.internal (compute4.nyi.internal [10.202.2.44])\n\tby mailout.nyi.internal (Postfix) with ESMTP id 0211F20D60;\n\tWed, 4 Oct 2017 01:13:28 -0400 (EDT)","from frontend2 ([10.202.2.161])\n\tby compute4.internal (MEProxy); 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