[{"id":1777148,"web_url":"http://patchwork.ozlabs.org/comment/1777148/","msgid":"<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>","list_archive_url":null,"date":"2017-09-28T16:17:51","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 27/09/2017 13:09, Patrick McGehearty wrote:\n> Tested in sparcv9-*-* and sparc64-*-* targets in both multi and\n> non-multi arch configurations.\n>\n> Support added to identify Sparc M7/T7/S7/M8/T8 processor capability.\n> Usual \"make check\" correctness tests run with no regressions.\n> Performance tests run on Sparc S7 using new code and old niagara4 code.\n>\n> Optimizations for memcpy also apply to mempcpy and memmove\n> where they share code. Optimizations for memset also apply\n> to bzero as they share code.\n>\n> For memcpy/mempcpy/memmove, performance comparison with niagara4 code:\n> Long word aligned data\n> 0-127 bytes - minimal changes\n> 128-1023 bytes - 7-30% gain\n> 1024+ bytes - 1-7% gain (in cache); 30-100% gain (out of cache)\n> Word aligned data\n> 0-127 bytes - 50%+ gain\n> 128-1023 bytes - 10-200% gain\n> 1024+ bytes - 0-15% gain (in cache); 5-50% gain (out of cache)\n> Unaligned data\n> 0-127 bytes - 0-70%+ gain\n> 128-447 bytes - 40-80%+ gain\n> 448-511 bytes - 1-3% loss\n> 512-4096 bytes - 2-3% gain (in cache); 0-20% gain (out of cache)\n> 4096+ bytes - +/- 3% (in cache); 20-50% gain (out of cache)\n>\n> For memset/bzero, performance comparison with niagara4 code:\n> For memset nonzero data,\n> 256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache)\n> 1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache)\n> For memset zero data (and bzero),\n> 256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache)\n> 1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache)\n> ---\n> ChangeLog | 20 +\n> sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile | 3 +-\n> .../sparcv9/multiarch/memcpy-memmove-niagara7.S | 2 +\n> sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S | 2 +\n> .../sparc32/sparcv9/multiarch/memset-niagara7.S | 2 +\n> .../sparc/sparc32/sparcv9/multiarch/rtld-memmove.c | 1 +\n> sysdeps/sparc/sparc64/multiarch/Makefile | 3 +-\n> sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c | 13 +\n> .../sparc64/multiarch/memcpy-memmove-niagara7.S | 979 ++++++++++++++++++++\n> sysdeps/sparc/sparc64/multiarch/memcpy.S | 28 +-\n> sysdeps/sparc/sparc64/multiarch/memmove.S | 72 ++\n> sysdeps/sparc/sparc64/multiarch/memset-niagara7.S | 334 +++++++\n> sysdeps/sparc/sparc64/multiarch/memset.S | 28 +-\n> sysdeps/sparc/sparc64/multiarch/rtld-memmove.c | 1 +\n> 14 files changed, 1482 insertions(+), 6 deletions(-)\n> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-memmove-niagara7.S\n> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S\n> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S\n> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memmove.c\n> create mode 100644 sysdeps/sparc/sparc64/multiarch/memcpy-memmove-niagara7.S\n> create mode 100644 sysdeps/sparc/sparc64/multiarch/memmove.S\n> create mode 100644 sysdeps/sparc/sparc64/multiarch/memset-niagara7.S\n> create mode 100644 sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n\nI would prefer if you split this patch in a memcpy/mempcpy/memmove and\na memset/bzero one since they are separated implementations.\n\nI also noticed this whitespace issues, so you might want to check this out:\n\n---\n\npatch03:886: trailing whitespace.\n * lines from memory. Use ST_CHUNK stores to first element of each cache \npatch03:890: space before tab in indent.\n andn %o2, 0x3f, %o5 /* %o5 is multiple of block size */\npatch03:891: space before tab in indent.\n and %o2, 0x3f, %o2 /* residue bytes in %o2 */\npatch03:892: trailing whitespace.\n \npatch03:1216: new blank line at EOF.\n+\nwarning: 5 lines add whitespace errors.\n---\n\n> diff --git a/sysdeps/sparc/sparc64/multiarch/memcpy.S b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n> index b6396ee..d72f4b1 100644\n> --- a/sysdeps/sparc/sparc64/multiarch/memcpy.S\n> +++ b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n> @@ -27,7 +27,19 @@ ENTRY(memcpy)\n> # ifdef SHARED\n> \tSETUP_PIC_REG_LEAF(o3, o5)\n> # endif\n> -\tset\tHWCAP_SPARC_CRYPTO, %o1\n> +\tset\tHWCAP_SPARC_ADP, %o1\n> +\tandcc\t%o0, %o1, %g0\n> +\tbe\t1f\n> +\t nop\n> +# ifdef SHARED\n> +\tsethi\t%gdop_hix22(__memcpy_niagara7), %o1\n> +\txor\t%o1, %gdop_lox10(__memcpy_niagara7), %o1\n> +# else\n> +\tset\t__memcpy_niagara7, %o1\n> +# endif\n> +\tba\t10f\n> +\t nop\n> +1: set\tHWCAP_SPARC_CRYPTO, %o1\n> \tandcc\t%o0, %o1, %g0\n> \tbe\t1f\n> \t andcc\t%o0, HWCAP_SPARC_N2, %g0\n> @@ -89,7 +101,19 @@ ENTRY(__mempcpy)\n> # ifdef SHARED\n> \tSETUP_PIC_REG_LEAF(o3, o5)\n> # endif\n> -\tset\tHWCAP_SPARC_CRYPTO, %o1\n> +\tset HWCAP_SPARC_ADP, %o1\n> +\tandcc %o0, %o1, %g0\n> + be 1f\n> +\t nop\n> +# ifdef SHARED\n> +\tsethi\t%gdop_hix22(__mempcpy_niagara7), %o1\n> +\txor\t%o1, %gdop_lox10(__mempcpy_niagara7), %o1\n> +# else\n> +\tset\t__mempcpy_niagara7, %o1\n> +# endif\n> +\tba 10f\n> +\t nop\n> +1:\tset\tHWCAP_SPARC_CRYPTO, %o1\n> \tandcc\t%o0, %o1, %g0\n> \tbe\t1f\n> \t andcc\t%o0, HWCAP_SPARC_N2, %g0\n\nSince you are touching this file, I think it would be better to change the\nifunc selector to a C implementation by using the __ifunc/sparc_libc_ifunc\nmacros.\n\n\n> diff --git a/sysdeps/sparc/sparc64/multiarch/memmove.S b/sysdeps/sparc/sparc64/multiarch/memmove.S\n> new file mode 100644\n> index 0000000..43bdf08\n> --- /dev/null\n> +++ b/sysdeps/sparc/sparc64/multiarch/memmove.S\n> @@ -0,0 +1,72 @@\n> +/* Multiple versions of memmove and bcopy\n> + All versions must be listed in ifunc-impl-list.c.\n> + Copyright (C) 2017 Free Software Foundation, Inc.\n> + This file is part of the GNU C Library.\n> +\n> + The GNU C Library is free software; you can redistribute it and/or\n> + modify it under the terms of the GNU Lesser General Public\n> + License as published by the Free Software Foundation; either\n> + version 2.1 of the License, or (at your option) any later version.\n> +\n> + The GNU C Library is distributed in the hope that it will be useful,\n> + but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n> + Lesser General Public License for more details.\n> +\n> + You should have received a copy of the GNU Lesser General Public\n> + License along with the GNU C Library; if not, write to the Free\n> + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA\n> + 02111-1307 USA. */\n> +\n> +#include \n> +\n> +#if IS_IN (libc)\n> +\t.text\n> +ENTRY(memmove)\n> +\t.type\tmemmove, @gnu_indirect_function\n> +# ifdef SHARED\n> +\tSETUP_PIC_REG_LEAF(o3, o5)\n> +# endif\n> +\tset\tHWCAP_SPARC_ADP, %o1\n> +\tandcc\t%o0, %o1, %g0\n> +\tbe\t1f\n> +\t nop\n> +# ifdef SHARED\n> +\tsethi\t%gdop_hix22(__memmove_niagara7), %o1\n> +\txor\t%o1, %gdop_lox10(__memmove_niagara7), %o1\n> +# else\n> +\tset\t__memmove_niagara7, %o1\n> +# endif\n> +\tba 10f\n> +\t nop\n> +1:\n> +# ifdef SHARED\n> +\tsethi %gdop_hix22(__memmove_ultra1), %o1\n> +\txor %o1, %gdop_lox10(__memmove_ultra1), %o1\n> +# else\n> +\tset __memmove_ultra1, %o1\n> +# endif\n> +10:\n> +# ifdef SHARED\n> +\tadd\t%o3, %o1, %o1\n> +# endif\n> +\tretl\n> +\t mov\t%o1, %o0\n> +END(memmove)\n> +\n> +libc_hidden_builtin_def (memmove)\n> +\n> +#undef libc_hidden_builtin_def\n> +#define libc_hidden_builtin_def(name)\n> +#undef weak_alias\n> +#define weak_alias(x, y)\n> +#undef libc_hidden_def\n> +#define libc_hidden_def(name)\n> +\n> +#define memmove __memmove_ultra1\n> +#define __memmove __memmove_ultra1\n> +\n> +#endif\n> +\n> +#include \"../memmove.S\"\n> +\n\nAs before, I think new ifunc resolvers should be avoid to be coded in assembly.\nAlso there is an extra line on this file.\n\n> diff --git a/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c b/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n> new file mode 100644\n> index 0000000..66fe118\n> --- /dev/null\n> +++ b/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n> @@ -0,0 +1 @@\n> +#include <../rtld-memmove.c>\n\nAvoid using relative patch, include the default memmove using full paths.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable"}},{"id":1777257,"web_url":"http://patchwork.ozlabs.org/comment/1777257/","msgid":"<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>","list_archive_url":null,"date":"2017-09-28T19:43:56","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":72081,"url":"http://patchwork.ozlabs.org/api/people/72081/","name":"Patrick McGehearty","email":"patrick.mcgehearty@oracle.com"},"content":"Responses after the comments. Apologies for the earlier incomplete message.\n\nOn 9/28/2017 11:17 AM, Adhemerval Zanella wrote:\n>\n> On 27/09/2017 13:09, Patrick McGehearty wrote:\n>> Tested in sparcv9-*-* and sparc64-*-* targets in both multi and\n>> non-multi arch configurations.\n>>\n>> Support added to identify Sparc M7/T7/S7/M8/T8 processor capability.\n>> Usual \"make check\" correctness tests run with no regressions.\n>> Performance tests run on Sparc S7 using new code and old niagara4 code.\n>>\n>> Optimizations for memcpy also apply to mempcpy and memmove\n>> where they share code. Optimizations for memset also apply\n>> to bzero as they share code.\n>>\n>> For memcpy/mempcpy/memmove, performance comparison with niagara4 code:\n>> Long word aligned data\n>> 0-127 bytes - minimal changes\n>> 128-1023 bytes - 7-30% gain\n>> 1024+ bytes - 1-7% gain (in cache); 30-100% gain (out of cache)\n>> Word aligned data\n>> 0-127 bytes - 50%+ gain\n>> 128-1023 bytes - 10-200% gain\n>> 1024+ bytes - 0-15% gain (in cache); 5-50% gain (out of cache)\n>> Unaligned data\n>> 0-127 bytes - 0-70%+ gain\n>> 128-447 bytes - 40-80%+ gain\n>> 448-511 bytes - 1-3% loss\n>> 512-4096 bytes - 2-3% gain (in cache); 0-20% gain (out of cache)\n>> 4096+ bytes - +/- 3% (in cache); 20-50% gain (out of cache)\n>>\n>> For memset/bzero, performance comparison with niagara4 code:\n>> For memset nonzero data,\n>> 256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache)\n>> 1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache)\n>> For memset zero data (and bzero),\n>> 256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache)\n>> 1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache)\n>> ---\n>> ChangeLog | 20 +\n>> sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile | 3 +-\n>> .../sparcv9/multiarch/memcpy-memmove-niagara7.S | 2 +\n>> sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S | 2 +\n>> .../sparc32/sparcv9/multiarch/memset-niagara7.S | 2 +\n>> .../sparc/sparc32/sparcv9/multiarch/rtld-memmove.c | 1 +\n>> sysdeps/sparc/sparc64/multiarch/Makefile | 3 +-\n>> sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c | 13 +\n>> .../sparc64/multiarch/memcpy-memmove-niagara7.S | 979 ++++++++++++++++++++\n>> sysdeps/sparc/sparc64/multiarch/memcpy.S | 28 +-\n>> sysdeps/sparc/sparc64/multiarch/memmove.S | 72 ++\n>> sysdeps/sparc/sparc64/multiarch/memset-niagara7.S | 334 +++++++\n>> sysdeps/sparc/sparc64/multiarch/memset.S | 28 +-\n>> sysdeps/sparc/sparc64/multiarch/rtld-memmove.c | 1 +\n>> 14 files changed, 1482 insertions(+), 6 deletions(-)\n>> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-memmove-niagara7.S\n>> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S\n>> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S\n>> create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memmove.c\n>> create mode 100644 sysdeps/sparc/sparc64/multiarch/memcpy-memmove-niagara7.S\n>> create mode 100644 sysdeps/sparc/sparc64/multiarch/memmove.S\n>> create mode 100644 sysdeps/sparc/sparc64/multiarch/memset-niagara7.S\n>> create mode 100644 sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n> I would prefer if you split this patch in a memcpy/mempcpy/memmove and\n> a memset/bzero one since they are separated implementations.\nI can see your point, and if I had started that way, it would not have \nbeen a problem.  At this point,\nit would take some effort to redo the patch structure at this point \ngiven our internal development\nprocess and might significantly delay the completion of this patch due \nto requirements to make\nprogress on other tasks. From a user's point of view, the optimizations \nfor memcpy on M7/T7/S7\nand memset on M7/T7/S7 both are driven by the use of block initializing \nstore as a 64 byte operation\ninstead of a 32 byte operation.  (side note: block initializing store on \nM8/T8 is also 64 bytes, so these\noptimizations are also appropriate for the new M8/T8 systems). Thus, a \nuser should be equally\nwilling to use both or neither of the new memcpy/memset optimizations.\n\n\n>\n> I also noticed this whitespace issues, so you might want to check this out:\n>\n> ---\n>\n> patch03:886: trailing whitespace.\n> * lines from memory. Use ST_CHUNK stores to first element of each cache\n> patch03:890: space before tab in indent.\n> andn %o2, 0x3f, %o5 /* %o5 is multiple of block size */\n> patch03:891: space before tab in indent.\n> and %o2, 0x3f, %o2 /* residue bytes in %o2 */\n> patch03:892: trailing whitespace.\n> \n> patch03:1216: new blank line at EOF.\n> +\n> warning: 5 lines add whitespace errors.\n> ---\nI've cleaned up the whitespace issues. Thank you for catching them.\n\n>\n>> diff --git a/sysdeps/sparc/sparc64/multiarch/memcpy.S b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>> index b6396ee..d72f4b1 100644\n>> --- a/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>> +++ b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>> @@ -27,7 +27,19 @@ ENTRY(memcpy)\n>> # ifdef SHARED\n>> \tSETUP_PIC_REG_LEAF(o3, o5)\n>> # endif\n>> -\tset\tHWCAP_SPARC_CRYPTO, %o1\n>> +\tset\tHWCAP_SPARC_ADP, %o1\n>> +\tandcc\t%o0, %o1, %g0\n>> +\tbe\t1f\n>> +\t nop\n>> +# ifdef SHARED\n>> +\tsethi\t%gdop_hix22(__memcpy_niagara7), %o1\n>> +\txor\t%o1, %gdop_lox10(__memcpy_niagara7), %o1\n>> +# else\n>> +\tset\t__memcpy_niagara7, %o1\n>> +# endif\n>> +\tba\t10f\n>> +\t nop\n>> +1: set\tHWCAP_SPARC_CRYPTO, %o1\n>> \tandcc\t%o0, %o1, %g0\n>> \tbe\t1f\n>> \t andcc\t%o0, HWCAP_SPARC_N2, %g0\n>> @@ -89,7 +101,19 @@ ENTRY(__mempcpy)\n>> # ifdef SHARED\n>> \tSETUP_PIC_REG_LEAF(o3, o5)\n>> # endif\n>> -\tset\tHWCAP_SPARC_CRYPTO, %o1\n>> +\tset HWCAP_SPARC_ADP, %o1\n>> +\tandcc %o0, %o1, %g0\n>> + be 1f\n>> +\t nop\n>> +# ifdef SHARED\n>> +\tsethi\t%gdop_hix22(__mempcpy_niagara7), %o1\n>> +\txor\t%o1, %gdop_lox10(__mempcpy_niagara7), %o1\n>> +# else\n>> +\tset\t__mempcpy_niagara7, %o1\n>> +# endif\n>> +\tba 10f\n>> +\t nop\n>> +1:\tset\tHWCAP_SPARC_CRYPTO, %o1\n>> \tandcc\t%o0, %o1, %g0\n>> \tbe\t1f\n>> \t andcc\t%o0, HWCAP_SPARC_N2, %g0\n> Since you are touching this file, I think it would be better to change the\n> ifunc selector to a C implementation by using the __ifunc/sparc_libc_ifunc\n> macros.\nAgain, I agree philosophically, but the actual code changes for ADP were \nmade many months ago.\nRevising those changes now would require more work with little perceived \nbenefit.\n\n>\n>\n>> diff --git a/sysdeps/sparc/sparc64/multiarch/memmove.S b/sysdeps/sparc/sparc64/multiarch/memmove.S\n>> new file mode 100644\n>> index 0000000..43bdf08\n>> --- /dev/null\n>> +++ b/sysdeps/sparc/sparc64/multiarch/memmove.S\n>> @@ -0,0 +1,72 @@\n>> +/* Multiple versions of memmove and bcopy\n>> + All versions must be listed in ifunc-impl-list.c.\n>> + Copyright (C) 2017 Free Software Foundation, Inc.\n>> + This file is part of the GNU C Library.\n>> +\n>> + The GNU C Library is free software; you can redistribute it and/or\n>> + modify it under the terms of the GNU Lesser General Public\n>> + License as published by the Free Software Foundation; either\n>> + version 2.1 of the License, or (at your option) any later version.\n>> +\n>> + The GNU C Library is distributed in the hope that it will be useful,\n>> + but WITHOUT ANY WARRANTY; without even the implied warranty of\n>> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n>> + Lesser General Public License for more details.\n>> +\n>> + You should have received a copy of the GNU Lesser General Public\n>> + License along with the GNU C Library; if not, write to the Free\n>> + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA\n>> + 02111-1307 USA. */\n>> +\n>> +#include \n>> +\n>> +#if IS_IN (libc)\n>> +\t.text\n>> +ENTRY(memmove)\n>> +\t.type\tmemmove, @gnu_indirect_function\n>> +# ifdef SHARED\n>> +\tSETUP_PIC_REG_LEAF(o3, o5)\n>> +# endif\n>> +\tset\tHWCAP_SPARC_ADP, %o1\n>> +\tandcc\t%o0, %o1, %g0\n>> +\tbe\t1f\n>> +\t nop\n>> +# ifdef SHARED\n>> +\tsethi\t%gdop_hix22(__memmove_niagara7), %o1\n>> +\txor\t%o1, %gdop_lox10(__memmove_niagara7), %o1\n>> +# else\n>> +\tset\t__memmove_niagara7, %o1\n>> +# endif\n>> +\tba 10f\n>> +\t nop\n>> +1:\n>> +# ifdef SHARED\n>> +\tsethi %gdop_hix22(__memmove_ultra1), %o1\n>> +\txor %o1, %gdop_lox10(__memmove_ultra1), %o1\n>> +# else\n>> +\tset __memmove_ultra1, %o1\n>> +# endif\n>> +10:\n>> +# ifdef SHARED\n>> +\tadd\t%o3, %o1, %o1\n>> +# endif\n>> +\tretl\n>> +\t mov\t%o1, %o0\n>> +END(memmove)\n>> +\n>> +libc_hidden_builtin_def (memmove)\n>> +\n>> +#undef libc_hidden_builtin_def\n>> +#define libc_hidden_builtin_def(name)\n>> +#undef weak_alias\n>> +#define weak_alias(x, y)\n>> +#undef libc_hidden_def\n>> +#define libc_hidden_def(name)\n>> +\n>> +#define memmove __memmove_ultra1\n>> +#define __memmove __memmove_ultra1\n>> +\n>> +#endif\n>> +\n>> +#include \"../memmove.S\"\n>> +\n> As before, I think new ifunc resolvers should be avoid to be coded in assembly.\n> Also there is an extra line on this file.\nThe extra line has been removed.\n>\n>> diff --git a/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c b/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n>> new file mode 100644\n>> index 0000000..66fe118\n>> --- /dev/null\n>> +++ b/sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n>> @@ -0,0 +1 @@\n>> +#include <../rtld-memmove.c>\n> Avoid using relative patch, include the default memmove using full paths.\n>\n>\nI'll fix the relative paths.\n- patrick","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85093-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"PsJkTgbq\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y34rf4kDfz9t5x\n\tfor ;\n\tFri, 29 Sep 2017 05:44:18 +1000 (AEST)","(qmail 91596 invoked by alias); 28 Sep 2017 19:44:05 -0000","(qmail 88650 invoked by uid 89); 28 Sep 2017 19:44:04 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; q=dns; s=default; b=KACE9++s0BypBtA5\n\tHtN4ZHIY6hR0HKjVqZPF64ENM/sP1WeBZwT36x5CezfqyDpU+k4xQD+WM/VZemUI\n\tav8syBJ+hHXjyh1E5wNlyYOIAaH6vqbyzZILUKznby1FGXTE1dRdmfrIC3a32bdq\n\tKAXmj5q4Y/6Sgj+Hu5kLpY1engc=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; s=default; bh=p+fWRt1vMYEX3ohPNWyvRI\n\tOJyss=; b=PsJkTgbq1tpIQlgEjVk6qRa5BDwsh5EjwVyMYeQql70gGUVhzkXvZl\n\t2yuWiMrQ2uoszCRnyfDBIqf7jg/ijAywUkqIxwnqmkTit08mFiKJefE8BpyeGj+E\n\tEfyKm5r3khLtBu3OqFQbZEiQYJdN+q8vteHpif4a8YEgGQWalKJt8=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-23.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD,\n\tUNSUBSCRIBE_BODY autolearn=ham version=3.3.2 spammy=perceived","X-HELO":"aserp1040.oracle.com","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","To":"libc-alpha@sourceware.org","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>","From":"Patrick McGehearty ","Message-ID":"<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>","Date":"Thu, 28 Sep 2017 14:43:56 -0500","User-Agent":"Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"8bit"}},{"id":1779201,"web_url":"http://patchwork.ozlabs.org/comment/1779201/","msgid":"","list_archive_url":null,"date":"2017-10-03T18:41:08","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 28/09/2017 16:43, Patrick McGehearty wrote:\n> Responses after the comments. Apologies for the earlier incomplete message.\n> \n> On 9/28/2017 11:17 AM, Adhemerval Zanella wrote:\n>>\n>> On 27/09/2017 13:09, Patrick McGehearty wrote:\n>>> Tested in sparcv9-*-* and sparc64-*-* targets in both multi and\n>>> non-multi arch configurations.\n>>>\n>>> Support added to identify Sparc M7/T7/S7/M8/T8 processor capability.\n>>> Usual \"make check\" correctness tests run with no regressions.\n>>> Performance tests run on Sparc S7 using new code and old niagara4 code.\n>>>\n>>> Optimizations for memcpy also apply to mempcpy and memmove\n>>> where they share code. Optimizations for memset also apply\n>>> to bzero as they share code.\n>>>\n>>> For memcpy/mempcpy/memmove, performance comparison with niagara4 code:\n>>> Long word aligned data\n>>>    0-127 bytes - minimal changes\n>>>    128-1023 bytes - 7-30% gain\n>>>    1024+ bytes - 1-7% gain (in cache); 30-100% gain (out of cache)\n>>> Word aligned data\n>>>    0-127 bytes - 50%+ gain\n>>>    128-1023 bytes - 10-200% gain\n>>>    1024+ bytes - 0-15% gain (in cache); 5-50% gain (out of cache)\n>>> Unaligned data\n>>>    0-127 bytes - 0-70%+ gain\n>>>    128-447 bytes - 40-80%+ gain\n>>>    448-511 bytes - 1-3% loss\n>>>    512-4096 bytes - 2-3% gain (in cache); 0-20% gain (out of cache)\n>>>    4096+ bytes - +/- 3% (in cache); 20-50% gain (out of cache)\n>>>\n>>> For memset/bzero, performance comparison with niagara4 code:\n>>> For memset nonzero data,\n>>>    256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache)\n>>>    1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache)\n>>> For memset zero data (and bzero),\n>>>    256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache)\n>>>    1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache)\n\nWhich benchmark did you use to get theses values? If it where obtained\nwith benchtests one please attach the resulting files. If not, please\neither indicate how to reproduce the data or work to improve benchtests\nwith required datapoints.\n\n>>> ---\n>>>   ChangeLog                                          |   20 +\n>>>   sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile   |    3 +-\n>>>   .../sparcv9/multiarch/memcpy-memmove-niagara7.S    |    2 +\n>>>   sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S  |    2 +\n>>>   .../sparc32/sparcv9/multiarch/memset-niagara7.S    |    2 +\n>>>   .../sparc/sparc32/sparcv9/multiarch/rtld-memmove.c |    1 +\n>>>   sysdeps/sparc/sparc64/multiarch/Makefile           |    3 +-\n>>>   sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c  |   13 +\n>>>   .../sparc64/multiarch/memcpy-memmove-niagara7.S    |  979 ++++++++++++++++++++\n>>>   sysdeps/sparc/sparc64/multiarch/memcpy.S           |   28 +-\n>>>   sysdeps/sparc/sparc64/multiarch/memmove.S          |   72 ++\n>>>   sysdeps/sparc/sparc64/multiarch/memset-niagara7.S  |  334 +++++++\n>>>   sysdeps/sparc/sparc64/multiarch/memset.S           |   28 +-\n>>>   sysdeps/sparc/sparc64/multiarch/rtld-memmove.c     |    1 +\n>>>   14 files changed, 1482 insertions(+), 6 deletions(-)\n>>>   create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-memmove-niagara7.S\n>>>   create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memmove.S\n>>>   create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S\n>>>   create mode 100644 sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memmove.c\n>>>   create mode 100644 sysdeps/sparc/sparc64/multiarch/memcpy-memmove-niagara7.S\n>>>   create mode 100644 sysdeps/sparc/sparc64/multiarch/memmove.S\n>>>   create mode 100644 sysdeps/sparc/sparc64/multiarch/memset-niagara7.S\n>>>   create mode 100644 sysdeps/sparc/sparc64/multiarch/rtld-memmove.c\n>> I would prefer if you split this patch in a memcpy/mempcpy/memmove and\n>> a memset/bzero one since they are separated implementations.\n> I can see your point, and if I had started that way, it would not have been a problem.  At this point,\n> it would take some effort to redo the patch structure at this point given our internal development\n> process and might significantly delay the completion of this patch due to requirements to make\n> progress on other tasks. From a user's point of view, the optimizations for memcpy on M7/T7/S7\n> and memset on M7/T7/S7 both are driven by the use of block initializing store as a 64 byte operation\n> instead of a 32 byte operation.  (side note: block initializing store on M8/T8 is also 64 bytes, so these\n> optimizations are also appropriate for the new M8/T8 systems). Thus, a user should be equally\n> willing to use both or neither of the new memcpy/memset optimizations.\n\nThis is not really a good reason to *not* structure better the \npachset, and the change does not relly require extensive changes\n(rather to move the memset bits not another patch). Please split\nthe patch in future submission.\n\n> \n> \n>>\n>> I also noticed this whitespace issues, so you might want to check this out:\n>>\n>> ---\n>>\n>> patch03:886: trailing whitespace.\n>>   *      lines from memory. Use ST_CHUNK stores to first element of each cache\n>> patch03:890: space before tab in indent.\n>>          andn    %o2, 0x3f, %o5          /* %o5 is multiple of block size  */\n>> patch03:891: space before tab in indent.\n>>          and     %o2, 0x3f, %o2          /* residue bytes in %o2  */\n>> patch03:892: trailing whitespace.\n>>   patch03:1216: new blank line at EOF.\n>> +\n>> warning: 5 lines add whitespace errors.\n>> ---\n> I've cleaned up the whitespace issues. Thank you for catching them.\n> \n>>\n>>> diff --git a/sysdeps/sparc/sparc64/multiarch/memcpy.S b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>>> index b6396ee..d72f4b1 100644\n>>> --- a/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>>> +++ b/sysdeps/sparc/sparc64/multiarch/memcpy.S\n>>> @@ -27,7 +27,19 @@ ENTRY(memcpy)\n>>>   # ifdef SHARED\n>>>       SETUP_PIC_REG_LEAF(o3, o5)\n>>>   # endif\n>>> -    set    HWCAP_SPARC_CRYPTO, %o1\n>>> +    set    HWCAP_SPARC_ADP, %o1\n>>> +    andcc    %o0, %o1, %g0\n>>> +    be    1f\n>>> +     nop\n>>> +# ifdef SHARED\n>>> +    sethi    %gdop_hix22(__memcpy_niagara7), %o1\n>>> +    xor    %o1, %gdop_lox10(__memcpy_niagara7), %o1\n>>> +# else\n>>> +    set    __memcpy_niagara7, %o1\n>>> +# endif\n>>> +    ba    10f\n>>> +     nop\n>>> +1:      set    HWCAP_SPARC_CRYPTO, %o1\n>>>       andcc    %o0, %o1, %g0\n>>>       be    1f\n>>>        andcc    %o0, HWCAP_SPARC_N2, %g0\n>>> @@ -89,7 +101,19 @@ ENTRY(__mempcpy)\n>>>   # ifdef SHARED\n>>>       SETUP_PIC_REG_LEAF(o3, o5)\n>>>   # endif\n>>> -    set    HWCAP_SPARC_CRYPTO, %o1\n>>> +    set     HWCAP_SPARC_ADP, %o1\n>>> +    andcc   %o0, %o1, %g0\n>>> +        be      1f\n>>> +     nop\n>>> +# ifdef SHARED\n>>> +    sethi    %gdop_hix22(__mempcpy_niagara7), %o1\n>>> +    xor    %o1, %gdop_lox10(__mempcpy_niagara7), %o1\n>>> +# else\n>>> +    set    __mempcpy_niagara7, %o1\n>>> +# endif\n>>> +    ba      10f\n>>> +     nop\n>>> +1:    set    HWCAP_SPARC_CRYPTO, %o1\n>>>       andcc    %o0, %o1, %g0\n>>>       be    1f\n>>>        andcc    %o0, HWCAP_SPARC_N2, %g0\n>> Since you are touching this file, I think it would be better to change the\n>> ifunc selector to a C implementation by using the __ifunc/sparc_libc_ifunc\n>> macros.\n> Again, I agree philosophically, but the actual code changes for ADP were made many months ago.\n> Revising those changes now would require more work with little perceived benefit.\n\nSPARC is the only one still using ifunc resolvers coded in assembly and \ncurrently there is no gain in continuing doing so. You can rebase your next\nversion against azanella/sparc64-ifunc [1] which I intend to send upstream\nshortly.\n\nIt refactors sparc64 memcpy and memset ifunc selection current implementation\nto C. I think I get the selector logic correct and I checked on a UltraSparc T5, \nso please tell if I got something wrong.\n\n[1] https://sourceware.org/git/?p=glibc.git;a=shortlog;h=refs/heads/azanella/sparc64-ifunc","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85313-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"vTlectBJ\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y67Cl1BRGz9sRq\n\tfor ;\n\tWed, 4 Oct 2017 05:41:22 +1100 (AEDT)","(qmail 4278 invoked by alias); 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\n\tTue, 03 Oct 2017 11:41:12 -0700 (PDT)","From":"Adhemerval Zanella ","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","To":"libc-alpha@sourceware.org","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>","Message-ID":"","Date":"Tue, 3 Oct 2017 15:41:08 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit"}},{"id":1779253,"web_url":"http://patchwork.ozlabs.org/comment/1779253/","msgid":"","list_archive_url":null,"date":"2017-10-03T20:49:47","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":4349,"url":"http://patchwork.ozlabs.org/api/people/4349/","name":"Joseph Myers","email":"joseph@codesourcery.com"},"content":"On Tue, 3 Oct 2017, Adhemerval Zanella wrote:\n\n> SPARC is the only one still using ifunc resolvers coded in assembly and \n> currently there is no gain in continuing doing so. You can rebase your next\n\nARM resolvers are in assembly, and changing them to C would break the \nbuild with GCC mainline as the ifunc attribute is not enabled by default \nthere for ARM.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85319-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"ULyF94Nu\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6B4M2D4nz9sRm\n\tfor ;\n\tWed, 4 Oct 2017 07:50:11 +1100 (AEDT)","(qmail 126766 invoked by alias); 3 Oct 2017 20:49:57 -0000","(qmail 126755 invoked by uid 89); 3 Oct 2017 20:49:57 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; q=dns; s=default; b=aiVDJ\n\tbAB5L1hDummAVEPXxG6kvvck3rQ/BO3QB8UIuPKA3dyesuI+X9y3CgAw43aJ6r1M\n\tpfazkVjo9YFhjZmBRuPY9GSEvS36cD3fPgCKReUVtQbUEnUcmiBGR5vZxPoCkZiV\n\tZ7HgQAHFP7GTGqCOxzHOEtckEgoyceW0X+xVmQ=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; s=default; bh=Ol/hDFLXxKv\n\tWYbHKabFD23E0Hko=; b=ULyF94Nuw00FaUZeLxj/T6QL7OgRxD4e3fz4qRblNZ1\n\ts6H48pUblMlwOwn/Lw2OmWGL7qK0xzpbQKcsG/jpGotH9MdPSONGxQXJ6Q6SdAH5\n\tPoWQs/8w27yn7hrvQEps3uZ3wJGkPqQ1ysPS02xiErLqmAS4SYW83V3V6e6X8T4E\n\t=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.0 required=5.0 tests=AWL, BAYES_00,\n\tRCVD_IN_DNSWL_NONE, SPF_PASS,\n\tURIBL_RED autolearn=ham version=3.3.2 spammy=","X-HELO":"relay1.mentorg.com","Date":"Tue, 3 Oct 2017 20:49:47 +0000","From":"Joseph Myers ","To":"Adhemerval Zanella ","CC":"","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","In-Reply-To":"","Message-ID":"","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"US-ASCII\"","X-ClientProxiedBy":"svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) To\n\tsvr-ies-mbx-01.mgc.mentorg.com (139.181.222.1)"}},{"id":1780096,"web_url":"http://patchwork.ozlabs.org/comment/1780096/","msgid":"","list_archive_url":null,"date":"2017-10-04T19:53:20","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 03/10/2017 17:49, Joseph Myers wrote:\n> On Tue, 3 Oct 2017, Adhemerval Zanella wrote:\n> \n>> SPARC is the only one still using ifunc resolvers coded in assembly and \n>> currently there is no gain in continuing doing so. You can rebase your next\n> \n> ARM resolvers are in assembly, and changing them to C would break the \n> build with GCC mainline as the ifunc attribute is not enabled by default \n> there for ARM.\n> \n\nIt is possible to implement the ARM resolvers in C and built it with GCC\nmainline with two adjustments along with default _ifunc macro:\n\n 1. Add the assembly directives for libc_hidden_builtin_def (memcpy)\n using asm as:\n\nasm (\".globl __GI_memcpy;\"\n \".hidden __GI_memcpy;\"\n \"__GI_memcpy = memcpy\");\n\n 2. Circle around which I think it is a GCC bug which it is placing the\n very asm statements from 1. before memcpy resolvers definition\n and thus conflicting with the symbol-hacks.h. I had to disable\n the asm alias from symbol-hacks.h with an extra preprocessor.\n\nI am checking on both arm-linux-gnueabihf and arm-linux-gnueabi and I\nwill prepare a patch.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85376-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"LnZ6mjVW\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6mmb10sfz9sCZ\n\tfor ;\n\tThu, 5 Oct 2017 06:53:34 +1100 (AEDT)","(qmail 124258 invoked by alias); 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\n\tWed, 04 Oct 2017 12:53:25 -0700 (PDT)","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","To":"Joseph Myers ","Cc":"libc-alpha@sourceware.org","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t\n\t","From":"Adhemerval Zanella ","Message-ID":"","Date":"Wed, 4 Oct 2017 16:53:20 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit"}},{"id":1780103,"web_url":"http://patchwork.ozlabs.org/comment/1780103/","msgid":"","list_archive_url":null,"date":"2017-10-04T20:16:25","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":4349,"url":"http://patchwork.ozlabs.org/api/people/4349/","name":"Joseph Myers","email":"joseph@codesourcery.com"},"content":"On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n\n> It is possible to implement the ARM resolvers in C and built it with GCC\n> mainline with two adjustments along with default _ifunc macro:\n\nDo you not get the problems with errors about incompatible types for a \nsymbol and its aliases, in the absence of ifunc attribute support?","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85378-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"PYPsT+3D\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6nHG0vTyz9t39\n\tfor ;\n\tThu, 5 Oct 2017 07:16:41 +1100 (AEDT)","(qmail 7385 invoked by alias); 4 Oct 2017 20:16:36 -0000","(qmail 7374 invoked by uid 89); 4 Oct 2017 20:16:35 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; q=dns; s=default; b=E+2rv\n\t+2LLMst+SFmZaTrXn4z7ytB0VL2NtQUTZjPnIwB8xeWp2bEytCkdVz9RPpH0jaIq\n\ttuDXOkPtlkz3Mbj0VBAXu8BdmILxTGpHM/j752u9PYbuBiv569zEsls2pLQLqOpv\n\tSOx1oK4CZKu6NRhF2G8PbKR+pU1lLHZ0cxyHtU=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; s=default; bh=gAVEqUVopp9\n\tAi14ewWPeKuKAVBs=; b=PYPsT+3Dh6rD8LfSZxQyE8Q1ZNrnIxm7KDExyNkyhHw\n\tG6ucDK/WLoB7sJhBplBIWrii7zTzviBgf31F5v3P4rjyDZKjx84SvevrQN7htfqS\n\tpTyz1qPjxTvLp3fWVUL4LsstGr3NGDMXX7Ie7E16a0YfboW+Mg0l8OI4hiZQzmQQ\n\t=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.0 required=5.0 tests=AWL, BAYES_00,\n\tRCVD_IN_DNSWL_NONE, SPF_PASS,\n\tURIBL_RED autolearn=ham version=3.3.2 spammy=","X-HELO":"relay1.mentorg.com","Date":"Wed, 4 Oct 2017 20:16:25 +0000","From":"Joseph Myers ","To":"Adhemerval Zanella ","CC":"","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","In-Reply-To":"","Message-ID":"","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t\n\t\n\t","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"US-ASCII\"","X-ClientProxiedBy":"svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) To\n\tsvr-ies-mbx-01.mgc.mentorg.com (139.181.222.1)"}},{"id":1780108,"web_url":"http://patchwork.ozlabs.org/comment/1780108/","msgid":"<8e229c32-4ca7-a2e5-82c7-a46cc34563ee@linaro.org>","list_archive_url":null,"date":"2017-10-04T20:39:20","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 04/10/2017 17:16, Joseph Myers wrote:\n> On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n> \n>> It is possible to implement the ARM resolvers in C and built it with GCC\n>> mainline with two adjustments along with default _ifunc macro:\n> \n> Do you not get the problems with errors about incompatible types for a \n> symbol and its aliases, in the absence of ifunc attribute support?\n> \n\nWith two adjustments from my previous message I can build with\nGCC 8.0.0 20171004 (experimental) for armv7. The issue is if we try\nto do something as x86_64 does:\n\n__hidden_ver1 (__new_memcpy, __GI_memcpy, __redirect_memcpy)\n __attribute__ ((visibility (\"hidden\")));\n\nThis indeed dump incompatible types with mainline GCC.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85380-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"m/OGNHNw\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6nnm5X2dz9t69\n\tfor ;\n\tThu, 5 Oct 2017 07:39:40 +1100 (AEDT)","(qmail 96556 invoked by alias); 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\n\tWed, 04 Oct 2017 13:39:25 -0700 (PDT)","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","To":"Joseph Myers ","Cc":"libc-alpha@sourceware.org","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t\n\t\n\t\n\t","From":"Adhemerval Zanella ","Message-ID":"<8e229c32-4ca7-a2e5-82c7-a46cc34563ee@linaro.org>","Date":"Wed, 4 Oct 2017 17:39:20 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"7bit"}},{"id":1780109,"web_url":"http://patchwork.ozlabs.org/comment/1780109/","msgid":"","list_archive_url":null,"date":"2017-10-04T20:41:53","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":4349,"url":"http://patchwork.ozlabs.org/api/people/4349/","name":"Joseph Myers","email":"joseph@codesourcery.com"},"content":"On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n\n> On 04/10/2017 17:16, Joseph Myers wrote:\n> > On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n> > \n> >> It is possible to implement the ARM resolvers in C and built it with GCC\n> >> mainline with two adjustments along with default _ifunc macro:\n> > \n> > Do you not get the problems with errors about incompatible types for a \n> > symbol and its aliases, in the absence of ifunc attribute support?\n> > \n> \n> With two adjustments from my previous message I can build with\n> GCC 8.0.0 20171004 (experimental) for armv7. The issue is if we try\n> to do something as x86_64 does:\n> \n> __hidden_ver1 (__new_memcpy, __GI_memcpy, __redirect_memcpy)\n> __attribute__ ((visibility (\"hidden\")));\n> \n> This indeed dump incompatible types with mainline GCC.\n\nWell, we should first fix mainline GCC to allow ifunc attributes on ARM by \ndefault. Then only consider workarounds in glibc if still needed after \nsuch a fix.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85381-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"oGW+0ux5\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6nrd0nj8z9t69\n\tfor ;\n\tThu, 5 Oct 2017 07:42:08 +1100 (AEDT)","(qmail 98530 invoked by alias); 4 Oct 2017 20:42:03 -0000","(qmail 98518 invoked by uid 89); 4 Oct 2017 20:42:02 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; q=dns; s=default; b=t6cUI\n\t+jgO6zsvvGDmg3X/0WhJKI3NOHkRYqFSPjyMhxX+REQ/rknmoFE2El+hatW43Pug\n\tXsRvt3frMX4yD9MNKP1V66w+iGq0VhZOVpnriXqHfAIjjlrFvsNXj+Wi90109XXs\n\t1g0SQOvXMLuzCwmFFT56vpxWwO0iM/DIhuSbEA=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:in-reply-to:message-id\n\t:references:mime-version:content-type; s=default; bh=vaI90MtUU1b\n\tk4Gd7Ris7X5DzMXY=; b=oGW+0ux5/OI00bRJs8qLYckEPt5EgRLzMN/ZU6jYsqq\n\tXba3nuE9gb6bL1lkgFELYBsEGh82f0OqAfsFosfiGADoSDKyUZBtXgSwY6C4L0Wb\n\txKzZKv84vQag8f4HHNmr3q3QcpgQwWj/++p7ghBbY9Xmb/oNd+h/eyq+pP1U2eJo\n\t=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.0 required=5.0 tests=AWL, BAYES_00,\n\tRCVD_IN_DNSWL_NONE, SPF_PASS,\n\tURIBL_RED autolearn=ham version=3.3.2 spammy=Hx-languages-length:1059","X-HELO":"relay1.mentorg.com","Date":"Wed, 4 Oct 2017 20:41:53 +0000","From":"Joseph Myers ","To":"Adhemerval Zanella ","CC":"","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","In-Reply-To":"<8e229c32-4ca7-a2e5-82c7-a46cc34563ee@linaro.org>","Message-ID":"","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t\n\t\n\t\n\t\n\t<8e229c32-4ca7-a2e5-82c7-a46cc34563ee@linaro.org>","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"US-ASCII\"","X-ClientProxiedBy":"svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) To\n\tsvr-ies-mbx-01.mgc.mentorg.com (139.181.222.1)"}},{"id":1780111,"web_url":"http://patchwork.ozlabs.org/comment/1780111/","msgid":"","list_archive_url":null,"date":"2017-10-04T20:48:16","subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 04/10/2017 17:41, Joseph Myers wrote:\n> On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n> \n>> On 04/10/2017 17:16, Joseph Myers wrote:\n>>> On Wed, 4 Oct 2017, Adhemerval Zanella wrote:\n>>>\n>>>> It is possible to implement the ARM resolvers in C and built it with GCC\n>>>> mainline with two adjustments along with default _ifunc macro:\n>>>\n>>> Do you not get the problems with errors about incompatible types for a \n>>> symbol and its aliases, in the absence of ifunc attribute support?\n>>>\n>>\n>> With two adjustments from my previous message I can build with\n>> GCC 8.0.0 20171004 (experimental) for armv7. The issue is if we try\n>> to do something as x86_64 does:\n>>\n>> __hidden_ver1 (__new_memcpy, __GI_memcpy, __redirect_memcpy)\n>> __attribute__ ((visibility (\"hidden\")));\n>>\n>> This indeed dump incompatible types with mainline GCC.\n> \n> Well, we should first fix mainline GCC to allow ifunc attributes on ARM by \n> default. Then only consider workarounds in glibc if still needed after \n> such a fix.\n> \n\nOk, I will try to check this out on gcc side as well.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85382-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"pkRPGEPT\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6p0D5sM6z9t16\n\tfor ;\n\tThu, 5 Oct 2017 07:48:44 +1100 (AEDT)","(qmail 50204 invoked by alias); 4 Oct 2017 20:48:25 -0000","(qmail 50186 invoked by uid 89); 4 Oct 2017 20:48:24 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:cc:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; q=dns; s=default; b=mTPRD0j7MChV2hBc\n\t15W7G6sjr/GVn8E6z2KUGsBLbnizaQhTq5XhtzEec7CLVlpWU+T9LJ3YyKrbBZgg\n\tBNjKaH5X0lZMl2I0PO92WTjejHR/TrtNWtLy381d69AFe1Sp6yQkZt6iv4h8yGM7\n\tFkrMu5wbnEyZJH3kq1Uzqc8Ff9w=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:cc:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; s=default; bh=AhpV75eNrbFE0HZXts9fhA\n\t7IwUg=; b=pkRPGEPT1Ven7DUu+9cBFfFAPxDxF5G6V6+VPxy/c7bCNvsmKERlZn\n\tpWKB7jAgADS87TaRDWLX3URh4Nt+EzsXGvtgFvmTRT1SOIJ8OZDDzem671IU4FWE\n\tSk0Avb9ZwUED7LrbMPfBdQ3CfAuxZ/yK3f/6tKdbpG6ANuOVmeaac=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-1.9 required=5.0 tests=BAYES_00,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1134","X-HELO":"mail-qk0-f175.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=QiBy/LmimIq4F0AM2U75D8WSNyJgbB4OZ4UY5cXBV8E=;\n\tb=dAL7towv9Sg9ydCi4CFYfUhJOe8TcE3ME5eBlYwDhrhXENugkyDu+UafQvTr6nT/zH\n\tag9wix1jiQlV1Pd2eUvMAB3n72Psz4uoPKKfrWk3pTj2Y3HnEWe65mKMKN3RyXY5AOWP\n\t1OO+sSBxA0b35Di0FMmw5Zwd5WudVhG7sfKfIXRZlD4/gQMlrnmayCSkQ8kal0smKPMt\n\tIGl4CGDNM01yElrRGBGzzQXMTjGnm8qK/BXxF8PG27ufWNAoQYFm9b4XuWYp/dNljzzX\n\tGC2q1i7DZE6mShjRB6OhkFxmW42JJZTYwETs0xAWpIawxJnFy4NpfWa12213MPx8ehlZ\n\tIpWA==","X-Gm-Message-State":"AMCzsaXeeAeoA/UDQhqXn5rnrfmh0tk6JrL922z+Qw9+nPryK2rqaiGI\n\tcPGfhg3UFDtOOosHgwWP5LJqEsKpe/4=","X-Google-Smtp-Source":"AOwi7QBer/QOSinCDl/a1HgwSpmT+X6t5+3hMwqNZ+L75n/NPtRYgwhhDA6DSegbZxhqu17OQA07kQ==","X-Received":"by 10.55.10.18 with SMTP id 18mr11532466qkk.184.1507150101528;\n\tWed, 04 Oct 2017 13:48:21 -0700 (PDT)","Subject":"Re: [PATCH 3/3] sparc: M7 optimized\n\tmemcpy/mempcpy/memmove/memset/bzero.","To":"Joseph Myers ","Cc":"libc-alpha@sourceware.org","References":"<1506542999-97895-1-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-2-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-3-git-send-email-patrick.mcgehearty@oracle.com>\n\t<1506542999-97895-4-git-send-email-patrick.mcgehearty@oracle.com>\n\t<125b565d-1c04-c532-e7f7-8a95ba97702c@linaro.org>\n\t<4f2d87d6-05ca-bef5-3f01-7a97ce19ea16@oracle.com>\n\t\n\t\n\t\n\t\n\t<8e229c32-4ca7-a2e5-82c7-a46cc34563ee@linaro.org>\n\t","From":"Adhemerval Zanella ","Message-ID":"","Date":"Wed, 4 Oct 2017 17:48:16 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"7bit"}}]