[{"id":1776742,"web_url":"http://patchwork.ozlabs.org/comment/1776742/","msgid":"<20170928041056.GB12504@umbus>","list_archive_url":null,"date":"2017-09-28T04:10:56","subject":"Re: [Qemu-devel] [PATCH v2 3/5] pci: Add INTERFACE_PCIE_DEVICE to\n\tall PCIe devices","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Wed, Sep 27, 2017 at 04:56:33PM -0300, Eduardo Habkost wrote:\n> Change all devices that set is_express=1 to implement\n> INTERFACE_PCIE_DEVICE.\n> \n> Cc: Keith Busch \n> Cc: Kevin Wolf \n> Cc: Max Reitz \n> Cc: Dmitry Fleytman \n> Cc: Jason Wang \n> Cc: \"Michael S. Tsirkin\" \n> Cc: Marcel Apfelbaum \n> Cc: Paul Burton \n> Cc: Paolo Bonzini \n> Cc: Hannes Reinecke \n> Cc: qemu-block@nongnu.org\n> Reviewed-by: Alistair Francis \n> Signed-off-by: Eduardo Habkost \n\nReviewed-by: David Gibson \n\n> ---\n> Changes v1 -> v2:\n> * base-xhci is marked as hybrid, now (in another patch)\n> * Included pcie-pci-bridge\n> ---\n> hw/block/nvme.c | 4 ++++\n> hw/net/e1000e.c | 4 ++++\n> hw/pci-bridge/pcie_pci_bridge.c | 1 +\n> hw/pci-bridge/pcie_root_port.c | 4 ++++\n> hw/pci-bridge/xio3130_downstream.c | 4 ++++\n> hw/pci-bridge/xio3130_upstream.c | 4 ++++\n> hw/pci-host/xilinx-pcie.c | 4 ++++\n> hw/scsi/megasas.c | 6 ++++++\n> 8 files changed, 31 insertions(+)\n> \n> diff --git a/hw/block/nvme.c b/hw/block/nvme.c\n> index 9aa32692a3..441e21ed1f 100644\n> --- a/hw/block/nvme.c\n> +++ b/hw/block/nvme.c\n> @@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {\n> .instance_size = sizeof(NvmeCtrl),\n> .class_init = nvme_class_init,\n> .instance_init = nvme_instance_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void nvme_register_types(void)\n> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c\n> index 6c42b4478c..81f7934a59 100644\n> --- a/hw/net/e1000e.c\n> +++ b/hw/net/e1000e.c\n> @@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {\n> .instance_size = sizeof(E1000EState),\n> .class_init = e1000e_class_init,\n> .instance_init = e1000e_instance_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void e1000e_register_types(void)\n> diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c\n> index 9aa5cc3e45..88db143633 100644\n> --- a/hw/pci-bridge/pcie_pci_bridge.c\n> +++ b/hw/pci-bridge/pcie_pci_bridge.c\n> @@ -180,6 +180,7 @@ static const TypeInfo pcie_pci_bridge_info = {\n> .class_init = pcie_pci_bridge_class_init,\n> .interfaces = (InterfaceInfo[]) {\n> { TYPE_HOTPLUG_HANDLER },\n> + { INTERFACE_PCIE_DEVICE },\n> { },\n> }\n> };\n> diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c\n> index 4d588cb22e..9b6e4ce512 100644\n> --- a/hw/pci-bridge/pcie_root_port.c\n> +++ b/hw/pci-bridge/pcie_root_port.c\n> @@ -161,6 +161,10 @@ static const TypeInfo rp_info = {\n> .class_init = rp_class_init,\n> .abstract = true,\n> .class_size = sizeof(PCIERootPortClass),\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void rp_register_types(void)\n> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c\n> index e706f36cb7..7d2f7629c1 100644\n> --- a/hw/pci-bridge/xio3130_downstream.c\n> +++ b/hw/pci-bridge/xio3130_downstream.c\n> @@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {\n> .name = \"xio3130-downstream\",\n> .parent = TYPE_PCIE_SLOT,\n> .class_init = xio3130_downstream_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xio3130_downstream_register_types(void)\n> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c\n> index a052224bbf..227997ce46 100644\n> --- a/hw/pci-bridge/xio3130_upstream.c\n> +++ b/hw/pci-bridge/xio3130_upstream.c\n> @@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {\n> .name = \"x3130-upstream\",\n> .parent = TYPE_PCIE_PORT,\n> .class_init = xio3130_upstream_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xio3130_upstream_register_types(void)\n> diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c\n> index 4613dda1d2..7659253090 100644\n> --- a/hw/pci-host/xilinx-pcie.c\n> +++ b/hw/pci-host/xilinx-pcie.c\n> @@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {\n> .parent = TYPE_PCI_BRIDGE,\n> .instance_size = sizeof(XilinxPCIERoot),\n> .class_init = xilinx_pcie_root_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xilinx_pcie_register(void)\n> diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c\n> index 0db68aacee..535ee267c3 100644\n> --- a/hw/scsi/megasas.c\n> +++ b/hw/scsi/megasas.c\n> @@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {\n> int osts;\n> const VMStateDescription *vmsd;\n> Property *props;\n> + InterfaceInfo *interfaces;\n> } MegasasInfo;\n> \n> static struct MegasasInfo megasas_devices[] = {\n> @@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {\n> .is_express = true,\n> .vmsd = &vmstate_megasas_gen2,\n> .props = megasas_properties_gen2,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> }\n> };\n> \n> @@ -2531,6 +2536,7 @@ static void megasas_register_types(void)\n> type_info.parent = TYPE_MEGASAS_BASE;\n> type_info.class_data = (void *)info;\n> type_info.class_init = megasas_class_init;\n> + type_info.interfaces = info->interfaces;\n> \n> type_register(&type_info);\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"YOsNtO2j\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2hKl2mlDz9sRq\n\tfor ;\n\tThu, 28 Sep 2017 14:19:39 +1000 (AEST)","from localhost ([::1]:57307 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dxQIT-0004ne-ID\n\tfor incoming@patchwork.ozlabs.org; Thu, 28 Sep 2017 00:19:37 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:54031)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dxQCY-0000fy-GD\n\tfor qemu-devel@nongnu.org; Thu, 28 Sep 2017 00:13:32 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dxQCW-0003Xp-Rx\n\tfor qemu-devel@nongnu.org; Thu, 28 Sep 2017 00:13:30 -0400","from ozlabs.org ([103.22.144.67]:46983)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dxQCQ-0003TM-GI; Thu, 28 Sep 2017 00:13:23 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3y2hBN1j2xz9tXs; Thu, 28 Sep 2017 14:13:15 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1506571996;\n\tbh=HFIlVVVA4P5GQIloT6LR1p2kWfF3kXgudtZ8BiypTxY=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=YOsNtO2jhZSCkPM6i8ExT0i80tePnmBo0tTcEVgE53dnlYraMJFQoKYhf9wfFXxex\n\t5ZymH/GSjyfI6cwdVzdgNkBWk9cOxZfgFntdxp/argO7FaY6mynFavfQP8l9vk6o8t\n\tMmxKDEmzN98oKGlZLK3q0+aPTkPr7ztcLpQ9PYKI=","Date":"Thu, 28 Sep 2017 14:10:56 +1000","From":"David Gibson ","To":"Eduardo Habkost ","Message-ID":"<20170928041056.GB12504@umbus>","References":"<20170927195635.16014-1-ehabkost@redhat.com>\n\t<20170927195635.16014-4-ehabkost@redhat.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"TIEGfCGDzZzDroj5\"","Content-Disposition":"inline","In-Reply-To":"<20170927195635.16014-4-ehabkost@redhat.com>","User-Agent":"Mutt/1.9.0 (2017-09-02)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"103.22.144.67","Subject":"Re: [Qemu-devel] [PATCH v2 3/5] pci: Add INTERFACE_PCIE_DEVICE to\n\tall PCIe devices","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Kevin Wolf , Hannes Reinecke ,\n\tqemu-block@nongnu.org, Paul Burton ,\n\t\"Michael S. Tsirkin\" ,\n\tJason Wang , qemu-devel@nongnu.org,\n\tMax Reitz , Keith Busch ,\n\tDmitry Fleytman ,\n\tAlex Williamson ,\n\tPaolo Bonzini , Laine Stump , \n\tAlistair Francis ,\n\tMarcel Apfelbaum , David Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1776913,"web_url":"http://patchwork.ozlabs.org/comment/1776913/","msgid":"<9ad2077b-a161-1100-fb44-bd308e3e412f@redhat.com>","list_archive_url":null,"date":"2017-09-28T09:31:41","subject":"Re: [Qemu-devel] [PATCH v2 3/5] pci: Add INTERFACE_PCIE_DEVICE to\n\tall PCIe devices","submitter":{"id":65362,"url":"http://patchwork.ozlabs.org/api/people/65362/","name":"Marcel Apfelbaum","email":"marcel@redhat.com"},"content":"On 27/09/2017 22:56, Eduardo Habkost wrote:\n> Change all devices that set is_express=1 to implement\n> INTERFACE_PCIE_DEVICE.\n> \n> Cc: Keith Busch \n> Cc: Kevin Wolf \n> Cc: Max Reitz \n> Cc: Dmitry Fleytman \n> Cc: Jason Wang \n> Cc: \"Michael S. Tsirkin\" \n> Cc: Marcel Apfelbaum \n> Cc: Paul Burton \n> Cc: Paolo Bonzini \n> Cc: Hannes Reinecke \n> Cc: qemu-block@nongnu.org\n> Reviewed-by: Alistair Francis \n> Signed-off-by: Eduardo Habkost \n> ---\n> Changes v1 -> v2:\n> * base-xhci is marked as hybrid, now (in another patch)\n> * Included pcie-pci-bridge\n> ---\n> hw/block/nvme.c | 4 ++++\n> hw/net/e1000e.c | 4 ++++\n> hw/pci-bridge/pcie_pci_bridge.c | 1 +\n> hw/pci-bridge/pcie_root_port.c | 4 ++++\n> hw/pci-bridge/xio3130_downstream.c | 4 ++++\n> hw/pci-bridge/xio3130_upstream.c | 4 ++++\n> hw/pci-host/xilinx-pcie.c | 4 ++++\n> hw/scsi/megasas.c | 6 ++++++\n> 8 files changed, 31 insertions(+)\n> \n> diff --git a/hw/block/nvme.c b/hw/block/nvme.c\n> index 9aa32692a3..441e21ed1f 100644\n> --- a/hw/block/nvme.c\n> +++ b/hw/block/nvme.c\n> @@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {\n> .instance_size = sizeof(NvmeCtrl),\n> .class_init = nvme_class_init,\n> .instance_init = nvme_instance_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void nvme_register_types(void)\n> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c\n> index 6c42b4478c..81f7934a59 100644\n> --- a/hw/net/e1000e.c\n> +++ b/hw/net/e1000e.c\n> @@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {\n> .instance_size = sizeof(E1000EState),\n> .class_init = e1000e_class_init,\n> .instance_init = e1000e_instance_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void e1000e_register_types(void)\n> diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c\n> index 9aa5cc3e45..88db143633 100644\n> --- a/hw/pci-bridge/pcie_pci_bridge.c\n> +++ b/hw/pci-bridge/pcie_pci_bridge.c\n> @@ -180,6 +180,7 @@ static const TypeInfo pcie_pci_bridge_info = {\n> .class_init = pcie_pci_bridge_class_init,\n> .interfaces = (InterfaceInfo[]) {\n> { TYPE_HOTPLUG_HANDLER },\n> + { INTERFACE_PCIE_DEVICE },\n> { },\n> }\n> };\n> diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c\n> index 4d588cb22e..9b6e4ce512 100644\n> --- a/hw/pci-bridge/pcie_root_port.c\n> +++ b/hw/pci-bridge/pcie_root_port.c\n> @@ -161,6 +161,10 @@ static const TypeInfo rp_info = {\n> .class_init = rp_class_init,\n> .abstract = true,\n> .class_size = sizeof(PCIERootPortClass),\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void rp_register_types(void)\n> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c\n> index e706f36cb7..7d2f7629c1 100644\n> --- a/hw/pci-bridge/xio3130_downstream.c\n> +++ b/hw/pci-bridge/xio3130_downstream.c\n> @@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {\n> .name = \"xio3130-downstream\",\n> .parent = TYPE_PCIE_SLOT,\n> .class_init = xio3130_downstream_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xio3130_downstream_register_types(void)\n> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c\n> index a052224bbf..227997ce46 100644\n> --- a/hw/pci-bridge/xio3130_upstream.c\n> +++ b/hw/pci-bridge/xio3130_upstream.c\n> @@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {\n> .name = \"x3130-upstream\",\n> .parent = TYPE_PCIE_PORT,\n> .class_init = xio3130_upstream_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xio3130_upstream_register_types(void)\n> diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c\n> index 4613dda1d2..7659253090 100644\n> --- a/hw/pci-host/xilinx-pcie.c\n> +++ b/hw/pci-host/xilinx-pcie.c\n> @@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {\n> .parent = TYPE_PCI_BRIDGE,\n> .instance_size = sizeof(XilinxPCIERoot),\n> .class_init = xilinx_pcie_root_class_init,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> };\n> \n> static void xilinx_pcie_register(void)\n> diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c\n> index 0db68aacee..535ee267c3 100644\n> --- a/hw/scsi/megasas.c\n> +++ b/hw/scsi/megasas.c\n> @@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {\n> int osts;\n> const VMStateDescription *vmsd;\n> Property *props;\n> + InterfaceInfo *interfaces;\n> } MegasasInfo;\n> \n> static struct MegasasInfo megasas_devices[] = {\n> @@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {\n> .is_express = true,\n> .vmsd = &vmstate_megasas_gen2,\n> .props = megasas_properties_gen2,\n> + .interfaces = (InterfaceInfo[]) {\n> + { INTERFACE_PCIE_DEVICE },\n> + { }\n> + },\n> }\n> };\n> \n> @@ -2531,6 +2536,7 @@ static void megasas_register_types(void)\n> type_info.parent = TYPE_MEGASAS_BASE;\n> type_info.class_data = (void *)info;\n> type_info.class_init = megasas_class_init;\n> + type_info.interfaces = info->interfaces;\n> \n> type_register(&type_info);\n> }\n> \n\nReviewed-by: Marcel Apfelbaum \n\nThanks,\nMarcel","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=marcel@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2qH35lkvz9t3h\n\tfor ;\n\tThu, 28 Sep 2017 19:32:47 +1000 (AEST)","from localhost ([::1]:58167 helo=lists.gnu.org)\n\tby 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Tsirkin\" ,\n\tJason Wang , Max Reitz ,\n\tKeith Busch ,\n\tAlex Williamson ,\n\tPaolo Bonzini , Laine Stump , \n\tAlistair Francis ,\n\tDmitry Fleytman , David Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]