[{"id":1790376,"web_url":"http://patchwork.ozlabs.org/comment/1790376/","msgid":"<20171019104817.GJ9005@ulmo>","list_archive_url":null,"date":"2017-10-19T10:48:17","subject":"Re: [PATCH V2 3/4] arm64: tegra: Add PCIe node for Tegra186","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Wed, Sep 27, 2017 at 05:28:36PM +0530, Manikanta Maddireddy wrote:\n> Tegra186 has three PCIe controllers, which can be operated\n> in 401, 211 or 111 lane combinations. Add DT support for\n> PCIe controllers.\n> \n> Signed-off-by: Manikanta Maddireddy \n> Reviewed-by: Mikko Perttunen \n> Tested-by: Mikko Perttunen \n> ---\n> V2: No change in this patch\n> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 82 ++++++++++++++++++++++++++++++++\n> 1 file changed, 82 insertions(+)\n> \n> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> index 0b0552c9f7dd..9edf2a839e5d 100644\n> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> @@ -443,6 +443,7 @@\n> \t\tshmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;\n> \t\t#clock-cells = <1>;\n> \t\t#reset-cells = <1>;\n> +\t\t#power-domain-cells = <1>;\n> \n> \t\tbpmp_i2c: i2c {\n> \t\t\tcompatible = \"nvidia,tegra186-bpmp-i2c\";\n> @@ -465,4 +466,85 @@\n> \t\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n> \t\tinterrupt-parent = <&gic>;\n> \t};\n> +\n> +\tpcie@10003000 {\n\nI sorted this in correctly. For the future, please sort nodes by unit\naddress. If a node doesn't have a unit address, sort it by name and\nafter those with a unit address.\n\nAlso removed a gratuituous blank line.\n\nApplied to for-4.15/arm64/dt.\n\nThanks,\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Rkp3UA/0\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yHlyc1QMWz9t44\n\tfor ;\n\tThu, 19 Oct 2017 21:48:24 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751739AbdJSKsV (ORCPT );\n\tThu, 19 Oct 2017 06:48:21 -0400","from mail-qk0-f193.google.com ([209.85.220.193]:50450 \"EHLO\n\tmail-qk0-f193.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751311AbdJSKsU (ORCPT\n\t); Thu, 19 Oct 2017 06:48:20 -0400","by mail-qk0-f193.google.com with SMTP id o187so9767059qke.7;\n\tThu, 19 Oct 2017 03:48:20 -0700 (PDT)","from localhost\n\t(p200300E41BE4FD00CEAD5B94E1CFD280.dip0.t-ipconnect.de.\n\t[2003:e4:1be4:fd00:cead:5b94:e1cf:d280])\n\tby smtp.gmail.com with ESMTPSA id\n\tf66sm8716611qkc.25.2017.10.19.03.48.18\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 19 Oct 2017 03:48:19 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=iLIg9ORFlRXmUmGvP/VblaAqdrxKqaE5/S7hmlhBLIE=;\n\tb=Rkp3UA/05nslsedPsbb9vtMTQt/1liVYDFhhAjC/9K1iUACOiUQFmRTvFr3NTcWy/Q\n\tA0knmyM5uXEZdpfG6pBEBE+mcbt8JeBHYpLLq+ugHbzzvmIaiUMHn5IxIrANoKGcOm6+\n\tAjowK6brBXLuTLvwGnFqlxgkF4JDe7E5pzrNSnByr3OvYIY2HYPSP4hQXFxmuvY5uQuI\n\tGjSzctDVQXZWQ+jpxSEZy6HXnxLyg0PxtcQWqoH9jo5EhZUl9IXuZy4qNV7pMKftwAWr\n\t7dFrwExH61Tc4g4IkJ/N31R0dPMbE9wBO86QqSyOKfOS4++/0zDb/2iqH8DEHTekaA/x\n\tAQOw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=iLIg9ORFlRXmUmGvP/VblaAqdrxKqaE5/S7hmlhBLIE=;\n\tb=Mx6BO/MOt+zwxCrbgW3bqAeKkg7IxdzB2Be4brMvYi9mVL4E3TOO9xnG5kP1Puii9n\n\txE4exK61cOIqYYG9i2CTTYtzfLZbtiZCqN8B4qxqzbQiR9HhN3mKnOuG0WG+zezWBHbi\n\tydFN24fS/61L04UzQEeVbqYV5IamnZxde8H+vTfK9iAyvd1JywluonM5/JqwYMXsaml6\n\tHy5uxXi/s4PySaTt+zmO9ODA8oroG+CyweoBsSLcbb1wCcD6GUsLdq2ppxb85ux/SU8u\n\tlNYMfDhxw/N/zGcpvTWrJJipMsj5yoS6CvZbpqmHtOe5A7OlAVIWrdWGPY9hnSomozsa\n\txSOA==","X-Gm-Message-State":"AMCzsaWzl5ssZ0mzEFRU+vcv1CQJ7LQHJ6sASopPFgfMXt16fkeYEjpW\n\tZcn+OrJzzXLMwTOj5f1Kb3U=","X-Google-Smtp-Source":"ABhQp+SHhWgTtjhpPqJ6gzPN/JhC3cXJrTFSUbYzgZpEelUWBQ3LkYi1SKwdsJw9qR3AzFgTCY1eJg==","X-Received":"by 10.55.100.14 with SMTP id y14mr1197635qkb.242.1508410099781; \n\tThu, 19 Oct 2017 03:48:19 -0700 (PDT)","Date":"Thu, 19 Oct 2017 12:48:17 +0200","From":"Thierry Reding ","To":"Manikanta Maddireddy ","Cc":"bhelgaas@google.com, jonathanh@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,\n\tmperttunen@nvidia.com","Subject":"Re: [PATCH V2 3/4] arm64: tegra: Add PCIe node for Tegra186","Message-ID":"<20171019104817.GJ9005@ulmo>","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>\n\t<1506513517-25870-4-git-send-email-mmaddireddy@nvidia.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"CxDuMX1Cv2n9FQfo\"","Content-Disposition":"inline","In-Reply-To":"<1506513517-25870-4-git-send-email-mmaddireddy@nvidia.com>","User-Agent":"Mutt/1.9.1 (2017-09-22)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]