[{"id":1786438,"web_url":"http://patchwork.ozlabs.org/comment/1786438/","msgid":"<20171013163712.GA8761@ulmo>","list_archive_url":null,"date":"2017-10-13T16:37:12","subject":"Re: [PATCH V2 1/4] dt-bindings: pci: tegra: Document Tegra186 PCIe\n\tDT","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Wed, Sep 27, 2017 at 05:28:34PM +0530, Manikanta Maddireddy wrote:\n> Tegra186 PCIe controller DT properties has couple of differences\n> wrt Tegra210 PCIe, rest of the DT properties are same.\n> \n> Signed-off-by: Manikanta Maddireddy \n> Reviewed-by: Mikko Perttunen \n> Tested-by: Mikko Perttunen \n> ---\n> V2: No change in this patch\n> .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++-\n> 1 file changed, 130 insertions(+), 4 deletions(-)\n\nHi Rob,\n\nManikanta forgot to add you on Cc on this one. Can you take a look or\nshould Manikanta resend the series to include you and the device tree\nmailing list?\n\nFWIW, this looks good to me, so:\n\nAcked-by: Thierry Reding \n\nBjorn,\n\nI take it that you'd pull this into the PCI tree along with the host\ncontroller driver changes? I can take patches 3 and 4 through the Tegra\ntree.\n\nThierry\n\n> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\n> index 982a74ea6df9..753b67327373 100644\n> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\n> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\n> @@ -1,10 +1,15 @@\n> NVIDIA Tegra PCIe controller\n> \n> Required properties:\n> -- compatible: For Tegra20, must contain \"nvidia,tegra20-pcie\". For Tegra30,\n> - \"nvidia,tegra30-pcie\". For Tegra124, must contain \"nvidia,tegra124-pcie\".\n> - Otherwise, must contain \"nvidia,-pcie\", plus one of the above, where\n> - is tegra132 or tegra210.\n> +- compatible: Must be:\n> + - \"nvidia,tegra20-pcie\": for Tegra20\n> + - \"nvidia,tegra30-pcie\": for Tegra30\n> + - \"nvidia,tegra124-pcie\": for Tegra124 and Tegra132\n> + - \"nvidia,tegra210-pcie\": for Tegra210\n> + - \"nvidia,tegra186-pcie\": for Tegra186\n> +- power-domains: To ungate power partition by BPMP powergate driver. Must\n> +contain BPMP phandle and PCIe power partition ID. This is required only\n> +for Tegra186.\n> - device_type: Must be \"pci\"\n> - reg: A list of physical base address and length for each set of controller\n> registers. Must contain an entry for each entry in the reg-names property.\n> @@ -124,6 +129,16 @@ Power supplies for Tegra210:\n> - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must\n> supply 1.8 V.\n> \n> +Power supplies for Tegra186:\n> +- Required:\n> + - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.\n> + - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must\n> + supply 1.8 V.\n> + - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.\n> + Must supply 1.8 V.\n> + - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must\n> + supply 1.8 V.\n> +\n> Root ports are defined as subnodes of the PCIe controller node.\n> \n> Required properties:\n> @@ -546,3 +561,114 @@ Board DTS:\n> \t\t\tstatus = \"okay\";\n> \t\t};\n> \t};\n> +\n> +Tegra186:\n> +---------\n> +\n> +SoC DTSI:\n> +\n> +\tpcie@10003000 {\n> +\t\tcompatible = \"nvidia,tegra186-pcie\";\n> +\t\tpower-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;\n> +\t\tdevice_type = \"pci\";\n> +\t\treg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */\n> +\t\t 0x0 0x10003800 0x0 0x00000800 /* AFI registers */\n> +\t\t 0x0 0x40000000 0x0 0x10000000>; /* configuration space */\n> +\t\treg-names = \"pads\", \"afi\", \"cs\";\n> +\n> +\t\tinterrupts = , /* controller interrupt */\n> +\t\t\t ; /* MSI interrupt */\n> +\t\tinterrupt-names = \"intr\", \"msi\";\n> +\n> +\t\t#interrupt-cells = <1>;\n> +\t\tinterrupt-map-mask = <0 0 0 0>;\n> +\t\tinterrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n> +\n> +\t\tbus-range = <0x00 0xff>;\n> +\t\t#address-cells = <3>;\n> +\t\t#size-cells = <2>;\n> +\n> +\t\tranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */\n> +\t\t\t 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */\n> +\t\t\t 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */\n> +\t\t\t 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */\n> +\t\t\t 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */\n> +\t\t\t 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */\n> +\n> +\t\tclocks = <&bpmp TEGRA186_CLK_AFI>,\n> +\t\t\t <&bpmp TEGRA186_CLK_PCIE>,\n> +\t\t\t <&bpmp TEGRA186_CLK_PLLE>;\n> +\t\tclock-names = \"afi\", \"pex\", \"pll_e\";\n> +\n> +\t\tresets = <&bpmp TEGRA186_RESET_AFI>,\n> +\t\t\t <&bpmp TEGRA186_RESET_PCIE>,\n> +\t\t\t <&bpmp TEGRA186_RESET_PCIEXCLK>;\n> +\t\treset-names = \"afi\", \"pex\", \"pcie_x\";\n> +\n> +\t\tstatus = \"disabled\";\n> +\n> +\t\tpci@1,0 {\n> +\t\t\tdevice_type = \"pci\";\n> +\t\t\tassigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;\n> +\t\t\treg = <0x000800 0 0 0 0>;\n> +\t\t\tstatus = \"disabled\";\n> +\n> +\t\t\t#address-cells = <3>;\n> +\t\t\t#size-cells = <2>;\n> +\t\t\tranges;\n> +\n> +\t\t\tnvidia,num-lanes = <2>;\n> +\t\t};\n> +\n> +\t\tpci@2,0 {\n> +\t\t\tdevice_type = \"pci\";\n> +\t\t\tassigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;\n> +\t\t\treg = <0x001000 0 0 0 0>;\n> +\t\t\tstatus = \"disabled\";\n> +\n> +\t\t\t#address-cells = <3>;\n> +\t\t\t#size-cells = <2>;\n> +\t\t\tranges;\n> +\n> +\t\t\tnvidia,num-lanes = <1>;\n> +\t\t};\n> +\n> +\t\tpci@3,0 {\n> +\t\t\tdevice_type = \"pci\";\n> +\t\t\tassigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;\n> +\t\t\treg = <0x001800 0 0 0 0>;\n> +\t\t\tstatus = \"disabled\";\n> +\n> +\t\t\t#address-cells = <3>;\n> +\t\t\t#size-cells = <2>;\n> +\t\t\tranges;\n> +\n> +\t\t\tnvidia,num-lanes = <1>;\n> +\t\t};\n> +\t};\n> +\n> +Board DTS:\n> +\n> +\tpcie@10003000 {\n> +\t\tstatus = \"okay\";\n> +\n> +\t\tdvdd-pex-supply = <&vdd_pex>;\n> +\t\thvdd-pex-pll-supply = <&vdd_1v8>;\n> +\t\thvdd-pex-supply = <&vdd_1v8>;\n> +\t\tvddio-pexctl-aud-supply = <&vdd_1v8>;\n> +\n> +\t\tpci@1,0 {\n> +\t\t\tnvidia,num-lanes = <4>;\n> +\t\t\tstatus = \"okay\";\n> +\t\t};\n> +\n> +\t\tpci@2,0 {\n> +\t\t\tnvidia,num-lanes = <0>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tpci@3,0 {\n> +\t\t\tnvidia,num-lanes = <1>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\t};\n> -- \n> 2.1.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tFri, 13 Oct 2017 09:37:14 -0700 (PDT)","Date":"Fri, 13 Oct 2017 18:37:12 +0200","From":"Thierry Reding ","To":"Rob Herring , Bjorn Helgaas ","Cc":"Manikanta Maddireddy , bhelgaas@google.com,\n\tjonathanh@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n\tmperttunen@nvidia.com","Subject":"Re: [PATCH V2 1/4] dt-bindings: pci: tegra: Document Tegra186 PCIe\n\tDT","Message-ID":"<20171013163712.GA8761@ulmo>","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>\n\t<1506513517-25870-2-git-send-email-mmaddireddy@nvidia.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"u3/rZRmxL6MmkK24\"","Content-Disposition":"inline","In-Reply-To":"<1506513517-25870-2-git-send-email-mmaddireddy@nvidia.com>","User-Agent":"Mutt/1.9.1 (2017-09-22)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]