[{"id":1776164,"web_url":"http://patchwork.ozlabs.org/comment/1776164/","msgid":"<8F91DDED-60B9-4C6E-9DEA-5A66C018DEC0@theobroma-systems.com>","list_archive_url":null,"date":"2017-09-27T08:46:20","subject":"Re: [U-Boot] [PATCH v4 1/2] rockchip: rk322x: add sdram driver","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 27 Sep 2017, at 10:38, Kever Yang <kever.yang@rock-chips.com> wrote:\n> \n> Add driver for rk322x to support sdram initialize in SPL.\n> \n> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>\n\nAcked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nReviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n\nAs previously discussed, I'll merge this in its current form (i.e. duplicating code\nand data structures) with a commitment (AFAIK there is work ongoing towards this\ngoal at Rockchip, but it will take a while to complete) to unify our DRAM drivers in\none of the upcoming merge windows.\n\n> ---\n> \n> Changes in v4:\n> - rebase on u-boot-rockchip master with patchset \"move rockchip sdram\n>  driver to driver/ram”\n\nThanks for doing this.\nThis saves me a lot of work.\n\nRegards,\nPhilipp.\n\n> Changes in v3:\n> - move rk332x sdram driver to driver/ram\n> - do the ram init in TPL instad of SPL\n> \n> arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++++++++++++++\n> drivers/ram/rockchip/Makefile                     |   1 +\n> drivers/ram/rockchip/sdram_rk322x.c               | 855 ++++++++++++++++++++++\n> 3 files changed, 1437 insertions(+)\n> create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h\n> create mode 100644 drivers/ram/rockchip/sdram_rk322x.c\n> \n> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h\n> new file mode 100644\n> index 0000000..b40da40\n> --- /dev/null\n> +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h\n> @@ -0,0 +1,581 @@\n> +/*\n> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n> + *\n> + * SPDX-License-Identifier:     GPL-2.0+\n> + */\n> +#ifndef _ASM_ARCH_SDRAM_RK322X_H\n> +#define _ASM_ARCH_SDRAM_RK322X_H\n> +\n> +#include <common.h>\n> +\n> +enum {\n> +\tDDR3\t\t= 3,\n> +\tLPDDR2\t\t= 5,\n> +\tLPDDR3\t\t= 6,\n> +\tUNUSED\t\t= 0xFF,\n> +};\n> +\n> +struct rk322x_sdram_channel {\n> +\t/*\n> +\t * bit width in address, eg:\n> +\t * 8 banks using 3 bit to address,\n> +\t * 2 cs using 1 bit to address.\n> +\t */\n> +\tu8 rank;\n> +\tu8 col;\n> +\tu8 bk;\n> +\tu8 bw;\n> +\tu8 dbw;\n> +\tu8 row_3_4;\n> +\tu8 cs0_row;\n> +\tu8 cs1_row;\n> +#if CONFIG_IS_ENABLED(OF_PLATDATA)\n> +\t/*\n> +\t * For of-platdata, which would otherwise convert this into two\n> +\t * byte-swapped integers. With a size of 9 bytes, this struct will\n> +\t * appear in of-platdata as a byte array.\n> +\t *\n> +\t * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)\n> +\t */\n> +\tu8 dummy;\n> +#endif\n> +};\n> +\n> +struct rk322x_ddr_pctl {\n> +\tu32 scfg;\n> +\tu32 sctl;\n> +\tu32 stat;\n> +\tu32 intrstat;\n> +\tu32 reserved0[(0x40 - 0x10) / 4];\n> +\tu32 mcmd;\n> +\tu32 powctl;\n> +\tu32 powstat;\n> +\tu32 cmdtstat;\n> +\tu32 cmdtstaten;\n> +\tu32 reserved1[(0x60 - 0x54) / 4];\n> +\tu32 mrrcfg0;\n> +\tu32 mrrstat0;\n> +\tu32 mrrstat1;\n> +\tu32 reserved2[(0x7c - 0x6c) / 4];\n> +\n> +\tu32 mcfg1;\n> +\tu32 mcfg;\n> +\tu32 ppcfg;\n> +\tu32 mstat;\n> +\tu32 lpddr2zqcfg;\n> +\tu32 reserved3;\n> +\n> +\tu32 dtupdes;\n> +\tu32 dtuna;\n> +\tu32 dtune;\n> +\tu32 dtuprd0;\n> +\tu32 dtuprd1;\n> +\tu32 dtuprd2;\n> +\tu32 dtuprd3;\n> +\tu32 dtuawdt;\n> +\tu32 reserved4[(0xc0 - 0xb4) / 4];\n> +\n> +\tu32 togcnt1u;\n> +\tu32 tinit;\n> +\tu32 trsth;\n> +\tu32 togcnt100n;\n> +\tu32 trefi;\n> +\tu32 tmrd;\n> +\tu32 trfc;\n> +\tu32 trp;\n> +\tu32 trtw;\n> +\tu32 tal;\n> +\tu32 tcl;\n> +\tu32 tcwl;\n> +\tu32 tras;\n> +\tu32 trc;\n> +\tu32 trcd;\n> +\tu32 trrd;\n> +\tu32 trtp;\n> +\tu32 twr;\n> +\tu32 twtr;\n> +\tu32 texsr;\n> +\tu32 txp;\n> +\tu32 txpdll;\n> +\tu32 tzqcs;\n> +\tu32 tzqcsi;\n> +\tu32 tdqs;\n> +\tu32 tcksre;\n> +\tu32 tcksrx;\n> +\tu32 tcke;\n> +\tu32 tmod;\n> +\tu32 trstl;\n> +\tu32 tzqcl;\n> +\tu32 tmrr;\n> +\tu32 tckesr;\n> +\tu32 tdpd;\n> +\tu32 tref_mem_ddr3;\n> +\tu32 reserved5[(0x180 - 0x14c) / 4];\n> +\tu32 ecccfg;\n> +\tu32 ecctst;\n> +\tu32 eccclr;\n> +\tu32 ecclog;\n> +\tu32 reserved6[(0x200 - 0x190) / 4];\n> +\tu32 dtuwactl;\n> +\tu32 dturactl;\n> +\tu32 dtucfg;\n> +\tu32 dtuectl;\n> +\tu32 dtuwd0;\n> +\tu32 dtuwd1;\n> +\tu32 dtuwd2;\n> +\tu32 dtuwd3;\n> +\tu32 dtuwdm;\n> +\tu32 dturd0;\n> +\tu32 dturd1;\n> +\tu32 dturd2;\n> +\tu32 dturd3;\n> +\tu32 dtulfsrwd;\n> +\tu32 dtulfsrrd;\n> +\tu32 dtueaf;\n> +\t/* dfi control registers */\n> +\tu32 dfitctrldelay;\n> +\tu32 dfiodtcfg;\n> +\tu32 dfiodtcfg1;\n> +\tu32 dfiodtrankmap;\n> +\t/* dfi write data registers */\n> +\tu32 dfitphywrdata;\n> +\tu32 dfitphywrlat;\n> +\tu32 reserved7[(0x260 - 0x258) / 4];\n> +\tu32 dfitrddataen;\n> +\tu32 dfitphyrdlat;\n> +\tu32 reserved8[(0x270 - 0x268) / 4];\n> +\tu32 dfitphyupdtype0;\n> +\tu32 dfitphyupdtype1;\n> +\tu32 dfitphyupdtype2;\n> +\tu32 dfitphyupdtype3;\n> +\tu32 dfitctrlupdmin;\n> +\tu32 dfitctrlupdmax;\n> +\tu32 dfitctrlupddly;\n> +\tu32 reserved9;\n> +\tu32 dfiupdcfg;\n> +\tu32 dfitrefmski;\n> +\tu32 dfitctrlupdi;\n> +\tu32 reserved10[(0x2ac - 0x29c) / 4];\n> +\tu32 dfitrcfg0;\n> +\tu32 dfitrstat0;\n> +\tu32 dfitrwrlvlen;\n> +\tu32 dfitrrdlvlen;\n> +\tu32 dfitrrdlvlgateen;\n> +\tu32 dfiststat0;\n> +\tu32 dfistcfg0;\n> +\tu32 dfistcfg1;\n> +\tu32 reserved11;\n> +\tu32 dfitdramclken;\n> +\tu32 dfitdramclkdis;\n> +\tu32 dfistcfg2;\n> +\tu32 dfistparclr;\n> +\tu32 dfistparlog;\n> +\tu32 reserved12[(0x2f0 - 0x2e4) / 4];\n> +\n> +\tu32 dfilpcfg0;\n> +\tu32 reserved13[(0x300 - 0x2f4) / 4];\n> +\tu32 dfitrwrlvlresp0;\n> +\tu32 dfitrwrlvlresp1;\n> +\tu32 dfitrwrlvlresp2;\n> +\tu32 dfitrrdlvlresp0;\n> +\tu32 dfitrrdlvlresp1;\n> +\tu32 dfitrrdlvlresp2;\n> +\tu32 dfitrwrlvldelay0;\n> +\tu32 dfitrwrlvldelay1;\n> +\tu32 dfitrwrlvldelay2;\n> +\tu32 dfitrrdlvldelay0;\n> +\tu32 dfitrrdlvldelay1;\n> +\tu32 dfitrrdlvldelay2;\n> +\tu32 dfitrrdlvlgatedelay0;\n> +\tu32 dfitrrdlvlgatedelay1;\n> +\tu32 dfitrrdlvlgatedelay2;\n> +\tu32 dfitrcmd;\n> +\tu32 reserved14[(0x3f8 - 0x340) / 4];\n> +\tu32 ipvr;\n> +\tu32 iptr;\n> +};\n> +check_member(rk322x_ddr_pctl, iptr, 0x03fc);\n> +\n> +struct rk322x_ddr_phy {\n> +\tu32 ddrphy_reg[0x100];\n> +};\n> +\n> +struct rk322x_pctl_timing {\n> +\tu32 togcnt1u;\n> +\tu32 tinit;\n> +\tu32 trsth;\n> +\tu32 togcnt100n;\n> +\tu32 trefi;\n> +\tu32 tmrd;\n> +\tu32 trfc;\n> +\tu32 trp;\n> +\tu32 trtw;\n> +\tu32 tal;\n> +\tu32 tcl;\n> +\tu32 tcwl;\n> +\tu32 tras;\n> +\tu32 trc;\n> +\tu32 trcd;\n> +\tu32 trrd;\n> +\tu32 trtp;\n> +\tu32 twr;\n> +\tu32 twtr;\n> +\tu32 texsr;\n> +\tu32 txp;\n> +\tu32 txpdll;\n> +\tu32 tzqcs;\n> +\tu32 tzqcsi;\n> +\tu32 tdqs;\n> +\tu32 tcksre;\n> +\tu32 tcksrx;\n> +\tu32 tcke;\n> +\tu32 tmod;\n> +\tu32 trstl;\n> +\tu32 tzqcl;\n> +\tu32 tmrr;\n> +\tu32 tckesr;\n> +\tu32 tdpd;\n> +\tu32 trefi_mem_ddr3;\n> +};\n> +\n> +struct rk322x_phy_timing {\n> +\tu32 mr[4];\n> +\tu32 mr11;\n> +\tu32 bl;\n> +\tu32 cl_al;\n> +};\n> +\n> +struct rk322x_msch_timings {\n> +\tu32 ddrtiming;\n> +\tu32 ddrmode;\n> +\tu32 readlatency;\n> +\tu32 activate;\n> +\tu32 devtodev;\n> +};\n> +\n> +struct rk322x_service_sys {\n> +\tu32 id_coreid;\n> +\tu32 id_revisionid;\n> +\tu32 ddrconf;\n> +\tu32 ddrtiming;\n> +\tu32 ddrmode;\n> +\tu32 readlatency;\n> +\tu32 activate;\n> +\tu32 devtodev;\n> +};\n> +\n> +struct rk322x_base_params {\n> +\tstruct rk322x_msch_timings noc_timing;\n> +\tu32 ddrconfig;\n> +\tu32 ddr_freq;\n> +\tu32 dramtype;\n> +\t/*\n> +\t * unused for rk322x\n> +\t */\n> +\tu32 stride;\n> +\tu32 odt;\n> +};\n> +\n> +/* PCT_DFISTCFG0 */\n> +#define DFI_INIT_START\t\t\tBIT(0)\n> +#define DFI_DATA_BYTE_DISABLE_EN\tBIT(2)\n> +\n> +/* PCT_DFISTCFG1 */\n> +#define DFI_DRAM_CLK_SR_EN\t\tBIT(0)\n> +#define DFI_DRAM_CLK_DPD_EN\t\tBIT(1)\n> +\n> +/* PCT_DFISTCFG2 */\n> +#define DFI_PARITY_INTR_EN\t\tBIT(0)\n> +#define DFI_PARITY_EN\t\t\tBIT(1)\n> +\n> +/* PCT_DFILPCFG0 */\n> +#define TLP_RESP_TIME_SHIFT\t\t16\n> +#define LP_SR_EN\t\t\tBIT(8)\n> +#define LP_PD_EN\t\t\tBIT(0)\n> +\n> +/* PCT_DFITCTRLDELAY */\n> +#define TCTRL_DELAY_TIME_SHIFT\t\t0\n> +\n> +/* PCT_DFITPHYWRDATA */\n> +#define TPHY_WRDATA_TIME_SHIFT\t\t0\n> +\n> +/* PCT_DFITPHYRDLAT */\n> +#define TPHY_RDLAT_TIME_SHIFT\t\t0\n> +\n> +/* PCT_DFITDRAMCLKDIS */\n> +#define TDRAM_CLK_DIS_TIME_SHIFT\t0\n> +\n> +/* PCT_DFITDRAMCLKEN */\n> +#define TDRAM_CLK_EN_TIME_SHIFT\t\t0\n> +\n> +/* PCTL_DFIODTCFG */\n> +#define RANK0_ODT_WRITE_SEL\t\tBIT(3)\n> +#define RANK1_ODT_WRITE_SEL\t\tBIT(11)\n> +\n> +/* PCTL_DFIODTCFG1 */\n> +#define ODT_LEN_BL8_W_SHIFT\t\t16\n> +\n> +/* PUBL_ACDLLCR */\n> +#define ACDLLCR_DLLDIS\t\t\tBIT(31)\n> +#define ACDLLCR_DLLSRST\t\t\tBIT(30)\n> +\n> +/* PUBL_DXDLLCR */\n> +#define DXDLLCR_DLLDIS\t\t\tBIT(31)\n> +#define DXDLLCR_DLLSRST\t\t\tBIT(30)\n> +\n> +/* PUBL_DLLGCR */\n> +#define DLLGCR_SBIAS\t\t\tBIT(30)\n> +\n> +/* PUBL_DXGCR */\n> +#define DQSRTT\t\t\t\tBIT(9)\n> +#define DQRTT\t\t\t\tBIT(10)\n> +\n> +/* PIR */\n> +#define PIR_INIT\t\t\tBIT(0)\n> +#define PIR_DLLSRST\t\t\tBIT(1)\n> +#define PIR_DLLLOCK\t\t\tBIT(2)\n> +#define PIR_ZCAL\t\t\tBIT(3)\n> +#define PIR_ITMSRST\t\t\tBIT(4)\n> +#define PIR_DRAMRST\t\t\tBIT(5)\n> +#define PIR_DRAMINIT\t\t\tBIT(6)\n> +#define PIR_QSTRN\t\t\tBIT(7)\n> +#define PIR_RVTRN\t\t\tBIT(8)\n> +#define PIR_ICPC\t\t\tBIT(16)\n> +#define PIR_DLLBYP\t\t\tBIT(17)\n> +#define PIR_CTLDINIT\t\t\tBIT(18)\n> +#define PIR_CLRSR\t\t\tBIT(28)\n> +#define PIR_LOCKBYP\t\t\tBIT(29)\n> +#define PIR_ZCALBYP\t\t\tBIT(30)\n> +#define PIR_INITBYP\t\t\tBIT(31)\n> +\n> +/* PGCR */\n> +#define PGCR_DFTLMT_SHIFT\t\t3\n> +#define PGCR_DFTCMP_SHIFT\t\t2\n> +#define PGCR_DQSCFG_SHIFT\t\t1\n> +#define PGCR_ITMDMD_SHIFT\t\t0\n> +\n> +/* PGSR */\n> +#define PGSR_IDONE\t\t\tBIT(0)\n> +#define PGSR_DLDONE\t\t\tBIT(1)\n> +#define PGSR_ZCDONE\t\t\tBIT(2)\n> +#define PGSR_DIDONE\t\t\tBIT(3)\n> +#define PGSR_DTDONE\t\t\tBIT(4)\n> +#define PGSR_DTERR\t\t\tBIT(5)\n> +#define PGSR_DTIERR\t\t\tBIT(6)\n> +#define PGSR_DFTERR\t\t\tBIT(7)\n> +#define PGSR_RVERR\t\t\tBIT(8)\n> +#define PGSR_RVEIRR\t\t\tBIT(9)\n> +\n> +/* PTR0 */\n> +#define PRT_ITMSRST_SHIFT\t\t18\n> +#define PRT_DLLLOCK_SHIFT\t\t6\n> +#define PRT_DLLSRST_SHIFT\t\t0\n> +\n> +/* PTR1 */\n> +#define PRT_DINIT0_SHIFT\t\t0\n> +#define PRT_DINIT1_SHIFT\t\t19\n> +\n> +/* PTR2 */\n> +#define PRT_DINIT2_SHIFT\t\t0\n> +#define PRT_DINIT3_SHIFT\t\t17\n> +\n> +/* DCR */\n> +#define DDRMD_LPDDR\t\t\t0\n> +#define DDRMD_DDR\t\t\t1\n> +#define DDRMD_DDR2\t\t\t2\n> +#define DDRMD_DDR3\t\t\t3\n> +#define DDRMD_LPDDR2_LPDDR3\t\t4\n> +#define DDRMD_MASK\t\t\t7\n> +#define DDRMD_SHIFT\t\t\t0\n> +#define PDQ_MASK\t\t\t7\n> +#define PDQ_SHIFT\t\t\t4\n> +\n> +/* DXCCR */\n> +#define DQSNRES_MASK\t\t\t0xf\n> +#define DQSNRES_SHIFT\t\t\t8\n> +#define DQSRES_MASK\t\t\t0xf\n> +#define DQSRES_SHIFT\t\t\t4\n> +\n> +/* DTPR */\n> +#define TDQSCKMAX_SHIFT\t\t\t27\n> +#define TDQSCKMAX_MASK\t\t\t7\n> +#define TDQSCK_SHIFT\t\t\t24\n> +#define TDQSCK_MASK\t\t\t7\n> +\n> +/* DSGCR */\n> +#define DQSGX_SHIFT\t\t\t5\n> +#define DQSGX_MASK\t\t\t7\n> +#define DQSGE_SHIFT\t\t\t8\n> +#define DQSGE_MASK\t\t\t7\n> +\n> +/* SCTL */\n> +#define INIT_STATE\t\t\t0\n> +#define CFG_STATE\t\t\t1\n> +#define GO_STATE\t\t\t2\n> +#define SLEEP_STATE\t\t\t3\n> +#define WAKEUP_STATE\t\t\t4\n> +\n> +/* STAT */\n> +#define LP_TRIG_SHIFT\t\t\t4\n> +#define LP_TRIG_MASK\t\t\t7\n> +#define PCTL_STAT_MASK\t\t\t7\n> +#define INIT_MEM\t\t\t0\n> +#define CONFIG\t\t\t\t1\n> +#define CONFIG_REQ\t\t\t2\n> +#define ACCESS\t\t\t\t3\n> +#define ACCESS_REQ\t\t\t4\n> +#define LOW_POWER\t\t\t5\n> +#define LOW_POWER_ENTRY_REQ\t\t6\n> +#define LOW_POWER_EXIT_REQ\t\t7\n> +\n> +/* ZQCR*/\n> +#define PD_OUTPUT_SHIFT\t\t\t0\n> +#define PU_OUTPUT_SHIFT\t\t\t5\n> +#define PD_ONDIE_SHIFT\t\t\t10\n> +#define PU_ONDIE_SHIFT\t\t\t15\n> +#define ZDEN_SHIFT\t\t\t28\n> +\n> +/* DDLGCR */\n> +#define SBIAS_BYPASS\t\t\tBIT(23)\n> +\n> +/* MCFG */\n> +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT\t24\n> +#define PD_IDLE_SHIFT\t\t\t8\n> +#define MDDR_EN\t\t\t\t(2 << 22)\n> +#define LPDDR2_EN\t\t\t(3 << 22)\n> +#define LPDDR3_EN\t\t\t(1 << 22)\n> +#define DDR2_EN\t\t\t\t(0 << 5)\n> +#define DDR3_EN\t\t\t\t(1 << 5)\n> +#define LPDDR2_S2\t\t\t(0 << 6)\n> +#define LPDDR2_S4\t\t\t(1 << 6)\n> +#define MDDR_LPDDR2_BL_2\t\t(0 << 20)\n> +#define MDDR_LPDDR2_BL_4\t\t(1 << 20)\n> +#define MDDR_LPDDR2_BL_8\t\t(2 << 20)\n> +#define MDDR_LPDDR2_BL_16\t\t(3 << 20)\n> +#define DDR2_DDR3_BL_4\t\t\t0\n> +#define DDR2_DDR3_BL_8\t\t\t1\n> +#define TFAW_SHIFT\t\t\t18\n> +#define PD_EXIT_SLOW\t\t\t(0 << 17)\n> +#define PD_EXIT_FAST\t\t\t(1 << 17)\n> +#define PD_TYPE_SHIFT\t\t\t16\n> +#define BURSTLENGTH_SHIFT\t\t20\n> +\n> +/* POWCTL */\n> +#define POWER_UP_START\t\t\tBIT(0)\n> +\n> +/* POWSTAT */\n> +#define POWER_UP_DONE\t\t\tBIT(0)\n> +\n> +/* MCMD */\n> +enum {\n> +\tDESELECT_CMD\t\t\t= 0,\n> +\tPREA_CMD,\n> +\tREF_CMD,\n> +\tMRS_CMD,\n> +\tZQCS_CMD,\n> +\tZQCL_CMD,\n> +\tRSTL_CMD,\n> +\tMRR_CMD\t\t\t\t= 8,\n> +\tDPDE_CMD,\n> +};\n> +\n> +#define BANK_ADDR_MASK\t\t\t7\n> +#define BANK_ADDR_SHIFT\t\t\t17\n> +#define CMD_ADDR_MASK\t\t\t0x1fff\n> +#define CMD_ADDR_SHIFT\t\t\t4\n> +\n> +#define LPDDR23_MA_SHIFT\t\t4\n> +#define LPDDR23_MA_MASK\t\t\t0xff\n> +#define LPDDR23_OP_SHIFT\t\t12\n> +#define LPDDR23_OP_MASK\t\t\t0xff\n> +\n> +#define START_CMD\t\t\t(1u << 31)\n> +\n> +/* DDRPHY REG */\n> +enum {\n> +\t/* DDRPHY_REG0 */\n> +\tSOFT_RESET_MASK\t\t\t\t= 3,\n> +\tSOFT_DERESET_ANALOG\t\t\t= 1 << 2,\n> +\tSOFT_DERESET_DIGITAL\t\t\t= 1 << 3,\n> +\tSOFT_RESET_SHIFT\t\t\t= 2,\n> +\n> +\t/* DDRPHY REG1 */\n> +\tPHY_DDR3\t\t\t\t= 0,\n> +\tPHY_DDR2\t\t\t\t= 1,\n> +\tPHY_LPDDR3\t\t\t\t= 2,\n> +\tPHY_LPDDR2\t\t\t\t= 3,\n> +\n> +\tPHT_BL_8\t\t\t\t= 1 << 2,\n> +\tPHY_BL_4\t\t\t\t= 0 << 2,\n> +\n> +\t/* DDRPHY_REG2 */\n> +\tMEMORY_SELECT_DDR3\t\t\t= 0 << 0,\n> +\tMEMORY_SELECT_LPDDR3\t\t\t= 2 << 0,\n> +\tMEMORY_SELECT_LPDDR2\t\t\t= 3 << 0,\n> +\tDQS_SQU_CAL_SEL_CS0_CS1\t\t\t= 0 << 4,\n> +\tDQS_SQU_CAL_SEL_CS1\t\t\t= 1 << 4,\n> +\tDQS_SQU_CAL_SEL_CS0\t\t\t= 2 << 4,\n> +\tDQS_SQU_CAL_NORMAL_MODE\t\t\t= 0 << 1,\n> +\tDQS_SQU_CAL_BYPASS_MODE\t\t\t= 1 << 1,\n> +\tDQS_SQU_CAL_START\t\t\t= 1 << 0,\n> +\tDQS_SQU_NO_CAL\t\t\t\t= 0 << 0,\n> +};\n> +\n> +/* CK pull up/down driver strength control */\n> +enum {\n> +\tPHY_RON_RTT_DISABLE = 0,\n> +\tPHY_RON_RTT_451OHM = 1,\n> +\tPHY_RON_RTT_225OHM,\n> +\tPHY_RON_RTT_150OHM,\n> +\tPHY_RON_RTT_112OHM,\n> +\tPHY_RON_RTT_90OHM,\n> +\tPHY_RON_RTT_75OHM,\n> +\tPHY_RON_RTT_64OHM = 7,\n> +\n> +\tPHY_RON_RTT_56OHM = 16,\n> +\tPHY_RON_RTT_50OHM,\n> +\tPHY_RON_RTT_45OHM,\n> +\tPHY_RON_RTT_41OHM,\n> +\tPHY_RON_RTT_37OHM,\n> +\tPHY_RON_RTT_34OHM,\n> +\tPHY_RON_RTT_33OHM,\n> +\tPHY_RON_RTT_30OHM = 23,\n> +\n> +\tPHY_RON_RTT_28OHM = 24,\n> +\tPHY_RON_RTT_26OHM,\n> +\tPHY_RON_RTT_25OHM,\n> +\tPHY_RON_RTT_23OHM,\n> +\tPHY_RON_RTT_22OHM,\n> +\tPHY_RON_RTT_21OHM,\n> +\tPHY_RON_RTT_20OHM,\n> +\tPHY_RON_RTT_19OHM = 31,\n> +};\n> +\n> +/* DQS squelch DLL delay */\n> +enum {\n> +\tDQS_DLL_NO_DELAY\t= 0,\n> +\tDQS_DLL_22P5_DELAY,\n> +\tDQS_DLL_45_DELAY,\n> +\tDQS_DLL_67P5_DELAY,\n> +\tDQS_DLL_90_DELAY,\n> +\tDQS_DLL_112P5_DELAY,\n> +\tDQS_DLL_135_DELAY,\n> +\tDQS_DLL_157P5_DELAY,\n> +};\n> +\n> +/* GRF_SOC_CON0 */\n> +#define GRF_DDR_16BIT_EN\t\t(((0x1 << 0) << 16) | (0x1 << 0))\n> +#define GRF_DDR_32BIT_EN\t\t(((0x1 << 0) << 16) | (0x0 << 0))\n> +#define GRF_MSCH_NOC_16BIT_EN\t\t(((0x1 << 7) << 16) | (0x1 << 7))\n> +#define GRF_MSCH_NOC_32BIT_EN\t\t(((0x1 << 7) << 16) | (0x0 << 7))\n> +\n> +#define GRF_DDRPHY_BUFFEREN_CORE_EN\t(((0x1 << 8) << 16) | (0x0 << 8))\n> +#define GRF_DDRPHY_BUFFEREN_CORE_DIS\t(((0x1 << 8) << 16) | (0x1 << 8))\n> +\n> +#define GRF_DDR3_EN\t\t\t(((0x1 << 6) << 16) | (0x1 << 6))\n> +#define GRF_LPDDR2_3_EN\t\t\t(((0x1 << 6) << 16) | (0x0 << 6))\n> +\n> +#define PHY_DRV_ODT_SET(n)\t\t(((n) << 4) | (n))\n> +#define DDR3_DLL_RESET\t\t\t(1 << 8)\n> +\n> +#endif /* _ASM_ARCH_SDRAM_RK322X_H */\n> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile\n> index 6c78eff..45b5fe7 100644\n> --- a/drivers/ram/rockchip/Makefile\n> +++ b/drivers/ram/rockchip/Makefile\n> @@ -6,6 +6,7 @@\n> \n> obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o\n> obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o\n> +obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o\n> obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o\n> obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o\n> obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o\n> diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c\n> new file mode 100644\n> index 0000000..cc3138b\n> --- /dev/null\n> +++ b/drivers/ram/rockchip/sdram_rk322x.c\n> @@ -0,0 +1,855 @@\n> +/*\n> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n> + *\n> + * SPDX-License-Identifier:     GPL-2.0\n> + */\n> +#include <common.h>\n> +#include <clk.h>\n> +#include <dm.h>\n> +#include <dt-structs.h>\n> +#include <errno.h>\n> +#include <ram.h>\n> +#include <regmap.h>\n> +#include <syscon.h>\n> +#include <asm/io.h>\n> +#include <asm/arch/clock.h>\n> +#include <asm/arch/cru_rk322x.h>\n> +#include <asm/arch/grf_rk322x.h>\n> +#include <asm/arch/hardware.h>\n> +#include <asm/arch/sdram_rk322x.h>\n> +#include <asm/arch/timer.h>\n> +#include <asm/arch/uart.h>\n> +#include <asm/arch/sdram_common.h>\n> +#include <asm/types.h>\n> +#include <linux/err.h>\n> +\n> +DECLARE_GLOBAL_DATA_PTR;\n> +struct chan_info {\n> +\tstruct rk322x_ddr_pctl *pctl;\n> +\tstruct rk322x_ddr_phy *phy;\n> +\tstruct rk322x_service_sys *msch;\n> +};\n> +\n> +struct dram_info {\n> +\tstruct chan_info chan[1];\n> +\tstruct ram_info info;\n> +\tstruct clk ddr_clk;\n> +\tstruct rk322x_cru *cru;\n> +\tstruct rk322x_grf *grf;\n> +};\n> +\n> +struct rk322x_sdram_params {\n> +#if CONFIG_IS_ENABLED(OF_PLATDATA)\n> +\t\tstruct dtd_rockchip_rk3228_dmc of_plat;\n> +#endif\n> +\t\tstruct rk322x_sdram_channel ch[1];\n> +\t\tstruct rk322x_pctl_timing pctl_timing;\n> +\t\tstruct rk322x_phy_timing phy_timing;\n> +\t\tstruct rk322x_base_params base;\n> +\t\tint num_channels;\n> +\t\tstruct regmap *map;\n> +};\n> +\n> +#ifdef CONFIG_TPL_BUILD\n> +/*\n> + * [7:6]  bank(n:n bit bank)\n> + * [5:4]  row(13+n)\n> + * [3]    cs(0:1 cs, 1:2 cs)\n> + * [2:1]  bank(n:n bit bank)\n> + * [0]    col(10+n)\n> + */\n> +const char ddr_cfg_2_rbc[] = {\n> +\t((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1),\n> +\t((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1),\n> +\t((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1),\n> +\t((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1),\n> +\t((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2),\n> +\t((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2),\n> +\t((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2),\n> +\t((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0),\n> +\t((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0),\n> +\t((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0),\n> +\t((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0),\n> +\t((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1),\n> +\t((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2),\n> +\t((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1),\n> +\t((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1),\n> +\t((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0),\n> +};\n> +\n> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)\n> +{\n> +\tint i;\n> +\n> +\tfor (i = 0; i < n / sizeof(u32); i++) {\n> +\t\twritel(*src, dest);\n> +\t\tsrc++;\n> +\t\tdest++;\n> +\t}\n> +}\n> +\n> +void phy_pctrl_reset(struct rk322x_cru *cru,\n> +\t\t     struct rk322x_ddr_phy *ddr_phy)\n> +{\n> +\trk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |\n> +\t\t\t1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |\n> +\t\t\t1 << DDRPHY_SRST_SHIFT,\n> +\t\t\t1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |\n> +\t\t\t1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);\n> +\n> +\trockchip_udelay(10);\n> +\n> +\trk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |\n> +\t\t\t\t\t\t  1 << DDRPHY_SRST_SHIFT);\n> +\trockchip_udelay(10);\n> +\n> +\trk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |\n> +\t\t\t\t\t\t  1 << DDRCTRL_SRST_SHIFT);\n> +\trockchip_udelay(10);\n> +\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0],\n> +\t\t     SOFT_RESET_MASK << SOFT_RESET_SHIFT);\n> +\trockchip_udelay(10);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0],\n> +\t\t     SOFT_DERESET_ANALOG);\n> +\trockchip_udelay(5);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0],\n> +\t\t     SOFT_DERESET_DIGITAL);\n> +\n> +\trockchip_udelay(1);\n> +}\n> +\n> +void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)\n> +{\n> +\tu32 tmp;\n> +\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10);\n> +\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8);\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8);\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8);\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8);\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8);\n> +\n> +\tif (freq <= 400)\n> +\t\tsetbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);\n> +\telse\n> +\t\tclrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);\n> +\n> +\tif (freq <= 680)\n> +\t\ttmp = 3;\n> +\telse\n> +\t\ttmp = 2;\n> +\n> +\twritel(tmp, &ddr_phy->ddrphy_reg[0x28]);\n> +\twritel(tmp, &ddr_phy->ddrphy_reg[0x38]);\n> +\twritel(tmp, &ddr_phy->ddrphy_reg[0x48]);\n> +\twritel(tmp, &ddr_phy->ddrphy_reg[0x58]);\n> +}\n> +\n> +static void send_command(struct rk322x_ddr_pctl *pctl,\n> +\t\t\t u32 rank, u32 cmd, u32 arg)\n> +{\n> +\twritel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);\n> +\trockchip_udelay(1);\n> +\twhile (readl(&pctl->mcmd) & START_CMD)\n> +\t\t;\n> +}\n> +\n> +static void memory_init(struct chan_info *chan,\n> +\t\t\tstruct rk322x_sdram_params *sdram_params)\n> +{\n> +\tstruct rk322x_ddr_pctl *pctl = chan->pctl;\n> +\tu32 dramtype = sdram_params->base.dramtype;\n> +\n> +\tif (dramtype == DDR3) {\n> +\t\tsend_command(pctl, 3, DESELECT_CMD, 0);\n> +\t\trockchip_udelay(1);\n> +\t\tsend_command(pctl, 3, PREA_CMD, 0);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) <<\n> +\t\t\t     CMD_ADDR_SHIFT);\n> +\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) <<\n> +\t\t\t     CMD_ADDR_SHIFT);\n> +\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) <<\n> +\t\t\t     CMD_ADDR_SHIFT);\n> +\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |\n> +\t\t\t     ((sdram_params->phy_timing.mr[0] |\n> +\t\t\t       DDR3_DLL_RESET) &\n> +\t\t\t     CMD_ADDR_MASK) << CMD_ADDR_SHIFT);\n> +\n> +\t\tsend_command(pctl, 3, ZQCL_CMD, 0);\n> +\t} else {\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (0 & LPDDR23_OP_MASK) <<\n> +\t\t\t     LPDDR23_OP_SHIFT);\n> +\t\trockchip_udelay(10);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (0xff & LPDDR23_OP_MASK) <<\n> +\t\t\t     LPDDR23_OP_SHIFT);\n> +\t\trockchip_udelay(1);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (0xff & LPDDR23_OP_MASK) <<\n> +\t\t\t     LPDDR23_OP_SHIFT);\n> +\t\trockchip_udelay(1);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[1] &\n> +\t\t\t      LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[2] &\n> +\t\t\t      LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);\n> +\t\tsend_command(pctl, 3, MRS_CMD,\n> +\t\t\t     (3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |\n> +\t\t\t     (sdram_params->phy_timing.mr[3] &\n> +\t\t\t      LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);\n> +\t\tif (dramtype == LPDDR3)\n> +\t\t\tsend_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) <<\n> +\t\t\t\t     LPDDR23_MA_SHIFT |\n> +\t\t\t\t     (sdram_params->phy_timing.mr11 &\n> +\t\t\t\t      LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);\n> +\t}\n> +}\n> +\n> +static u32 data_training(struct chan_info *chan)\n> +{\n> +\tstruct rk322x_ddr_phy *ddr_phy = chan->phy;\n> +\tstruct rk322x_ddr_pctl *pctl = chan->pctl;\n> +\tu32 value;\n> +\tu32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf;\n> +\tu32 ret;\n> +\n> +\t/* disable auto refresh */\n> +\tvalue = readl(&pctl->trefi) | (1 << 31);\n> +\twritel(1 << 31, &pctl->trefi);\n> +\n> +\tclrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30,\n> +\t\t\tDQS_SQU_CAL_SEL_CS0);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);\n> +\n> +\trockchip_udelay(30);\n> +\tret = readl(&ddr_phy->ddrphy_reg[0xff]);\n> +\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[2],\n> +\t\t     DQS_SQU_CAL_START);\n> +\n> +\t/*\n> +\t * since data training will take about 20us, so send some auto\n> +\t * refresh(about 7.8us) to complement the lost time\n> +\t */\n> +\tsend_command(pctl, 3, PREA_CMD, 0);\n> +\tsend_command(pctl, 3, REF_CMD, 0);\n> +\n> +\twritel(value, &pctl->trefi);\n> +\n> +\tif (ret & 0x10) {\n> +\t\tret = -1;\n> +\t} else {\n> +\t\tret = (ret & 0xf) ^ bw;\n> +\t\tret = (ret == 0) ? 0 : -1;\n> +\t}\n> +\treturn ret;\n> +}\n> +\n> +static void move_to_config_state(struct rk322x_ddr_pctl *pctl)\n> +{\n> +\tunsigned int state;\n> +\n> +\twhile (1) {\n> +\t\tstate = readl(&pctl->stat) & PCTL_STAT_MASK;\n> +\t\tswitch (state) {\n> +\t\tcase LOW_POWER:\n> +\t\t\twritel(WAKEUP_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK)\n> +\t\t\t\t!= ACCESS)\n> +\t\t\t\t;\n> +\t\t\t/*\n> +\t\t\t * If at low power state, need wakeup first, and then\n> +\t\t\t * enter the config, so fallthrough\n> +\t\t\t */\n> +\t\tcase ACCESS:\n> +\t\t\t/* fallthrough */\n> +\t\tcase INIT_MEM:\n> +\t\t\twritel(CFG_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)\n> +\t\t\t\t;\n> +\t\t\tbreak;\n> +\t\tcase CONFIG:\n> +\t\t\treturn;\n> +\t\tdefault:\n> +\t\t\tbreak;\n> +\t\t}\n> +\t}\n> +}\n> +\n> +static void move_to_access_state(struct rk322x_ddr_pctl *pctl)\n> +{\n> +\tunsigned int state;\n> +\n> +\twhile (1) {\n> +\t\tstate = readl(&pctl->stat) & PCTL_STAT_MASK;\n> +\t\tswitch (state) {\n> +\t\tcase LOW_POWER:\n> +\t\t\twritel(WAKEUP_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)\n> +\t\t\t\t;\n> +\t\t\tbreak;\n> +\t\tcase INIT_MEM:\n> +\t\t\twritel(CFG_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)\n> +\t\t\t\t;\n> +\t\t\t/* fallthrough */\n> +\t\tcase CONFIG:\n> +\t\t\twritel(GO_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)\n> +\t\t\t\t;\n> +\t\t\tbreak;\n> +\t\tcase ACCESS:\n> +\t\t\treturn;\n> +\t\tdefault:\n> +\t\t\tbreak;\n> +\t\t}\n> +\t}\n> +}\n> +\n> +static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl)\n> +{\n> +\tunsigned int state;\n> +\n> +\twhile (1) {\n> +\t\tstate = readl(&pctl->stat) & PCTL_STAT_MASK;\n> +\t\tswitch (state) {\n> +\t\tcase INIT_MEM:\n> +\t\t\twritel(CFG_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)\n> +\t\t\t\t;\n> +\t\t\t/* fallthrough */\n> +\t\tcase CONFIG:\n> +\t\t\twritel(GO_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)\n> +\t\t\t\t;\n> +\t\t\tbreak;\n> +\t\tcase ACCESS:\n> +\t\t\twritel(SLEEP_STATE, &pctl->sctl);\n> +\t\t\twhile ((readl(&pctl->stat) & PCTL_STAT_MASK) !=\n> +\t\t\t       LOW_POWER)\n> +\t\t\t\t;\n> +\t\t\tbreak;\n> +\t\tcase LOW_POWER:\n> +\t\t\treturn;\n> +\t\tdefault:\n> +\t\t\tbreak;\n> +\t\t}\n> +\t}\n> +}\n> +\n> +/* pctl should in low power mode when call this function */\n> +static void phy_softreset(struct dram_info *dram)\n> +{\n> +\tstruct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;\n> +\tstruct rk322x_grf *grf = dram->grf;\n> +\n> +\twritel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]);\n> +\tclrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);\n> +\trockchip_udelay(1);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);\n> +\trockchip_udelay(5);\n> +\tsetbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);\n> +\twritel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]);\n> +}\n> +\n> +/* bw: 2: 32bit, 1:16bit */\n> +static void set_bw(struct dram_info *dram, u32 bw)\n> +{\n> +\tstruct rk322x_ddr_pctl *pctl = dram->chan[0].pctl;\n> +\tstruct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;\n> +\tstruct rk322x_grf *grf = dram->grf;\n> +\n> +\tif (bw == 1) {\n> +\t\tsetbits_le32(&pctl->ppcfg, 1);\n> +\t\tclrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4);\n> +\t\twritel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]);\n> +\t\tclrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);\n> +\t\tclrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);\n> +\t} else {\n> +\t\tclrbits_le32(&pctl->ppcfg, 1);\n> +\t\tsetbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4);\n> +\t\twritel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN,\n> +\t\t       &grf->soc_con[0]);\n> +\t\tsetbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);\n> +\t\tsetbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);\n> +\t}\n> +}\n> +\n> +static void pctl_cfg(struct rk322x_ddr_pctl *pctl,\n> +\t\t     struct rk322x_sdram_params *sdram_params,\n> +\t\t     struct rk322x_grf *grf)\n> +{\n> +\tu32 burst_len;\n> +\tu32 bw;\n> +\tu32 dramtype = sdram_params->base.dramtype;\n> +\n> +\tif (sdram_params->ch[0].bw == 2)\n> +\t\tbw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN;\n> +\telse\n> +\t\tbw = GRF_MSCH_NOC_16BIT_EN;\n> +\n> +\twritel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);\n> +\twritel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);\n> +\twritel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);\n> +\twritel(0x51010, &pctl->dfilpcfg0);\n> +\n> +\twritel(1, &pctl->dfitphyupdtype0);\n> +\twritel(0x0d, &pctl->dfitphyrdlat);\n> +\twritel(0, &pctl->dfitphywrdata);\n> +\n> +\twritel(0, &pctl->dfiupdcfg);\n> +\tcopy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,\n> +\t\t    sizeof(struct rk322x_pctl_timing));\n> +\tif (dramtype == DDR3) {\n> +\t\twritel((1 << 3) | (1 << 11),\n> +\t\t       &pctl->dfiodtcfg);\n> +\t\twritel(7 << 16, &pctl->dfiodtcfg1);\n> +\t\twritel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen);\n> +\t\twritel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat);\n> +\t\twritel(500, &pctl->trsth);\n> +\t\twritel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |\n> +\t\t       DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |\n> +\t\t       1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,\n> +\t\t       &pctl->mcfg);\n> +\t\twritel(bw | GRF_DDR3_EN, &grf->soc_con[0]);\n> +\t} else {\n> +\t\tif (sdram_params->phy_timing.bl & PHT_BL_8)\n> +\t\t\tburst_len = MDDR_LPDDR2_BL_8;\n> +\t\telse\n> +\t\t\tburst_len = MDDR_LPDDR2_BL_4;\n> +\n> +\t\twritel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen);\n> +\t\twritel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat);\n> +\t\twritel(0, &pctl->trsth);\n> +\t\tif (dramtype == LPDDR2) {\n> +\t\t\twritel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |\n> +\t\t\t       LPDDR2_S4 | LPDDR2_EN | burst_len |\n> +\t\t\t       (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |\n> +\t\t\t       1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,\n> +\t\t\t       &pctl->mcfg);\n> +\t\t\twritel(0, &pctl->dfiodtcfg);\n> +\t\t\twritel(0, &pctl->dfiodtcfg1);\n> +\t\t} else {\n> +\t\t\twritel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |\n> +\t\t\t       LPDDR2_S4 | LPDDR3_EN | burst_len |\n> +\t\t\t       (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |\n> +\t\t\t       1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,\n> +\t\t\t       &pctl->mcfg);\n> +\t\t\twritel((1 << 3) | (1 << 2), &pctl->dfiodtcfg);\n> +\t\t\twritel((7 << 16) | 4, &pctl->dfiodtcfg1);\n> +\t\t}\n> +\t\twritel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]);\n> +\t}\n> +\tsetbits_le32(&pctl->scfg, 1);\n> +}\n> +\n> +static void phy_cfg(struct chan_info *chan,\n> +\t\t    struct rk322x_sdram_params *sdram_params)\n> +{\n> +\tstruct rk322x_ddr_phy *ddr_phy = chan->phy;\n> +\tstruct rk322x_service_sys *axi_bus = chan->msch;\n> +\tstruct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing;\n> +\tstruct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing;\n> +\tstruct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing;\n> +\tu32 cmd_drv, clk_drv, dqs_drv, dqs_odt;\n> +\n> +\twritel(noc_timing->ddrtiming, &axi_bus->ddrtiming);\n> +\twritel(noc_timing->ddrmode, &axi_bus->ddrmode);\n> +\twritel(noc_timing->readlatency, &axi_bus->readlatency);\n> +\twritel(noc_timing->activate, &axi_bus->activate);\n> +\twritel(noc_timing->devtodev, &axi_bus->devtodev);\n> +\n> +\tswitch (sdram_params->base.dramtype) {\n> +\tcase DDR3:\n> +\t\twritel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);\n> +\t\tbreak;\n> +\tcase LPDDR2:\n> +\t\twritel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);\n> +\t\tbreak;\n> +\tdefault:\n> +\t\twritel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);\n> +\t\tbreak;\n> +\t}\n> +\n> +\twritel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]);\n> +\twritel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]);\n> +\n> +\tcmd_drv = PHY_RON_RTT_34OHM;\n> +\tclk_drv = PHY_RON_RTT_45OHM;\n> +\tdqs_drv = PHY_RON_RTT_34OHM;\n> +\tif (sdram_params->base.dramtype == LPDDR2)\n> +\t\tdqs_odt = PHY_RON_RTT_DISABLE;\n> +\telse\n> +\t\tdqs_odt = PHY_RON_RTT_225OHM;\n> +\n> +\twritel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]);\n> +\tclrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3);\n> +\twritel(clk_drv, &ddr_phy->ddrphy_reg[0x16]);\n> +\twritel(clk_drv, &ddr_phy->ddrphy_reg[0x18]);\n> +\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]);\n> +\twritel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]);\n> +\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]);\n> +\twritel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]);\n> +}\n> +\n> +void dram_cfg_rbc(struct chan_info *chan,\n> +\t\t  struct rk322x_sdram_params *sdram_params)\n> +{\n> +\tchar noc_config;\n> +\tint i = 0;\n> +\tstruct rk322x_sdram_channel *config = &sdram_params->ch[0];\n> +\tstruct rk322x_service_sys *axi_bus = chan->msch;\n> +\n> +\tmove_to_config_state(chan->pctl);\n> +\n> +\tif ((config->rank == 2) && (config->cs1_row == config->cs0_row)) {\n> +\t\tif ((config->col + config->bw) == 12) {\n> +\t\t\ti = 14;\n> +\t\t\tgoto finish;\n> +\t\t} else if ((config->col + config->bw) == 11) {\n> +\t\t\ti = 15;\n> +\t\t\tgoto finish;\n> +\t\t}\n> +\t}\n> +\tnoc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) |\n> +\t\t\t\t(config->col + config->bw - 11);\n> +\tfor (i = 0; i < 11; i++) {\n> +\t\tif (noc_config == ddr_cfg_2_rbc[i])\n> +\t\t\tbreak;\n> +\t}\n> +\n> +\tif (i < 11)\n> +\t\tgoto finish;\n> +\n> +\tnoc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) |\n> +\t\t\t\t(config->col + config->bw - 11);\n> +\n> +\tfor (i = 11; i < 14; i++) {\n> +\t\tif (noc_config == ddr_cfg_2_rbc[i])\n> +\t\t\tbreak;\n> +\t}\n> +\tif (i < 14)\n> +\t\tgoto finish;\n> +\telse\n> +\t\ti = 0;\n> +\n> +finish:\n> +\twritel(i, &axi_bus->ddrconf);\n> +\tmove_to_access_state(chan->pctl);\n> +}\n> +\n> +static void dram_all_config(const struct dram_info *dram,\n> +\t\t\t    struct rk322x_sdram_params *sdram_params)\n> +{\n> +\tstruct rk322x_sdram_channel *info = &sdram_params->ch[0];\n> +\tu32 sys_reg = 0;\n> +\n> +\tsys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;\n> +\tsys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT;\n> +\tsys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0);\n> +\tsys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0);\n> +\tsys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0);\n> +\tsys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0);\n> +\tsys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0);\n> +\tsys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0);\n> +\tsys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0);\n> +\tsys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0);\n> +\tsys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0);\n> +\n> +\twritel(sys_reg, &dram->grf->os_reg[2]);\n> +}\n> +\n> +#define TEST_PATTEN\t0x5aa5f00f\n> +\n> +static int dram_cap_detect(struct dram_info *dram,\n> +\t\t\t   struct rk322x_sdram_params *sdram_params)\n> +{\n> +\tu32 bw, row, col, addr;\n> +\tu32 ret = 0;\n> +\tstruct rk322x_service_sys *axi_bus = dram->chan[0].msch;\n> +\n> +\tif (sdram_params->base.dramtype == DDR3)\n> +\t\tsdram_params->ch[0].dbw = 1;\n> +\telse\n> +\t\tsdram_params->ch[0].dbw = 2;\n> +\n> +\tmove_to_config_state(dram->chan[0].pctl);\n> +\t/* bw detect */\n> +\tset_bw(dram, 2);\n> +\tif (data_training(&dram->chan[0]) == 0) {\n> +\t\tbw = 2;\n> +\t} else {\n> +\t\tbw = 1;\n> +\t\tset_bw(dram, 1);\n> +\t\tmove_to_lowpower_state(dram->chan[0].pctl);\n> +\t\tphy_softreset(dram);\n> +\t\tmove_to_config_state(dram->chan[0].pctl);\n> +\t\tif (data_training(&dram->chan[0])) {\n> +\t\t\tprintf(\"BW detect error\\n\");\n> +\t\t\tret = -EINVAL;\n> +\t\t}\n> +\t}\n> +\tsdram_params->ch[0].bw = bw;\n> +\tsdram_params->ch[0].bk = 3;\n> +\n> +\tif (bw == 2)\n> +\t\twritel(6, &axi_bus->ddrconf);\n> +\telse\n> +\t\twritel(3, &axi_bus->ddrconf);\n> +\tmove_to_access_state(dram->chan[0].pctl);\n> +\tfor (col = 11; col >= 9; col--) {\n> +\t\twritel(0, CONFIG_SYS_SDRAM_BASE);\n> +\t\taddr = CONFIG_SYS_SDRAM_BASE +\n> +\t\t\t(1 << (col + bw - 1));\n> +\t\twritel(TEST_PATTEN, addr);\n> +\t\tif ((readl(addr) == TEST_PATTEN) &&\n> +\t\t    (readl(CONFIG_SYS_SDRAM_BASE) == 0))\n> +\t\t\tbreak;\n> +\t}\n> +\tif (col == 8) {\n> +\t\tprintf(\"Col detect error\\n\");\n> +\t\tret = -EINVAL;\n> +\t\tgoto out;\n> +\t} else {\n> +\t\tsdram_params->ch[0].col = col;\n> +\t}\n> +\n> +\twritel(10, &axi_bus->ddrconf);\n> +\n> +\t/* Detect row*/\n> +\tfor (row = 16; row >= 12; row--) {\n> +\t\twritel(0, CONFIG_SYS_SDRAM_BASE);\n> +\t\taddr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));\n> +\t\twritel(TEST_PATTEN, addr);\n> +\t\tif ((readl(addr) == TEST_PATTEN) &&\n> +\t\t    (readl(CONFIG_SYS_SDRAM_BASE) == 0))\n> +\t\t\tbreak;\n> +\t}\n> +\tif (row == 11) {\n> +\t\tprintf(\"Row detect error\\n\");\n> +\t\tret = -EINVAL;\n> +\t} else {\n> +\t\tsdram_params->ch[0].cs1_row = row;\n> +\t\tsdram_params->ch[0].row_3_4 = 0;\n> +\t\tsdram_params->ch[0].cs0_row = row;\n> +\t}\n> +\t/* cs detect */\n> +\twritel(0, CONFIG_SYS_SDRAM_BASE);\n> +\twritel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));\n> +\twritel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);\n> +\tif ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&\n> +\t    (readl(CONFIG_SYS_SDRAM_BASE) == 0))\n> +\t\tsdram_params->ch[0].rank = 2;\n> +\telse\n> +\t\tsdram_params->ch[0].rank = 1;\n> +out:\n> +\treturn ret;\n> +}\n> +\n> +static int sdram_init(struct dram_info *dram,\n> +\t\t      struct rk322x_sdram_params *sdram_params)\n> +{\n> +\tint ret;\n> +\n> +\tret = clk_set_rate(&dram->ddr_clk,\n> +\t\t\t   sdram_params->base.ddr_freq * MHz * 2);\n> +\tif (ret < 0) {\n> +\t\tprintf(\"Could not set DDR clock\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n> +\tphy_pctrl_reset(dram->cru, dram->chan[0].phy);\n> +\tphy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq);\n> +\tpctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf);\n> +\tphy_cfg(&dram->chan[0], sdram_params);\n> +\twritel(POWER_UP_START, &dram->chan[0].pctl->powctl);\n> +\twhile (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE))\n> +\t\t;\n> +\tmemory_init(&dram->chan[0], sdram_params);\n> +\tmove_to_access_state(dram->chan[0].pctl);\n> +\tret = dram_cap_detect(dram, sdram_params);\n> +\tif (ret)\n> +\t\tgoto out;\n> +\tdram_cfg_rbc(&dram->chan[0], sdram_params);\n> +\tdram_all_config(dram, sdram_params);\n> +out:\n> +\treturn ret;\n> +}\n> +\n> +static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev)\n> +{\n> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)\n> +\tstruct rk322x_sdram_params *params = dev_get_platdata(dev);\n> +\tconst void *blob = gd->fdt_blob;\n> +\tint node = dev_of_offset(dev);\n> +\tint ret;\n> +\n> +\tparams->num_channels = 1;\n> +\n> +\tret = fdtdec_get_int_array(blob, node, \"rockchip,pctl-timing\",\n> +\t\t\t\t   (u32 *)&params->pctl_timing,\n> +\t\t\t\t   sizeof(params->pctl_timing) / sizeof(u32));\n> +\tif (ret) {\n> +\t\tprintf(\"%s: Cannot read rockchip,pctl-timing\\n\", __func__);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\tret = fdtdec_get_int_array(blob, node, \"rockchip,phy-timing\",\n> +\t\t\t\t   (u32 *)&params->phy_timing,\n> +\t\t\t\t   sizeof(params->phy_timing) / sizeof(u32));\n> +\tif (ret) {\n> +\t\tprintf(\"%s: Cannot read rockchip,phy-timing\\n\", __func__);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\tret = fdtdec_get_int_array(blob, node, \"rockchip,sdram-params\",\n> +\t\t\t\t   (u32 *)&params->base,\n> +\t\t\t\t   sizeof(params->base) / sizeof(u32));\n> +\tif (ret) {\n> +\t\tprintf(\"%s: Cannot read rockchip,sdram-params\\n\", __func__);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\tret = regmap_init_mem(dev, &params->map);\n> +\tif (ret)\n> +\t\treturn ret;\n> +#endif\n> +\n> +\treturn 0;\n> +}\n> +#endif /* CONFIG_TPL_BUILD */\n> +\n> +#if CONFIG_IS_ENABLED(OF_PLATDATA)\n> +static int conv_of_platdata(struct udevice *dev)\n> +{\n> +\tstruct rk322x_sdram_params *plat = dev_get_platdata(dev);\n> +\tstruct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat;\n> +\tint ret;\n> +\n> +\tmemcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,\n> +\t       sizeof(plat->pctl_timing));\n> +\tmemcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,\n> +\t       sizeof(plat->phy_timing));\n> +\tmemcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));\n> +\n> +\tplat->num_channels = 1;\n> +\tret = regmap_init_mem_platdata(dev, of_plat->reg,\n> +\t\t\t\t       ARRAY_SIZE(of_plat->reg) / 2,\n> +\t\t\t\t       &plat->map);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\treturn 0;\n> +}\n> +#endif\n> +\n> +static int rk322x_dmc_probe(struct udevice *dev)\n> +{\n> +#ifdef CONFIG_TPL_BUILD\n> +\tstruct rk322x_sdram_params *plat = dev_get_platdata(dev);\n> +\tint ret;\n> +\tstruct udevice *dev_clk;\n> +#endif\n> +\tstruct dram_info *priv = dev_get_priv(dev);\n> +\n> +\tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> +#ifdef CONFIG_TPL_BUILD\n> +#if CONFIG_IS_ENABLED(OF_PLATDATA)\n> +\tret = conv_of_platdata(dev);\n> +\tif (ret)\n> +\t\treturn ret;\n> +#endif\n> +\n> +\tpriv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);\n> +\tpriv->chan[0].pctl = regmap_get_range(plat->map, 0);\n> +\tpriv->chan[0].phy = regmap_get_range(plat->map, 1);\n> +\tret = rockchip_get_clk(&dev_clk);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\tpriv->ddr_clk.id = CLK_DDR;\n> +\tret = clk_request(dev_clk, &priv->ddr_clk);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tpriv->cru = rockchip_get_cru();\n> +\tif (IS_ERR(priv->cru))\n> +\t\treturn PTR_ERR(priv->cru);\n> +\tret = sdram_init(priv, plat);\n> +\tif (ret)\n> +\t\treturn ret;\n> +#else\n> +\tpriv->info.base = CONFIG_SYS_SDRAM_BASE;\n> +\tpriv->info.size = rockchip_sdram_size(\n> +\t\t\t(phys_addr_t)&priv->grf->os_reg[2]);\n> +#endif\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info)\n> +{\n> +\tstruct dram_info *priv = dev_get_priv(dev);\n> +\n> +\t*info = priv->info;\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct ram_ops rk322x_dmc_ops = {\n> +\t.get_info = rk322x_dmc_get_info,\n> +};\n> +\n> +static const struct udevice_id rk322x_dmc_ids[] = {\n> +\t{ .compatible = \"rockchip,rk3228-dmc\" },\n> +\t{ }\n> +};\n> +\n> +U_BOOT_DRIVER(dmc_rk322x) = {\n> +\t.name = \"rockchip_rk322x_dmc\",\n> +\t.id = UCLASS_RAM,\n> +\t.of_match = rk322x_dmc_ids,\n> +\t.ops = &rk322x_dmc_ops,\n> +#ifdef CONFIG_TPL_BUILD\n> +\t.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,\n> +#endif\n> +\t.probe = rk322x_dmc_probe,\n> +\t.priv_auto_alloc_size = sizeof(struct dram_info),\n> +#ifdef CONFIG_TPL_BUILD\n> +\t.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),\n> +#endif\n> +};\n> +\n> -- \n> 1.9.1\n>","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2BqQ2MPGz9tXg\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 19:10:10 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid F405EC21E14; Wed, 27 Sep 2017 09:10:08 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4DF98C21D76;\n\tWed, 27 Sep 2017 08:47:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 1C7EFC21D5D; Wed, 27 Sep 2017 08:47:43 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 43D96C21E08\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 08:46:22 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:59430\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from <philipp.tomsich@theobroma-systems.com>)\n\tid 1dx7z3-0007p8-0v; Wed, 27 Sep 2017 10:46:21 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" <philipp.tomsich@theobroma-systems.com>","In-Reply-To":"<1506501503-364-2-git-send-email-kever.yang@rock-chips.com>","Date":"Wed, 27 Sep 2017 10:46:20 +0200","Message-Id":"<8F91DDED-60B9-4C6E-9DEA-5A66C018DEC0@theobroma-systems.com>","References":"<1506501503-364-1-git-send-email-kever.yang@rock-chips.com>\n\t<1506501503-364-2-git-send-email-kever.yang@rock-chips.com>","To":"Kever Yang <kever.yang@rock-chips.com>","X-Mailer":"Apple Mail (2.3273)","Cc":"U-Boot Mailing List <u-boot@lists.denx.de>","Subject":"Re: [U-Boot] [PATCH v4 1/2] rockchip: rk322x: add sdram driver","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion <u-boot.lists.denx.de>","List-Unsubscribe":"<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>","List-Archive":"<http://lists.denx.de/pipermail/u-boot/>","List-Post":"<mailto:u-boot@lists.denx.de>","List-Help":"<mailto:u-boot-request@lists.denx.de?subject=help>","List-Subscribe":"<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" <u-boot-bounces@lists.denx.de>"}},{"id":1776268,"web_url":"http://patchwork.ozlabs.org/comment/1776268/","msgid":"<E1dxAbT-000481-6f@mail.theobroma-systems.com>","list_archive_url":null,"date":"2017-09-27T11:34:11","subject":"Re: [U-Boot] [U-Boot,v4,1/2] rockchip: rk322x: add sdram driver","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> Add driver for rk322x to support sdram initialize in SPL.\n> \n> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>\n> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n> ---\n> \n> Changes in v4:\n> - rebase on u-boot-rockchip master with patchset \"move rockchip sdram\n>   driver to driver/ram\"\n> \n> Changes in v3:\n> - move rk332x sdram driver to driver/ram\n> - do the ram init in TPL instad of SPL\n> \n>  arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++++++++++++++\n>  drivers/ram/rockchip/Makefile                     |   1 +\n>  drivers/ram/rockchip/sdram_rk322x.c               | 855 ++++++++++++++++++++++\n>  3 files changed, 1437 insertions(+)\n>  create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h\n>  create mode 100644 drivers/ram/rockchip/sdram_rk322x.c\n> \n\nApplied to u-boot-rockchip, thanks!","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2G506H0Dz9tXF\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 21:37:08 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9C810C21E3E; Wed, 27 Sep 2017 11:35:16 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CAF11C21E6F;\n\tWed, 27 Sep 2017 11:34:15 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 3EAF1C21DA3; Wed, 27 Sep 2017 11:34:12 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id E3375C21CB1\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 11:34:11 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:61706\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from <philipp.tomsich@theobroma-systems.com>)\n\tid 1dxAbT-000481-6f; Wed, 27 Sep 2017 13:34:11 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich <philipp.tomsich@theobroma-systems.com>","To":"Kever Yang <kever.yang@rock-chips.com>","In-Reply-To":"<1506501503-364-2-git-send-email-kever.yang@rock-chips.com>","References":"<1506501503-364-2-git-send-email-kever.yang@rock-chips.com>","Message-Id":"<E1dxAbT-000481-6f@mail.theobroma-systems.com>","Date":"Wed, 27 Sep 2017 13:34:11 +0200","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] [U-Boot,v4,1/2] rockchip: rk322x: add sdram driver","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion <u-boot.lists.denx.de>","List-Unsubscribe":"<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>","List-Archive":"<http://lists.denx.de/pipermail/u-boot/>","List-Post":"<mailto:u-boot@lists.denx.de>","List-Help":"<mailto:u-boot-request@lists.denx.de?subject=help>","List-Subscribe":"<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>","Content-Type":"text/plain; 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