[{"id":1776205,"web_url":"http://patchwork.ozlabs.org/comment/1776205/","msgid":"<20170927101508.z3u32gff7kqgnmr2@flea>","list_archive_url":null,"date":"2017-09-27T10:15:08","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Wed, Sep 27, 2017 at 07:34:08AM +0000, Corentin Labbe wrote:\n> This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> for integrated PHY.\n> \n> Signed-off-by: Corentin Labbe \n\nThis should be squashed with patch 1.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2DGg089Sz9tXC\n\tfor ;\n\tWed, 27 Sep 2017 20:15:22 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752114AbdI0KPV (ORCPT\n\t);\n\tWed, 27 Sep 2017 06:15:21 -0400","from mail.free-electrons.com ([62.4.15.54]:58037 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751808AbdI0KPU (ORCPT\n\t); Wed, 27 Sep 2017 06:15:20 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 096A42089D; Wed, 27 Sep 2017 12:15:18 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D9DED20898;\n\tWed, 27 Sep 2017 12:15:07 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Wed, 27 Sep 2017 12:15:08 +0200","From":"Maxime Ripard ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170927101508.z3u32gff7kqgnmr2@flea>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ghm4jv4fei6qquqw\"","Content-Disposition":"inline","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776379,"web_url":"http://patchwork.ozlabs.org/comment/1776379/","msgid":"<20170927140210.GE13516@lunn.ch>","list_archive_url":null,"date":"2017-09-27T14:02:10","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"Hi Corentin\n\n> +Required properties for the mdio-mux node:\n> + - compatible = \"mdio-mux\"\n\nThis is too generic. Please add a more specific compatible for this\nparticular mux. You can keep \"mdio-mux\", since that is what the MDIO\nsubsystem will look for.\n\n> +Required properties of the integrated phy node:\n> - clocks: a phandle to the reference clock for the EPHY\n> - resets: a phandle to the reset control for the EPHY\n> +- phy-is-integrated\n\nSo the last thing you said is that the mux is not the problem\nhere. Something else is locking up. Did you discover what?\n\nI really would like phy-is-integrated to go away.\n\n Andrew\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2KJh0LLTz9tY0\n\tfor ;\n\tThu, 28 Sep 2017 00:02:28 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753141AbdI0OC0 (ORCPT\n\t);\n\tWed, 27 Sep 2017 10:02:26 -0400","from vps0.lunn.ch ([185.16.172.187]:58154 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753035AbdI0OCZ (ORCPT );\n\tWed, 27 Sep 2017 10:02:25 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dxCug-0002aa-AQ; Wed, 27 Sep 2017 16:02:10 +0200"],"Date":"Wed, 27 Sep 2017 16:02:10 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170927140210.GE13516@lunn.ch>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776765,"web_url":"http://patchwork.ozlabs.org/comment/1776765/","msgid":"<25e44368-2c07-9b7e-a0d3-a2a642286e5d@gmail.com>","list_archive_url":null,"date":"2017-09-28T04:53:15","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/people/2800/","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"content":"On 09/27/2017 12:34 AM, Corentin Labbe wrote:\n> This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> for integrated PHY.\n> \n> Signed-off-by: Corentin Labbe \n> ---\n> .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++--\n> 1 file changed, 126 insertions(+), 12 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> index 725f3b187886..e2ef4683df08 100644\n> --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.\n> Please see stmmac.txt for the other unchanged properties.\n> \n> Required properties:\n> -- compatible: should be one of the following string:\n> +- compatible: must be one of the following string:\n> \t\t\"allwinner,sun8i-a83t-emac\"\n> \t\t\"allwinner,sun8i-h3-emac\"\n> \t\t\"allwinner,sun8i-v3s-emac\"\n> \t\t\"allwinner,sun50i-a64-emac\"\n> - reg: address and length of the register for the device.\n> - interrupts: interrupt for the device\n> -- interrupt-names: should be \"macirq\"\n> +- interrupt-names: must be \"macirq\"\n> - clocks: A phandle to the reference clock for this device\n> -- clock-names: should be \"stmmaceth\"\n> +- clock-names: must be \"stmmaceth\"\n> - resets: A phandle to the reset control for this device\n> -- reset-names: should be \"stmmaceth\"\n> +- reset-names: must be \"stmmaceth\"\n> - phy-mode: See ethernet.txt\n> - phy-handle: See ethernet.txt\n> - #address-cells: shall be 1\n> @@ -39,23 +39,38 @@ Optional properties for the following compatibles:\n> - allwinner,leds-active-low: EPHY LEDs are active low\n> \n> Required child node of emac:\n> -- mdio bus node: should be named mdio\n> +- mdio bus node: with compatible \"snps,dwmac-mdio\"\n> \n> Required properties of the mdio node:\n> - #address-cells: shall be 1\n> - #size-cells: shall be 0\n> \n> -The device node referenced by \"phy\" or \"phy-handle\" should be a child node\n> +The device node referenced by \"phy\" or \"phy-handle\" must be a child node\n> of the mdio node. See phy.txt for the generic PHY bindings.\n> \n> -Required properties of the phy node with the following compatibles:\n> +The following compatibles require that the mdio node have a mdio-mux child\n> +node called \"mdio-mux\":\n> + - \"allwinner,sun8i-h3-emac\"\n> + - \"allwinner,sun8i-v3s-emac\":\n> +Required properties for the mdio-mux node:\n> + - compatible = \"mdio-mux\"\n> + - one child mdio for the integrated mdio\n> + - one child mdio for the external mdio if present (V3s have none)\n> +Required properties for the mdio-mux children node:\n> + - reg: 1 for internal MDIO bus, 2 for external MDIO bus\n> +\n> +The following compatibles require a PHY node representing the integrated\n> +PHY, under the integrated MDIO bus node if an mdio-mux node is used:\n> - \"allwinner,sun8i-h3-emac\",\n> - \"allwinner,sun8i-v3s-emac\":\n> +\n> +Required properties of the integrated phy node:\n> - clocks: a phandle to the reference clock for the EPHY\n> - resets: a phandle to the reset control for the EPHY\n> +- phy-is-integrated\n> +- Must be a child of the integrated mdio\n> \n> -Example:\n> -\n> +Example with integrated PHY:\n> emac: ethernet@1c0b000 {\n> \tcompatible = \"allwinner,sun8i-h3-emac\";\n> \tsyscon = <&syscon>;\n> @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {\n> \tphy-handle = <&int_mii_phy>;\n> \tphy-mode = \"mii\";\n> \tallwinner,leds-active-low;\n> +\n> +\tmdio0: mdio {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> +\n> +\t\tmdio-mux {\n> +\t\t\tcompatible = \"mdio-mux\";\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n\nSorry for chiming in so late, but why don't we have the mdio-mux be the\nroot node here in the mdio bus hierarchy? I understand that with this\nbinding proposed here, we need to have patch 11 included (which btw,\nshould come before any DTS change), but this does not seem to accurately\nmodel the HW.\n\nThe mux itself is not a child node of the MDIO bus controller, it does\nnot really belong in that address space although it does mangle the MDIO\nbus controller address space between the two ends of the mux.\n\nIf this has been debated before, apologies for missing that part of the\ndiscussion.\n\n> +\n> +\t\t\tint_mdio: mdio@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> +\t\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> +\t\t\t\t\tphy-is-integrated;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t\text_mdio: mdio@2 {\n> +\t\t\t\treg = <2>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +};\n> +\n> +Example with external PHY:\n> +emac: ethernet@1c0b000 {\n> +\tcompatible = \"allwinner,sun8i-h3-emac\";\n> +\tsyscon = <&syscon>;\n> +\treg = <0x01c0b000 0x104>;\n> +\tinterrupts = ;\n> +\tinterrupt-names = \"macirq\";\n> +\tresets = <&ccu RST_BUS_EMAC>;\n> +\treset-names = \"stmmaceth\";\n> +\tclocks = <&ccu CLK_BUS_EMAC>;\n> +\tclock-names = \"stmmaceth\";\n> +\t#address-cells = <1>;\n> +\t#size-cells = <0>;\n> +\n> +\tphy-handle = <&ext_rgmii_phy>;\n> +\tphy-mode = \"rgmii\";\n> +\tallwinner,leds-active-low;\n> +\n> +\tmdio0: mdio {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> +\n> +\t\tmdio-mux {\n> +\t\t\tcompatible = \"mdio-mux\";\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tint_mdio: mdio@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> +\t\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> +\t\t\t\t\tphy-is-integrated;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t\text_mdio: mdio@2 {\n> +\t\t\t\treg = <2>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\text_rgmii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t};\n> +\t\t\t}:\n> +\t\t};\n> +\t};\n> +};\n> +\n> +Example with SoC without integrated PHY\n> +\n> +emac: ethernet@1c0b000 {\n> +\tcompatible = \"allwinner,sun8i-a83t-emac\";\n> +\tsyscon = <&syscon>;\n> +\treg = <0x01c0b000 0x104>;\n> +\tinterrupts = ;\n> +\tinterrupt-names = \"macirq\";\n> +\tresets = <&ccu RST_BUS_EMAC>;\n> +\treset-names = \"stmmaceth\";\n> +\tclocks = <&ccu CLK_BUS_EMAC>;\n> +\tclock-names = \"stmmaceth\";\n> +\t#address-cells = <1>;\n> +\t#size-cells = <0>;\n> +\n> +\tphy-handle = <&ext_rgmii_phy>;\n> +\tphy-mode = \"rgmii\";\n> +\n> \tmdio: mdio {\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> \t\t#address-cells = <1>;\n> \t\t#size-cells = <0>;\n> -\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\text_rgmii_phy: ethernet-phy@1 {\n> \t\t\treg = <1>;\n> -\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> -\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> \t\t};\n> \t};\n> };\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776805,"web_url":"http://patchwork.ozlabs.org/comment/1776805/","msgid":"<20170928070710.GA32676@Red>","list_archive_url":null,"date":"2017-09-28T07:07:10","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Wed, Sep 27, 2017 at 09:53:15PM -0700, Florian Fainelli wrote:\n> \n> \n> On 09/27/2017 12:34 AM, Corentin Labbe wrote:\n> > This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> > for integrated PHY.\n> > \n> > Signed-off-by: Corentin Labbe \n> > ---\n> > .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++--\n> > 1 file changed, 126 insertions(+), 12 deletions(-)\n> > \n> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > index 725f3b187886..e2ef4683df08 100644\n> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.\n> > Please see stmmac.txt for the other unchanged properties.\n> > \n> > Required properties:\n> > -- compatible: should be one of the following string:\n> > +- compatible: must be one of the following string:\n> > \t\t\"allwinner,sun8i-a83t-emac\"\n> > \t\t\"allwinner,sun8i-h3-emac\"\n> > \t\t\"allwinner,sun8i-v3s-emac\"\n> > \t\t\"allwinner,sun50i-a64-emac\"\n> > - reg: address and length of the register for the device.\n> > - interrupts: interrupt for the device\n> > -- interrupt-names: should be \"macirq\"\n> > +- interrupt-names: must be \"macirq\"\n> > - clocks: A phandle to the reference clock for this device\n> > -- clock-names: should be \"stmmaceth\"\n> > +- clock-names: must be \"stmmaceth\"\n> > - resets: A phandle to the reset control for this device\n> > -- reset-names: should be \"stmmaceth\"\n> > +- reset-names: must be \"stmmaceth\"\n> > - phy-mode: See ethernet.txt\n> > - phy-handle: See ethernet.txt\n> > - #address-cells: shall be 1\n> > @@ -39,23 +39,38 @@ Optional properties for the following compatibles:\n> > - allwinner,leds-active-low: EPHY LEDs are active low\n> > \n> > Required child node of emac:\n> > -- mdio bus node: should be named mdio\n> > +- mdio bus node: with compatible \"snps,dwmac-mdio\"\n> > \n> > Required properties of the mdio node:\n> > - #address-cells: shall be 1\n> > - #size-cells: shall be 0\n> > \n> > -The device node referenced by \"phy\" or \"phy-handle\" should be a child node\n> > +The device node referenced by \"phy\" or \"phy-handle\" must be a child node\n> > of the mdio node. See phy.txt for the generic PHY bindings.\n> > \n> > -Required properties of the phy node with the following compatibles:\n> > +The following compatibles require that the mdio node have a mdio-mux child\n> > +node called \"mdio-mux\":\n> > + - \"allwinner,sun8i-h3-emac\"\n> > + - \"allwinner,sun8i-v3s-emac\":\n> > +Required properties for the mdio-mux node:\n> > + - compatible = \"mdio-mux\"\n> > + - one child mdio for the integrated mdio\n> > + - one child mdio for the external mdio if present (V3s have none)\n> > +Required properties for the mdio-mux children node:\n> > + - reg: 1 for internal MDIO bus, 2 for external MDIO bus\n> > +\n> > +The following compatibles require a PHY node representing the integrated\n> > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:\n> > - \"allwinner,sun8i-h3-emac\",\n> > - \"allwinner,sun8i-v3s-emac\":\n> > +\n> > +Required properties of the integrated phy node:\n> > - clocks: a phandle to the reference clock for the EPHY\n> > - resets: a phandle to the reset control for the EPHY\n> > +- phy-is-integrated\n> > +- Must be a child of the integrated mdio\n> > \n> > -Example:\n> > -\n> > +Example with integrated PHY:\n> > emac: ethernet@1c0b000 {\n> > \tcompatible = \"allwinner,sun8i-h3-emac\";\n> > \tsyscon = <&syscon>;\n> > @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {\n> > \tphy-handle = <&int_mii_phy>;\n> > \tphy-mode = \"mii\";\n> > \tallwinner,leds-active-low;\n> > +\n> > +\tmdio0: mdio {\n> > +\t\t#address-cells = <1>;\n> > +\t\t#size-cells = <0>;\n> > +\t\tcompatible = \"snps,dwmac-mdio\";\n> > +\n> > +\t\tmdio-mux {\n> > +\t\t\tcompatible = \"mdio-mux\";\n> > +\t\t\t#address-cells = <1>;\n> > +\t\t\t#size-cells = <0>;\n> \n> Sorry for chiming in so late, but why don't we have the mdio-mux be the\n> root node here in the mdio bus hierarchy? I understand that with this\n> binding proposed here, we need to have patch 11 included (which btw,\n> should come before any DTS change), but this does not seem to accurately\n> model the HW.\n> \n> The mux itself is not a child node of the MDIO bus controller, it does\n> not really belong in that address space although it does mangle the MDIO\n> bus controller address space between the two ends of the mux.\n> \n> If this has been debated before, apologies for missing that part of the\n> discussion.\n> \n\nI have done it as asked by Rob.\nhttps://lkml.org/lkml/2017/9/13/422\nhttps://lkml.org/lkml/2017/9/19/849\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tThu, 28 Sep 2017 00:07:18 -0700 (PDT)","Date":"Thu, 28 Sep 2017 09:07:10 +0200","From":"Corentin Labbe ","To":"Florian Fainelli ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, andrew@lunn.ch, frowand.list@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170928070710.GA32676@Red>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>\n\t<25e44368-2c07-9b7e-a0d3-a2a642286e5d@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<25e44368-2c07-9b7e-a0d3-a2a642286e5d@gmail.com>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776825,"web_url":"http://patchwork.ozlabs.org/comment/1776825/","msgid":"<20170928073708.GB32676@Red>","list_archive_url":null,"date":"2017-09-28T07:37:08","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> Hi Corentin\n> \n> > +Required properties for the mdio-mux node:\n> > + - compatible = \"mdio-mux\"\n> \n> This is too generic. Please add a more specific compatible for this\n> particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> subsystem will look for.\n> \n\nI will add allwinner,sun8i-h3-mdio-mux\n\n> > +Required properties of the integrated phy node:\n> > - clocks: a phandle to the reference clock for the EPHY\n> > - resets: a phandle to the reset control for the EPHY\n> > +- phy-is-integrated\n> \n> So the last thing you said is that the mux is not the problem\n> here. Something else is locking up. Did you discover what?\n> \n> I really would like phy-is-integrated to go away.\n> \n\nI have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\nSo we could remove phy-is-integrated by:\nMoving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\nBut this means:\n- getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n- doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; 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\n\tThu, 28 Sep 2017 00:37:15 -0700 (PDT)","Date":"Thu, 28 Sep 2017 09:37:08 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170928073708.GB32676@Red>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>\n\t<20170927140210.GE13516@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170927140210.GE13516@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1780071,"web_url":"http://patchwork.ozlabs.org/comment/1780071/","msgid":"<20171004190028.GA9208@Red>","list_archive_url":null,"date":"2017-10-04T19:00:28","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:\n> On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> > Hi Corentin\n> > \n> > > +Required properties for the mdio-mux node:\n> > > + - compatible = \"mdio-mux\"\n> > \n> > This is too generic. Please add a more specific compatible for this\n> > particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> > subsystem will look for.\n> > \n> \n> I will add allwinner,sun8i-h3-mdio-mux\n> \n> > > +Required properties of the integrated phy node:\n> > > - clocks: a phandle to the reference clock for the EPHY\n> > > - resets: a phandle to the reset control for the EPHY\n> > > +- phy-is-integrated\n> > \n> > So the last thing you said is that the mux is not the problem\n> > here. Something else is locking up. Did you discover what?\n> > \n> > I really would like phy-is-integrated to go away.\n> > \n> \n> I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\n> So we could remove phy-is-integrated by:\n> Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\n> But this means:\n> - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n> - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n> \n\nHello\n\nI have get rid of phy-is-integrated, but mdio_mux_syscon_switch_fn need to enable/disable ephy clk/reset.\nAnd so access to internal PHY node.\nBut current DT made this ugly: (need to find mdio-mux then internalmdio then internal PHY)\n\nSince MAC cannot reset/choose internal MDIO without ephy clk/rst, could we interpret this as thoses clk/rst must be set in emac node.\nThis will simplify a lot the code.\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170928073708.GB32676@Red>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1783249,"web_url":"http://patchwork.ozlabs.org/comment/1783249/","msgid":"<20171009210831.qc2cgxr4cx2qz5x7@flea.home>","list_archive_url":null,"date":"2017-10-09T21:08:31","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Sun, Oct 08, 2017 at 06:33:40PM +0000, Corentin Labbe wrote:\n> On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:\n> > On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> > > Hi Corentin\n> > > \n> > > > +Required properties for the mdio-mux node:\n> > > > + - compatible = \"mdio-mux\"\n> > > \n> > > This is too generic. Please add a more specific compatible for this\n> > > particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> > > subsystem will look for.\n> > > \n> > \n> > I will add allwinner,sun8i-h3-mdio-mux\n> > \n> > > > +Required properties of the integrated phy node:\n> > > > - clocks: a phandle to the reference clock for the EPHY\n> > > > - resets: a phandle to the reset control for the EPHY\n> > > > +- phy-is-integrated\n> > > \n> > > So the last thing you said is that the mux is not the problem\n> > > here. Something else is locking up. Did you discover what?\n> > > \n> > > I really would like phy-is-integrated to go away.\n> > > \n> > \n> > I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\n> > So we could remove phy-is-integrated by:\n> > Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\n> > But this means:\n> > - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n> > - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n> > \n> > Regards\n> \n> Hello all\n> \n> Below is the current patch, as you can read, it does not use anymore the phy-is-integrated property.\n> So now, the mdio-mux must always enable the internal mdio when switch_fn ask for it and so reset MAC and so need to enable ephy clk/reset.\n> But for this I need a reference to thoses clock and reset. (this is done in get_ephy_nodes)\n> The current version set those clock in mdio-mux node, and as you can see it is already ugly (lots of get next node),\n> if the clk/rst nodes were as it should be, in phy nodes, it will be more bad.\n> \n> So, since the MAC have a dependency on thoses clk/rst nodes for\n> doing reset(), I seek a proper way to get references on it.\n>\n> OR do you agree that putting ephy clk/rst in emac is acceptable ?\n\nWhy not just parsing the DT child nodes looking for resets and clocks\nproperties? The usual PHY don't have that.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9tC64wjBz9t5Q\n\tfor ;\n\tTue, 10 Oct 2017 08:08:50 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754700AbdJIVIe (ORCPT\n\t);\n\tMon, 9 Oct 2017 17:08:34 -0400","from mail.free-electrons.com ([62.4.15.54]:45210 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754530AbdJIVId (ORCPT\n\t); Mon, 9 Oct 2017 17:08:33 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid C9A2A207D4; Mon, 9 Oct 2017 23:08:30 +0200 (CEST)","from localhost (LFbn-TOU-1-209-191.w86-201.abo.wanadoo.fr\n\t[86.201.56.191])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 9EE2E2076D;\n\tMon, 9 Oct 2017 23:08:30 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 9 Oct 2017 23:08:31 +0200","From":"Maxime Ripard ","To":"Corentin Labbe ","Cc":"Andrew Lunn , robh+dt@kernel.org, wens@csie.org,\n\tf.fainelli@gmail.com, mark.rutland@arm.com, linux@armlinux.org.uk,\n\tcatalin.marinas@arm.com, will.deacon@arm.com,\n\tpeppe.cavallaro@st.com, alexandre.torgue@st.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20171009210831.qc2cgxr4cx2qz5x7@flea.home>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>\n\t<20170927140210.GE13516@lunn.ch> <20170928073708.GB32676@Red>\n\t<20171008183340.GA21531@Red>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"mrd4h4xx4avcyvdw\"","Content-Disposition":"inline","In-Reply-To":"<20171008183340.GA21531@Red>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]