[{"id":1776206,"web_url":"http://patchwork.ozlabs.org/comment/1776206/","msgid":"<20170927101508.z3u32gff7kqgnmr2@flea>","list_archive_url":null,"date":"2017-09-27T10:15:08","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Wed, Sep 27, 2017 at 07:34:08AM +0000, Corentin Labbe wrote:\n> This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> for integrated PHY.\n> \n> Signed-off-by: Corentin Labbe \n\nThis should be squashed with patch 1.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2DGt2RJxz9t66\n\tfor ;\n\tWed, 27 Sep 2017 20:15:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752478AbdI0KPW (ORCPT );\n\tWed, 27 Sep 2017 06:15:22 -0400","from mail.free-electrons.com ([62.4.15.54]:58037 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751808AbdI0KPU (ORCPT\n\t); Wed, 27 Sep 2017 06:15:20 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 096A42089D; Wed, 27 Sep 2017 12:15:18 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D9DED20898;\n\tWed, 27 Sep 2017 12:15:07 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Wed, 27 Sep 2017 12:15:08 +0200","From":"Maxime Ripard ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170927101508.z3u32gff7kqgnmr2@flea>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ghm4jv4fei6qquqw\"","Content-Disposition":"inline","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1776380,"web_url":"http://patchwork.ozlabs.org/comment/1776380/","msgid":"<20170927140210.GE13516@lunn.ch>","list_archive_url":null,"date":"2017-09-27T14:02:10","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"Hi Corentin\n\n> +Required properties for the mdio-mux node:\n> + - compatible = \"mdio-mux\"\n\nThis is too generic. Please add a more specific compatible for this\nparticular mux. You can keep \"mdio-mux\", since that is what the MDIO\nsubsystem will look for.\n\n> +Required properties of the integrated phy node:\n> - clocks: a phandle to the reference clock for the EPHY\n> - resets: a phandle to the reset control for the EPHY\n> +- phy-is-integrated\n\nSo the last thing you said is that the mux is not the problem\nhere. Something else is locking up. Did you discover what?\n\nI really would like phy-is-integrated to go away.\n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2KJr42qLz9tXy\n\tfor ;\n\tThu, 28 Sep 2017 00:02:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753229AbdI0OC0 (ORCPT );\n\tWed, 27 Sep 2017 10:02:26 -0400","from vps0.lunn.ch ([185.16.172.187]:58154 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753035AbdI0OCZ (ORCPT );\n\tWed, 27 Sep 2017 10:02:25 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dxCug-0002aa-AQ; Wed, 27 Sep 2017 16:02:10 +0200"],"Date":"Wed, 27 Sep 2017 16:02:10 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20170927140210.GE13516@lunn.ch>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1776766,"web_url":"http://patchwork.ozlabs.org/comment/1776766/","msgid":"<25e44368-2c07-9b7e-a0d3-a2a642286e5d@gmail.com>","list_archive_url":null,"date":"2017-09-28T04:53:15","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/people/2800/","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"content":"On 09/27/2017 12:34 AM, Corentin Labbe wrote:\n> This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> for integrated PHY.\n> \n> Signed-off-by: Corentin Labbe \n> ---\n> .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++--\n> 1 file changed, 126 insertions(+), 12 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> index 725f3b187886..e2ef4683df08 100644\n> --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.\n> Please see stmmac.txt for the other unchanged properties.\n> \n> Required properties:\n> -- compatible: should be one of the following string:\n> +- compatible: must be one of the following string:\n> \t\t\"allwinner,sun8i-a83t-emac\"\n> \t\t\"allwinner,sun8i-h3-emac\"\n> \t\t\"allwinner,sun8i-v3s-emac\"\n> \t\t\"allwinner,sun50i-a64-emac\"\n> - reg: address and length of the register for the device.\n> - interrupts: interrupt for the device\n> -- interrupt-names: should be \"macirq\"\n> +- interrupt-names: must be \"macirq\"\n> - clocks: A phandle to the reference clock for this device\n> -- clock-names: should be \"stmmaceth\"\n> +- clock-names: must be \"stmmaceth\"\n> - resets: A phandle to the reset control for this device\n> -- reset-names: should be \"stmmaceth\"\n> +- reset-names: must be \"stmmaceth\"\n> - phy-mode: See ethernet.txt\n> - phy-handle: See ethernet.txt\n> - #address-cells: shall be 1\n> @@ -39,23 +39,38 @@ Optional properties for the following compatibles:\n> - allwinner,leds-active-low: EPHY LEDs are active low\n> \n> Required child node of emac:\n> -- mdio bus node: should be named mdio\n> +- mdio bus node: with compatible \"snps,dwmac-mdio\"\n> \n> Required properties of the mdio node:\n> - #address-cells: shall be 1\n> - #size-cells: shall be 0\n> \n> -The device node referenced by \"phy\" or \"phy-handle\" should be a child node\n> +The device node referenced by \"phy\" or \"phy-handle\" must be a child node\n> of the mdio node. See phy.txt for the generic PHY bindings.\n> \n> -Required properties of the phy node with the following compatibles:\n> +The following compatibles require that the mdio node have a mdio-mux child\n> +node called \"mdio-mux\":\n> + - \"allwinner,sun8i-h3-emac\"\n> + - \"allwinner,sun8i-v3s-emac\":\n> +Required properties for the mdio-mux node:\n> + - compatible = \"mdio-mux\"\n> + - one child mdio for the integrated mdio\n> + - one child mdio for the external mdio if present (V3s have none)\n> +Required properties for the mdio-mux children node:\n> + - reg: 1 for internal MDIO bus, 2 for external MDIO bus\n> +\n> +The following compatibles require a PHY node representing the integrated\n> +PHY, under the integrated MDIO bus node if an mdio-mux node is used:\n> - \"allwinner,sun8i-h3-emac\",\n> - \"allwinner,sun8i-v3s-emac\":\n> +\n> +Required properties of the integrated phy node:\n> - clocks: a phandle to the reference clock for the EPHY\n> - resets: a phandle to the reset control for the EPHY\n> +- phy-is-integrated\n> +- Must be a child of the integrated mdio\n> \n> -Example:\n> -\n> +Example with integrated PHY:\n> emac: ethernet@1c0b000 {\n> \tcompatible = \"allwinner,sun8i-h3-emac\";\n> \tsyscon = <&syscon>;\n> @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {\n> \tphy-handle = <&int_mii_phy>;\n> \tphy-mode = \"mii\";\n> \tallwinner,leds-active-low;\n> +\n> +\tmdio0: mdio {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> +\n> +\t\tmdio-mux {\n> +\t\t\tcompatible = \"mdio-mux\";\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n\nSorry for chiming in so late, but why don't we have the mdio-mux be the\nroot node here in the mdio bus hierarchy? I understand that with this\nbinding proposed here, we need to have patch 11 included (which btw,\nshould come before any DTS change), but this does not seem to accurately\nmodel the HW.\n\nThe mux itself is not a child node of the MDIO bus controller, it does\nnot really belong in that address space although it does mangle the MDIO\nbus controller address space between the two ends of the mux.\n\nIf this has been debated before, apologies for missing that part of the\ndiscussion.\n\n> +\n> +\t\t\tint_mdio: mdio@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> +\t\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> +\t\t\t\t\tphy-is-integrated;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t\text_mdio: mdio@2 {\n> +\t\t\t\treg = <2>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +};\n> +\n> +Example with external PHY:\n> +emac: ethernet@1c0b000 {\n> +\tcompatible = \"allwinner,sun8i-h3-emac\";\n> +\tsyscon = <&syscon>;\n> +\treg = <0x01c0b000 0x104>;\n> +\tinterrupts = ;\n> +\tinterrupt-names = \"macirq\";\n> +\tresets = <&ccu RST_BUS_EMAC>;\n> +\treset-names = \"stmmaceth\";\n> +\tclocks = <&ccu CLK_BUS_EMAC>;\n> +\tclock-names = \"stmmaceth\";\n> +\t#address-cells = <1>;\n> +\t#size-cells = <0>;\n> +\n> +\tphy-handle = <&ext_rgmii_phy>;\n> +\tphy-mode = \"rgmii\";\n> +\tallwinner,leds-active-low;\n> +\n> +\tmdio0: mdio {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> +\n> +\t\tmdio-mux {\n> +\t\t\tcompatible = \"mdio-mux\";\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tint_mdio: mdio@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> +\t\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> +\t\t\t\t\tphy-is-integrated;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t\text_mdio: mdio@2 {\n> +\t\t\t\treg = <2>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\t\t\t\text_rgmii_phy: ethernet-phy@1 {\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t};\n> +\t\t\t}:\n> +\t\t};\n> +\t};\n> +};\n> +\n> +Example with SoC without integrated PHY\n> +\n> +emac: ethernet@1c0b000 {\n> +\tcompatible = \"allwinner,sun8i-a83t-emac\";\n> +\tsyscon = <&syscon>;\n> +\treg = <0x01c0b000 0x104>;\n> +\tinterrupts = ;\n> +\tinterrupt-names = \"macirq\";\n> +\tresets = <&ccu RST_BUS_EMAC>;\n> +\treset-names = \"stmmaceth\";\n> +\tclocks = <&ccu CLK_BUS_EMAC>;\n> +\tclock-names = \"stmmaceth\";\n> +\t#address-cells = <1>;\n> +\t#size-cells = <0>;\n> +\n> +\tphy-handle = <&ext_rgmii_phy>;\n> +\tphy-mode = \"rgmii\";\n> +\n> \tmdio: mdio {\n> +\t\tcompatible = \"snps,dwmac-mdio\";\n> \t\t#address-cells = <1>;\n> \t\t#size-cells = <0>;\n> -\t\tint_mii_phy: ethernet-phy@1 {\n> +\t\text_rgmii_phy: ethernet-phy@1 {\n> \t\t\treg = <1>;\n> -\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n> -\t\t\tresets = <&ccu RST_BUS_EPHY>;\n> \t\t};\n> \t};\n> };\n>","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927073414.17361-6-clabbe.montjoie@gmail.com>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1776806,"web_url":"http://patchwork.ozlabs.org/comment/1776806/","msgid":"<20170928070710.GA32676@Red>","list_archive_url":null,"date":"2017-09-28T07:07:10","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Wed, Sep 27, 2017 at 09:53:15PM -0700, Florian Fainelli wrote:\n> \n> \n> On 09/27/2017 12:34 AM, Corentin Labbe wrote:\n> > This patch add documentation about the MDIO switch used on sun8i-h3-emac\n> > for integrated PHY.\n> > \n> > Signed-off-by: Corentin Labbe \n> > ---\n> > .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++--\n> > 1 file changed, 126 insertions(+), 12 deletions(-)\n> > \n> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > index 725f3b187886..e2ef4683df08 100644\n> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt\n> > @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.\n> > Please see stmmac.txt for the other unchanged properties.\n> > \n> > Required properties:\n> > -- compatible: should be one of the following string:\n> > +- compatible: must be one of the following string:\n> > \t\t\"allwinner,sun8i-a83t-emac\"\n> > \t\t\"allwinner,sun8i-h3-emac\"\n> > \t\t\"allwinner,sun8i-v3s-emac\"\n> > \t\t\"allwinner,sun50i-a64-emac\"\n> > - reg: address and length of the register for the device.\n> > - interrupts: interrupt for the device\n> > -- interrupt-names: should be \"macirq\"\n> > +- interrupt-names: must be \"macirq\"\n> > - clocks: A phandle to the reference clock for this device\n> > -- clock-names: should be \"stmmaceth\"\n> > +- clock-names: must be \"stmmaceth\"\n> > - resets: A phandle to the reset control for this device\n> > -- reset-names: should be \"stmmaceth\"\n> > +- reset-names: must be \"stmmaceth\"\n> > - phy-mode: See ethernet.txt\n> > - phy-handle: See ethernet.txt\n> > - #address-cells: shall be 1\n> > @@ -39,23 +39,38 @@ Optional properties for the following compatibles:\n> > - allwinner,leds-active-low: EPHY LEDs are active low\n> > \n> > Required child node of emac:\n> > -- mdio bus node: should be named mdio\n> > +- mdio bus node: with compatible \"snps,dwmac-mdio\"\n> > \n> > Required properties of the mdio node:\n> > - #address-cells: shall be 1\n> > - #size-cells: shall be 0\n> > \n> > -The device node referenced by \"phy\" or \"phy-handle\" should be a child node\n> > +The device node referenced by \"phy\" or \"phy-handle\" must be a child node\n> > of the mdio node. See phy.txt for the generic PHY bindings.\n> > \n> > -Required properties of the phy node with the following compatibles:\n> > +The following compatibles require that the mdio node have a mdio-mux child\n> > +node called \"mdio-mux\":\n> > + - \"allwinner,sun8i-h3-emac\"\n> > + - \"allwinner,sun8i-v3s-emac\":\n> > +Required properties for the mdio-mux node:\n> > + - compatible = \"mdio-mux\"\n> > + - one child mdio for the integrated mdio\n> > + - one child mdio for the external mdio if present (V3s have none)\n> > +Required properties for the mdio-mux children node:\n> > + - reg: 1 for internal MDIO bus, 2 for external MDIO bus\n> > +\n> > +The following compatibles require a PHY node representing the integrated\n> > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:\n> > - \"allwinner,sun8i-h3-emac\",\n> > - \"allwinner,sun8i-v3s-emac\":\n> > +\n> > +Required properties of the integrated phy node:\n> > - clocks: a phandle to the reference clock for the EPHY\n> > - resets: a phandle to the reset control for the EPHY\n> > +- phy-is-integrated\n> > +- Must be a child of the integrated mdio\n> > \n> > -Example:\n> > -\n> > +Example with integrated PHY:\n> > emac: ethernet@1c0b000 {\n> > \tcompatible = \"allwinner,sun8i-h3-emac\";\n> > \tsyscon = <&syscon>;\n> > @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {\n> > \tphy-handle = <&int_mii_phy>;\n> > \tphy-mode = \"mii\";\n> > \tallwinner,leds-active-low;\n> > +\n> > +\tmdio0: mdio {\n> > +\t\t#address-cells = <1>;\n> > +\t\t#size-cells = <0>;\n> > +\t\tcompatible = \"snps,dwmac-mdio\";\n> > +\n> > +\t\tmdio-mux {\n> > +\t\t\tcompatible = \"mdio-mux\";\n> > +\t\t\t#address-cells = <1>;\n> > +\t\t\t#size-cells = <0>;\n> \n> Sorry for chiming in so late, but why don't we have the mdio-mux be the\n> root node here in the mdio bus hierarchy? I understand that with this\n> binding proposed here, we need to have patch 11 included (which btw,\n> should come before any DTS change), but this does not seem to accurately\n> model the HW.\n> \n> The mux itself is not a child node of the MDIO bus controller, it does\n> not really belong in that address space although it does mangle the MDIO\n> bus controller address space between the two ends of the mux.\n> \n> If this has been debated before, apologies for missing that part of the\n> discussion.\n> \n\nI have done it as asked by Rob.\nhttps://lkml.org/lkml/2017/9/13/422\nhttps://lkml.org/lkml/2017/9/19/849\n\nRegards","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"mBwrfuNi\"; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<25e44368-2c07-9b7e-a0d3-a2a642286e5d@gmail.com>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1776826,"web_url":"http://patchwork.ozlabs.org/comment/1776826/","msgid":"<20170928073708.GB32676@Red>","list_archive_url":null,"date":"2017-09-28T07:37:08","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> Hi Corentin\n> \n> > +Required properties for the mdio-mux node:\n> > + - compatible = \"mdio-mux\"\n> \n> This is too generic. Please add a more specific compatible for this\n> particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> subsystem will look for.\n> \n\nI will add allwinner,sun8i-h3-mdio-mux\n\n> > +Required properties of the integrated phy node:\n> > - clocks: a phandle to the reference clock for the EPHY\n> > - resets: a phandle to the reset control for the EPHY\n> > +- phy-is-integrated\n> \n> So the last thing you said is that the mux is not the problem\n> here. Something else is locking up. Did you discover what?\n> \n> I really would like phy-is-integrated to go away.\n> \n\nI have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\nSo we could remove phy-is-integrated by:\nMoving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\nBut this means:\n- getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n- doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n\nRegards","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Q6LBOITu\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2mk46jpjz9t5x\n\tfor ;\n\tThu, 28 Sep 2017 17:37:32 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751710AbdI1HhS (ORCPT );\n\tThu, 28 Sep 2017 03:37:18 -0400","from mail-wm0-f51.google.com ([74.125.82.51]:45394 \"EHLO\n\tmail-wm0-f51.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751350AbdI1HhQ (ORCPT\n\t); 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170927140210.GE13516@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1780070,"web_url":"http://patchwork.ozlabs.org/comment/1780070/","msgid":"<20171004190028.GA9208@Red>","list_archive_url":null,"date":"2017-10-04T19:00:28","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:\n> On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> > Hi Corentin\n> > \n> > > +Required properties for the mdio-mux node:\n> > > + - compatible = \"mdio-mux\"\n> > \n> > This is too generic. Please add a more specific compatible for this\n> > particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> > subsystem will look for.\n> > \n> \n> I will add allwinner,sun8i-h3-mdio-mux\n> \n> > > +Required properties of the integrated phy node:\n> > > - clocks: a phandle to the reference clock for the EPHY\n> > > - resets: a phandle to the reset control for the EPHY\n> > > +- phy-is-integrated\n> > \n> > So the last thing you said is that the mux is not the problem\n> > here. Something else is locking up. Did you discover what?\n> > \n> > I really would like phy-is-integrated to go away.\n> > \n> \n> I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\n> So we could remove phy-is-integrated by:\n> Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\n> But this means:\n> - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n> - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n> \n\nHello\n\nI have get rid of phy-is-integrated, but mdio_mux_syscon_switch_fn need to enable/disable ephy clk/reset.\nAnd so access to internal PHY node.\nBut current DT made this ugly: (need to find mdio-mux then internalmdio then internal PHY)\n\nSince MAC cannot reset/choose internal MDIO without ephy clk/rst, could we interpret this as thoses clk/rst must be set in emac node.\nThis will simplify a lot the code.\n\nRegards","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170928073708.GB32676@Red>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1782306,"web_url":"http://patchwork.ozlabs.org/comment/1782306/","msgid":"<20171008183340.GA21531@Red>","list_archive_url":null,"date":"2017-10-08T18:33:40","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:\n> On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> > Hi Corentin\n> > \n> > > +Required properties for the mdio-mux node:\n> > > + - compatible = \"mdio-mux\"\n> > \n> > This is too generic. Please add a more specific compatible for this\n> > particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> > subsystem will look for.\n> > \n> \n> I will add allwinner,sun8i-h3-mdio-mux\n> \n> > > +Required properties of the integrated phy node:\n> > > - clocks: a phandle to the reference clock for the EPHY\n> > > - resets: a phandle to the reset control for the EPHY\n> > > +- phy-is-integrated\n> > \n> > So the last thing you said is that the mux is not the problem\n> > here. Something else is locking up. Did you discover what?\n> > \n> > I really would like phy-is-integrated to go away.\n> > \n> \n> I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\n> So we could remove phy-is-integrated by:\n> Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\n> But this means:\n> - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n> - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n> \n> Regards\n\nHello all\n\nBelow is the current patch, as you can read, it does not use anymore the phy-is-integrated property.\nSo now, the mdio-mux must always enable the internal mdio when switch_fn ask for it and so reset MAC and so need to enable ephy clk/reset.\nBut for this I need a reference to thoses clock and reset. (this is done in get_ephy_nodes)\nThe current version set those clock in mdio-mux node, and as you can see it is already ugly (lots of get next node),\nif the clk/rst nodes were as it should be, in phy nodes, it will be more bad.\n\nSo, since the MAC have a dependency on thoses clk/rst nodes for doing reset(), I seek a proper way to get references on it.\nOR do you agree that putting ephy clk/rst in emac is acceptable ?\n\nthanks\nregards\n\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n@@ -17,6 +17,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -41,14 +42,14 @@\n *\t\t\t\tThis value is used for disabling properly EMAC\n *\t\t\t\tand used as a good starting value in case of the\n *\t\t\t\tboot process(uboot) leave some stuff.\n- * @internal_phy:\t\tDoes the MAC embed an internal PHY\n+ * @soc_has_internal_phy:\tDoes the MAC embed an internal PHY\n * @support_mii:\t\tDoes the MAC handle MII\n * @support_rmii:\t\tDoes the MAC handle RMII\n * @support_rgmii:\t\tDoes the MAC handle RGMII\n */\n struct emac_variant {\n \tu32 default_syscon_value;\n-\tint internal_phy;\n+\tbool soc_has_internal_phy;\n \tbool support_mii;\n \tbool support_rmii;\n \tbool support_rgmii;\n@@ -61,7 +62,7 @@ struct emac_variant {\n * @rst_ephy:\treference to the optional EPHY reset for the internal PHY\n * @variant:\treference to the current board variant\n * @regmap:\tregmap for using the syscon\n- * @use_internal_phy: Does the current PHY choice imply using the internal PHY\n+ * @internal_phy_powered: Does the internal PHY is enabled\n */\n struct sunxi_priv_data {\n \tstruct clk *tx_clk;\n@@ -70,12 +71,13 @@ struct sunxi_priv_data {\n \tstruct reset_control *rst_ephy;\n \tconst struct emac_variant *variant;\n \tstruct regmap *regmap;\n-\tbool use_internal_phy;\n+\tbool internal_phy_powered;\n+\tvoid *mux_handle;\n };\n \n static const struct emac_variant emac_variant_h3 = {\n \t.default_syscon_value = 0x58000,\n-\t.internal_phy = PHY_INTERFACE_MODE_MII,\n+\t.soc_has_internal_phy = true,\n \t.support_mii = true,\n \t.support_rmii = true,\n \t.support_rgmii = true\n@@ -83,20 +85,20 @@ static const struct emac_variant emac_variant_h3 = {\n \n static const struct emac_variant emac_variant_v3s = {\n \t.default_syscon_value = 0x38000,\n-\t.internal_phy = PHY_INTERFACE_MODE_MII,\n+\t.soc_has_internal_phy = true,\n \t.support_mii = true\n };\n \n static const struct emac_variant emac_variant_a83t = {\n \t.default_syscon_value = 0,\n-\t.internal_phy = 0,\n+\t.soc_has_internal_phy = false,\n \t.support_mii = true,\n \t.support_rgmii = true\n };\n \n static const struct emac_variant emac_variant_a64 = {\n \t.default_syscon_value = 0,\n-\t.internal_phy = 0,\n+\t.soc_has_internal_phy = false,\n \t.support_mii = true,\n \t.support_rmii = true,\n \t.support_rgmii = true\n@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = {\n #define H3_EPHY_LED_POL\t\tBIT(17) /* 1: active low, 0: active high */\n #define H3_EPHY_SHUTDOWN\tBIT(16) /* 1: shutdown, 0: power up */\n #define H3_EPHY_SELECT\t\tBIT(15) /* 1: internal PHY, 0: external PHY */\n+#define H3_EPHY_MUX_MASK\t(H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)\n+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID\t1\n+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID\t2\n \n /* H3/A64 specific bits */\n #define SYSCON_RMII_EN\t\tBIT(13) /* 1: enable RMII (overrides EPIT) */\n@@ -634,6 +639,164 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)\n \treturn 0;\n }\n \n+static int get_ephy_nodes(struct stmmac_priv *priv)\n+{\n+\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n+\tstruct device_node *mdio_mux;\n+\tstruct device_node *mdio_internal;\n+\tint ret;\n+\n+\tmdio_mux = of_get_child_by_name(priv->plat->mdio_node, \"mdio-mux\");\n+\tif (!mdio_mux) {\n+\t\tdev_err(priv->device, \"Cannot get mdio-mux node\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tmdio_internal = of_find_compatible_node(mdio_mux, NULL,\n+\t\t\t\t\t\t\"allwinner,sun8i-h3-mdio-internal\");\n+\tif (!mdio_internal) {\n+\t\tdev_err(priv->device, \"Cannot get internal_mdio node\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* insert here code to get child phynode */\n+\tgmac->ephy_clk = of_clk_get(mdio_internal, 0);\n+\tif (IS_ERR(gmac->ephy_clk)) {\n+\t\tret = PTR_ERR(gmac->ephy_clk);\n+\t\tdev_err(priv->device, \"Cannot get EPHY clock: %d\\n\", ret);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Note that we cannot use devm_reset_control_get, since\n+\t * the reset is not in the device node.\n+\t */\n+\tgmac->rst_ephy = of_reset_control_get_exclusive(mdio_internal, NULL);\n+\tif (IS_ERR(gmac->rst_ephy)) {\n+\t\tret = PTR_ERR(gmac->rst_ephy);\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\treturn ret;\n+\t\tdev_err(priv->device, \"No EPHY reset control found %d\\n\", ret);\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)\n+{\n+\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n+\tint ret;\n+\n+\tif (gmac->internal_phy_powered) {\n+\t\tdev_warn(priv->device, \"Internal PHY already powered\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tdev_info(priv->device, \"Powering internal PHY\\n\");\n+\tret = clk_prepare_enable(gmac->ephy_clk);\n+\tif (ret) {\n+\t\tdev_err(priv->device, \"Cannot enable internal PHY\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Make sure the EPHY is properly reseted, as U-Boot may leave\n+\t * it at deasserted state, and thus it may fail to reset EMAC.\n+\t */\n+\treset_control_assert(gmac->rst_ephy);\n+\n+\tret = reset_control_deassert(gmac->rst_ephy);\n+\tif (ret) {\n+\t\tdev_err(priv->device, \"Cannot deassert internal phy\\n\");\n+\t\tclk_disable_unprepare(gmac->ephy_clk);\n+\t\treturn ret;\n+\t}\n+\n+\tgmac->internal_phy_powered = true;\n+\n+\treturn 0;\n+}\n+\n+static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)\n+{\n+\tif (!gmac->internal_phy_powered)\n+\t\treturn 0;\n+\n+\tclk_disable_unprepare(gmac->ephy_clk);\n+\treset_control_assert(gmac->rst_ephy);\n+\tgmac->internal_phy_powered = false;\n+\treturn 0;\n+}\n+\n+/* MDIO multiplexing switch function\n+ * This function is called by the mdio-mux layer when it thinks the mdio bus\n+ * multiplexer needs to switch.\n+ * 'current_child' is the current value of the mux register\n+ * 'desired_child' is the value of the 'reg' property of the target child MDIO\n+ * node.\n+ * The first time this function is called, current_child == -1.\n+ * If current_child == desired_child, then the mux is already set to the\n+ * correct bus.\n+ *\n+ * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to\n+ * know easily which bus is used (reset must be done only for desired bus).\n+ */\n+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n+\t\t\t\t void *data)\n+{\n+\tstruct stmmac_priv *priv = data;\n+\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n+\tu32 reg, val;\n+\tint ret = 0;\n+\tbool need_power_ephy = false;\n+\n+\tif (current_child ^ desired_child) {\n+\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n+\t\tswitch (desired_child) {\n+\t\tcase DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:\n+\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n+\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n+\n+\t\t\tneed_power_ephy = true;\n+\t\t\tbreak;\n+\t\tcase DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:\n+\t\t\tdev_info(priv->device, \"Switch mux to external PHY\");\n+\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;\n+\t\t\tneed_power_ephy = false;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(priv->device, \"Invalid child ID %x\\n\",\n+\t\t\t\tdesired_child);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tregmap_write(gmac->regmap, SYSCON_EMAC_REG, val);\n+\t\tif (need_power_ephy) {\n+\t\t\tret = sun8i_dwmac_power_internal_phy(priv);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tsun8i_dwmac_unpower_internal_phy(gmac);\n+\t\t}\n+\t\t/* After changing syscon value, the MAC need reset or it will\n+\t\t * use the last value (and so the last PHY set).\n+\t\t */\n+\t\tret = sun8i_dwmac_reset(priv);\n+\t}\n+\treturn ret;\n+}\n+\n+static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)\n+{\n+\tint ret;\n+\tstruct device_node *mdio_mux;\n+\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n+\n+\tmdio_mux = of_get_child_by_name(priv->plat->mdio_node, \"mdio-mux\");\n+\tif (!mdio_mux)\n+\t\treturn -ENODEV;\n+\n+\tret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,\n+\t\t\t &gmac->mux_handle, priv, priv->mii);\n+\treturn ret;\n+}\n+\n static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)\n {\n \tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n@@ -648,35 +811,25 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)\n \t\t\t \"Current syscon value is not the default %x (expect %x)\\n\",\n \t\t\t val, reg);\n \n-\tif (gmac->variant->internal_phy) {\n-\t\tif (!gmac->use_internal_phy) {\n-\t\t\t/* switch to external PHY interface */\n-\t\t\treg &= ~H3_EPHY_SELECT;\n-\t\t} else {\n-\t\t\treg |= H3_EPHY_SELECT;\n-\t\t\treg &= ~H3_EPHY_SHUTDOWN;\n-\t\t\tdev_dbg(priv->device, \"Select internal_phy %x\\n\", reg);\n-\n-\t\t\tif (of_property_read_bool(priv->plat->phy_node,\n-\t\t\t\t\t\t \"allwinner,leds-active-low\"))\n-\t\t\t\treg |= H3_EPHY_LED_POL;\n-\t\t\telse\n-\t\t\t\treg &= ~H3_EPHY_LED_POL;\n-\n-\t\t\t/* Force EPHY xtal frequency to 24MHz. */\n-\t\t\treg |= H3_EPHY_CLK_SEL;\n-\n-\t\t\tret = of_mdio_parse_addr(priv->device,\n-\t\t\t\t\t\t priv->plat->phy_node);\n-\t\t\tif (ret < 0) {\n-\t\t\t\tdev_err(priv->device, \"Could not parse MDIO addr\\n\");\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t\t/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY\n-\t\t\t * address. No need to mask it again.\n-\t\t\t */\n-\t\t\treg |= ret << H3_EPHY_ADDR_SHIFT;\n+\tif (gmac->variant->soc_has_internal_phy) {\n+\t\tif (of_property_read_bool(priv->plat->phy_node,\n+\t\t\t\t\t \"allwinner,leds-active-low\"))\n+\t\t\treg |= H3_EPHY_LED_POL;\n+\t\telse\n+\t\t\treg &= ~H3_EPHY_LED_POL;\n+\n+\t\t/* Force EPHY xtal frequency to 24MHz. */\n+\t\treg |= H3_EPHY_CLK_SEL;\n+\n+\t\tret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(priv->device, \"Could not parse MDIO addr\\n\");\n+\t\t\treturn ret;\n \t\t}\n+\t\t/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY\n+\t\t * address. No need to mask it again.\n+\t\t */\n+\t\treg |= 1 << H3_EPHY_ADDR_SHIFT;\n \t}\n \n \tif (!of_property_read_u32(node, \"allwinner,tx-delay-ps\", &val)) {\n@@ -746,81 +899,21 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)\n \tregmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);\n }\n \n-static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)\n+static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)\n {\n-\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n-\tint ret;\n-\n-\tif (!gmac->use_internal_phy)\n-\t\treturn 0;\n-\n-\tret = clk_prepare_enable(gmac->ephy_clk);\n-\tif (ret) {\n-\t\tdev_err(priv->device, \"Cannot enable ephy\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Make sure the EPHY is properly reseted, as U-Boot may leave\n-\t * it at deasserted state, and thus it may fail to reset EMAC.\n-\t */\n-\treset_control_assert(gmac->rst_ephy);\n+\tstruct sunxi_priv_data *gmac = priv;\n \n-\tret = reset_control_deassert(gmac->rst_ephy);\n-\tif (ret) {\n-\t\tdev_err(priv->device, \"Cannot deassert ephy\\n\");\n-\t\tclk_disable_unprepare(gmac->ephy_clk);\n-\t\treturn ret;\n+\tif (gmac->variant->soc_has_internal_phy) {\n+\t\t/* sun8i_dwmac_exit could be called with mdiomux uninit */\n+\t\tif (gmac->mux_handle)\n+\t\t\tmdio_mux_uninit(gmac->mux_handle);\n+\t\tif (gmac->internal_phy_powered)\n+\t\t\tsun8i_dwmac_unpower_internal_phy(gmac);\n \t}\n \n-\treturn 0;\n-}\n-\n-static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)\n-{\n-\tif (!gmac->use_internal_phy)\n-\t\treturn 0;\n-\n-\tclk_disable_unprepare(gmac->ephy_clk);\n-\treset_control_assert(gmac->rst_ephy);\n-\treturn 0;\n-}\n-\n-/* sun8i_power_phy() - Activate the PHY:\n- * In case of error, no need to call sun8i_unpower_phy(),\n- * it will be called anyway by sun8i_dwmac_exit()\n- */\n-static int sun8i_power_phy(struct stmmac_priv *priv)\n-{\n-\tint ret;\n-\n-\tret = sun8i_dwmac_power_internal_phy(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = sun8i_dwmac_set_syscon(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* After changing syscon value, the MAC need reset or it will use\n-\t * the last value (and so the last PHY set.\n-\t */\n-\tret = sun8i_dwmac_reset(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\treturn 0;\n-}\n-\n-static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)\n-{\n \tsun8i_dwmac_unset_syscon(gmac);\n-\tsun8i_dwmac_unpower_internal_phy(gmac);\n-}\n \n-static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)\n-{\n-\tstruct sunxi_priv_data *gmac = priv;\n-\n-\tsun8i_unpower_phy(gmac);\n+\treset_control_put(gmac->rst_ephy);\n \n \tclk_disable_unprepare(gmac->tx_clk);\n \n@@ -849,7 +942,7 @@ static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)\n \tif (!mac)\n \t\treturn NULL;\n \n-\tret = sun8i_power_phy(priv);\n+\tret = sun8i_dwmac_set_syscon(priv);\n \tif (ret)\n \t\treturn NULL;\n \n@@ -889,6 +982,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)\n \tstruct sunxi_priv_data *gmac;\n \tstruct device *dev = &pdev->dev;\n \tint ret;\n+\tstruct stmmac_priv *priv;\n+\tstruct net_device *ndev;\n \n \tret = stmmac_get_platform_resources(pdev, &stmmac_res);\n \tif (ret)\n@@ -932,29 +1027,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)\n \t}\n \n \tplat_dat->interface = of_get_phy_mode(dev->of_node);\n-\tif (plat_dat->interface == gmac->variant->internal_phy) {\n-\t\tdev_info(&pdev->dev, \"Will use internal PHY\\n\");\n-\t\tgmac->use_internal_phy = true;\n-\t\tgmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);\n-\t\tif (IS_ERR(gmac->ephy_clk)) {\n-\t\t\tret = PTR_ERR(gmac->ephy_clk);\n-\t\t\tdev_err(&pdev->dev, \"Cannot get EPHY clock: %d\\n\", ret);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tgmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);\n-\t\tif (IS_ERR(gmac->rst_ephy)) {\n-\t\t\tret = PTR_ERR(gmac->rst_ephy);\n-\t\t\tif (ret == -EPROBE_DEFER)\n-\t\t\t\treturn ret;\n-\t\t\tdev_err(&pdev->dev, \"No EPHY reset control found %d\\n\",\n-\t\t\t\tret);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\tdev_info(&pdev->dev, \"Will use external PHY\\n\");\n-\t\tgmac->use_internal_phy = false;\n-\t}\n \n \t/* platform data specifying hardware features and callbacks.\n \t * hardware features were copied from Allwinner drivers.\n@@ -973,9 +1045,34 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)\n \n \tret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);\n \tif (ret)\n-\t\tsun8i_dwmac_exit(pdev, plat_dat->bsp_priv);\n+\t\tgoto dwmac_exit;\n+\n+\tndev = dev_get_drvdata(&pdev->dev);\n+\tpriv = netdev_priv(ndev);\n+\t/* The mux must be registered after parent MDIO\n+\t * so after stmmac_dvr_probe()\n+\t */\n+\tif (gmac->variant->soc_has_internal_phy) {\n+\t\tret = get_ephy_nodes(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tret = sun8i_dwmac_register_mdio_mux(priv);\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"Failed to register mux\\n\");\n+\t\t\tgoto dwmac_mux;\n+\t\t}\n+\t} else {\n+\t\tret = sun8i_dwmac_reset(priv);\n+\t\tif (ret)\n+\t\t\tgoto dwmac_exit;\n+\t}\n \n \treturn ret;\n+dwmac_mux:\n+\tsun8i_dwmac_unset_syscon(gmac);\n+dwmac_exit:\n+\tsun8i_dwmac_exit(pdev, plat_dat->bsp_priv);\n+return ret;\n }\n \n static const struct of_device_id sun8i_dwmac_match[] = {","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"aCTOBx9N\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 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robh+dt@kernel.org,\n\tmaxime.ripard@free-electrons.com, wens@csie.org, f.fainelli@gmail.com","Cc":"mark.rutland@arm.com, linux@armlinux.org.uk,\n\tcatalin.marinas@arm.com, will.deacon@arm.com,\n\tpeppe.cavallaro@st.com, alexandre.torgue@st.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20171008183340.GA21531@Red>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>\n\t<20170927140210.GE13516@lunn.ch> <20170928073708.GB32676@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170928073708.GB32676@Red>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1783248,"web_url":"http://patchwork.ozlabs.org/comment/1783248/","msgid":"<20171009210831.qc2cgxr4cx2qz5x7@flea.home>","list_archive_url":null,"date":"2017-10-09T21:08:31","subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Sun, Oct 08, 2017 at 06:33:40PM +0000, Corentin Labbe wrote:\n> On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:\n> > On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:\n> > > Hi Corentin\n> > > \n> > > > +Required properties for the mdio-mux node:\n> > > > + - compatible = \"mdio-mux\"\n> > > \n> > > This is too generic. Please add a more specific compatible for this\n> > > particular mux. You can keep \"mdio-mux\", since that is what the MDIO\n> > > subsystem will look for.\n> > > \n> > \n> > I will add allwinner,sun8i-h3-mdio-mux\n> > \n> > > > +Required properties of the integrated phy node:\n> > > > - clocks: a phandle to the reference clock for the EPHY\n> > > > - resets: a phandle to the reset control for the EPHY\n> > > > +- phy-is-integrated\n> > > \n> > > So the last thing you said is that the mux is not the problem\n> > > here. Something else is locking up. Did you discover what?\n> > > \n> > > I really would like phy-is-integrated to go away.\n> > > \n> > \n> > I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore.\n> > So we could remove phy-is-integrated by:\n> > Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()\n> > But this means:\n> > - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle)\n> > - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed\n> > \n> > Regards\n> \n> Hello all\n> \n> Below is the current patch, as you can read, it does not use anymore the phy-is-integrated property.\n> So now, the mdio-mux must always enable the internal mdio when switch_fn ask for it and so reset MAC and so need to enable ephy clk/reset.\n> But for this I need a reference to thoses clock and reset. (this is done in get_ephy_nodes)\n> The current version set those clock in mdio-mux node, and as you can see it is already ugly (lots of get next node),\n> if the clk/rst nodes were as it should be, in phy nodes, it will be more bad.\n> \n> So, since the MAC have a dependency on thoses clk/rst nodes for\n> doing reset(), I seek a proper way to get references on it.\n>\n> OR do you agree that putting ephy clk/rst in emac is acceptable ?\n\nWhy not just parsing the DT child nodes looking for resets and clocks\nproperties? The usual PHY don't have that.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9tC20WKKz9t5Q\n\tfor ;\n\tTue, 10 Oct 2017 08:08:46 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755257AbdJIVIf (ORCPT );\n\tMon, 9 Oct 2017 17:08:35 -0400","from mail.free-electrons.com ([62.4.15.54]:45210 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754530AbdJIVId (ORCPT\n\t); Mon, 9 Oct 2017 17:08:33 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid C9A2A207D4; Mon, 9 Oct 2017 23:08:30 +0200 (CEST)","from localhost (LFbn-TOU-1-209-191.w86-201.abo.wanadoo.fr\n\t[86.201.56.191])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 9EE2E2076D;\n\tMon, 9 Oct 2017 23:08:30 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 9 Oct 2017 23:08:31 +0200","From":"Maxime Ripard ","To":"Corentin Labbe ","Cc":"Andrew Lunn , robh+dt@kernel.org, wens@csie.org,\n\tf.fainelli@gmail.com, mark.rutland@arm.com, linux@armlinux.org.uk,\n\tcatalin.marinas@arm.com, will.deacon@arm.com,\n\tpeppe.cavallaro@st.com, alexandre.torgue@st.com,\n\tfrowand.list@gmail.com, netdev@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update\n\tdocumentation about integrated PHY","Message-ID":"<20171009210831.qc2cgxr4cx2qz5x7@flea.home>","References":"<20170927073414.17361-1-clabbe.montjoie@gmail.com>\n\t<20170927073414.17361-6-clabbe.montjoie@gmail.com>\n\t<20170927140210.GE13516@lunn.ch> <20170928073708.GB32676@Red>\n\t<20171008183340.GA21531@Red>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"mrd4h4xx4avcyvdw\"","Content-Disposition":"inline","In-Reply-To":"<20171008183340.GA21531@Red>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}}]