[{"id":1776067,"web_url":"http://patchwork.ozlabs.org/comment/1776067/","msgid":"<20170927085318.0670a849@xps13>","list_archive_url":null,"date":"2017-09-27T06:53:18","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hello Kalyan,\n\nOn Wed, 27 Sep 2017 13:55:16 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741.\n> \n> This commit sets the FORCE_CSX bit to 1 for all\n> ARMADA370 variants as the arbitration is always enabled by default.\n\nMaybe you could mention here that this does not apply for pxa3xx\nvariant as this bit does not exist/is reserved on the NFCv1.\n\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n> drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n> 1 file changed, 7 insertions(+)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -68,6 +68,7 @@\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> #define NDCR_ND_MODE\t\t(0x3 << 21)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_NAND_MODE \t(0x0)\n\nThe three lines above seems to have the same purpose.\nI had a look to the specs (pxa/370/375/xp/380/390), and I could\nnot find any reference to a valid bit 22 in NDCR (it is always\nreserved). Maybe you could delete NDCR_ND_MODE and\nNDCR_NAND_MODE then ?\n\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\n> 0;\n> +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n> Ref#: GL-5830741*/\n\nYou miss a space between \"GL-5830741\" and \"*/\".\n\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> NDCR_ND_ARB_EN : 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> GL-5830741*/\n\nSame here.\n\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }\n\n\nThanks,\nMiquèl","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"NCe6i9UD\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y27pL2KFWz9t3x\n\tfor ;\n\tWed, 27 Sep 2017 16:54:02 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx6E7-0001SP-Rh; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_235343_326225_646E7E6C ","X-CRM114-Status":"GOOD ( 16.52 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, boris.brezillon@free-electrons.com,\n\tdevicetree@vger.kernel.org, richard@nod.at,\n\tchris.packham@alliedtelesis.co.nz, \n\tlinux-kernel@vger.kernel.org, marek.vasut@gmail.com, robh+dt@kernel.org, \n\tlinux-mtd@lists.infradead.org, ezequiel.garcia@free-electrons.com,\n\tcyrille.pitchen@wedev4u.fr, computersforpeace@gmail.com,\n\tdwmw2@infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1776173,"web_url":"http://patchwork.ozlabs.org/comment/1776173/","msgid":"<20170927111547.3536eb2b@xps13>","list_archive_url":null,"date":"2017-09-27T09:15:47","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"On Wed, 27 Sep 2017 08:53:18 +0200\nMiquel RAYNAL wrote:\n\n> Hello Kalyan,\n> \n> On Wed, 27 Sep 2017 13:55:16 +1300\n> Kalyan Kinthada wrote:\n> \n> > When the arbitration between NOR and NAND flash is enabled\n> > the field bit[21] in the Data Flash Control Register\n> > needs to be set to 1 according to guidleine GL-5830741.\n\nI forgot to ask you what is this guideline ? Is this a Marvell\ndocument ? I could not find it. The functional spec clearly states:\n\"When NOR/NAND hardware arbiter enabled, this bit must be set\" but as\nyou mention it in the commit log and in the code it is worth knowing\nwhat your are referring to.\n\nAlso, could you test if this bit introduces a regression or a speed\npenalty when using for instance only one NAND chip (so not using\nthe arbiter even if it is enabled) ?\n\nTo do so you may use the flash_speed tool from the mtd-utils package:\nhttp://lists.infradead.org/pipermail/linux-mtd/2017-August/076477.html\n\nThank you,\nMiquèl\n\n> > \n> > This commit sets the FORCE_CSX bit to 1 for all\n> > ARMADA370 variants as the arbitration is always enabled by\n> > default. \n> \n> Maybe you could mention here that this does not apply for pxa3xx\n> variant as this bit does not exist/is reserved on the NFCv1.\n> \n> > \n> > Signed-off-by: Kalyan Kinthada \n> > ---\n> > drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n> > 1 file changed, 7 insertions(+)\n> > \n> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> > b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n> > 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> > +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> > @@ -68,6 +68,7 @@\n> > #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> > #define NDCR_NCSX\t\t(0x1 << 23)\n> > #define NDCR_ND_MODE\t\t(0x3 << 21)\n> > +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> > #define NDCR_NAND_MODE \t(0x0) \n> \n> The three lines above seems to have the same purpose.\n> I had a look to the specs (pxa/370/375/xp/380/390), and I could\n> not find any reference to a valid bit 22 in NDCR (it is always\n> reserved). Maybe you could delete NDCR_ND_MODE and\n> NDCR_NAND_MODE then ?\n> \n> > #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> > #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> > @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n> > pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> > \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> > \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n> > NDCR_ND_ARB_EN : 0;\n> > +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n> > Ref#: GL-5830741*/ \n> \n> You miss a space between \"GL-5830741\" and \"*/\".\n> \n> > +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> > +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> > \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> > \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> > \n> > @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n> > pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> > \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> > NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> > NDCR_ND_ARB_EN : 0;\n> > +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> > GL-5830741*/ \n> \n> Same here.\n> \n> > +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> > +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> > \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> > \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> > } \n> \n> \n> Thanks,\n> Miquèl\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"glOiNK0V\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2ByY47lbz9tXp\n\tfor ;\n\tWed, 27 Sep 2017 19:16:21 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx8Rx-0004ze-8s; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_021609_686783_BC491BAA ","X-CRM114-Status":"GOOD ( 22.05 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, boris.brezillon@free-electrons.com,\n\tdevicetree@vger.kernel.org, richard@nod.at,\n\tchris.packham@alliedtelesis.co.nz, \n\tlinux-kernel@vger.kernel.org, marek.vasut@gmail.com, robh+dt@kernel.org, \n\tlinux-mtd@lists.infradead.org, ezequiel.garcia@free-electrons.com,\n\tcyrille.pitchen@wedev4u.fr, computersforpeace@gmail.com,\n\tdwmw2@infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1776647,"web_url":"http://patchwork.ozlabs.org/comment/1776647/","msgid":"","list_archive_url":null,"date":"2017-09-27T21:53:39","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","submitter":{"id":27499,"url":"http://patchwork.ozlabs.org/api/people/27499/","name":"Chris Packham","email":"chris.packham@alliedtelesis.co.nz"},"content":"Hi Miquel,\n\nOn 27/09/17 22:16, Miquel RAYNAL wrote:\n> On Wed, 27 Sep 2017 08:53:18 +0200\n> Miquel RAYNAL wrote:\n> \n>> Hello Kalyan,\n>>\n>> On Wed, 27 Sep 2017 13:55:16 +1300\n>> Kalyan Kinthada wrote:\n>>\n>>> When the arbitration between NOR and NAND flash is enabled\n>>> the field bit[21] in the Data Flash Control Register\n>>> needs to be set to 1 according to guidleine GL-5830741.\n> \n> I forgot to ask you what is this guideline ? Is this a Marvell\n> document ? I could not find it. The functional spec clearly states:\n> \"When NOR/NAND hardware arbiter enabled, this bit must be set\" but as\n> you mention it in the commit log and in the code it is worth knowing\n> what your are referring to.\n\nThe guideline number is from a Marvell Errata document MV-S501377-00, \nalthough this specific change is a guideline not an erratum. You'll need \naccess to Marvell's extranet (with appropriate NDAs etc) to retrieve it. \nWe can mention the document reference in the commit message for v3.\n\n> Also, could you test if this bit introduces a regression or a speed\n> penalty when using for instance only one NAND chip (so not using\n> the arbiter even if it is enabled) ?\n> \n> To do so you may use the flash_speed tool from the mtd-utils package:\n> http://lists.infradead.org/pipermail/linux-mtd/2017-August/076477.html\n\nWe haven't run flash_speed (yet) but anecdotally we've seen no \nnoticeable performance difference.\n\n> \n> Thank you,\n> Miquèl\n> \n>>>\n>>> This commit sets the FORCE_CSX bit to 1 for all\n>>> ARMADA370 variants as the arbitration is always enabled by\n>>> default.\n>>\n>> Maybe you could mention here that this does not apply for pxa3xx\n>> variant as this bit does not exist/is reserved on the NFCv1.\n>>\n>>>\n>>> Signed-off-by: Kalyan Kinthada \n>>> ---\n>>> drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n>>> 1 file changed, 7 insertions(+)\n>>>\n>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n>>> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n>>> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n>>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n>>> @@ -68,6 +68,7 @@\n>>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n>>> #define NDCR_NCSX\t\t(0x1 << 23)\n>>> #define NDCR_ND_MODE\t\t(0x3 << 21)\n>>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n>>> #define NDCR_NAND_MODE \t(0x0)\n>>\n>> The three lines above seems to have the same purpose.\n>> I had a look to the specs (pxa/370/375/xp/380/390), and I could\n>> not find any reference to a valid bit 22 in NDCR (it is always\n>> reserved). Maybe you could delete NDCR_ND_MODE and\n>> NDCR_NAND_MODE then ?\n>>\n>>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n>>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n>>> @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n>>> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n>>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n>>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n>>> NDCR_ND_ARB_EN : 0;\n>>> +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n>>> Ref#: GL-5830741*/\n>>\n>> You miss a space between \"GL-5830741\" and \"*/\".\n>>\n>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n>>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n>>> \n>>> @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n>>> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n>>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n>>> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n>>> NDCR_ND_ARB_EN : 0;\n>>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n>>> GL-5830741*/\n>>\n>> Same here.\n>>\n>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n>>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n>>> }\n>>\n>>\n>> Thanks,\n>> Miquèl\n>>\n> \n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"npLuBbd3\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz header.b=\"Y90ZdihW\"; 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