[{"id":1775205,"web_url":"http://patchwork.ozlabs.org/comment/1775205/","msgid":"<20170926091852.196f647d@xps13>","list_archive_url":null,"date":"2017-09-26T07:18:52","subject":"Re: [PATCH 2/2] mtd: nand: pxa3xx: Handle \"marvell, nand-force-csx\"\n\tcompatible string","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hi Kalyan,\n\nOn Tue, 26 Sep 2017 17:17:00 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741.\n\nI do agree, the driver lacks the support of this bit, which\nlooks important when you effectively use the arbiter.\nNevertheless:\n\n- On PXA (marvell,pxa3xx-nand compatible), there is a ND_ARB_EN bit to\n enable or disable the arbiter, but there is no FORCE_CSX bit (bit 21\n of NDCR, the so called Control Register, is reserved).\n- On Armada (marvell,armada370-nand), there is a FORCE_CSX bit, but\n there is no ND_ARB_EN bit in the NDCR (moved to system registers) and\n the arbitration is always enabled by default.\n\nI guess you should always set the FORCE_CSX bit when using the armada\ncompatible, because it is harmless, right? Thus, you could get rid\nof the new DT property.\n\nThank you,\nMiquèl\n\n> \n> This commit sets the FORCE_CSX bit to 1 if the compatible\n> string \"marvell,nand-force-csx\" is enabled in the device tree\n> of the corresponding boards.\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n> drivers/mtd/nand/pxa3xx_nand.c | 6 ++++++\n> include/linux/platform_data/mtd-nand-pxa3xx.h | 3 +++\n> 2 files changed, 9 insertions(+)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..4ad1f0601930\n> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -68,6 +68,7 @@\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> #define NDCR_ND_MODE\t\t(0x3 << 21)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_NAND_MODE \t(0x0)\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> @@ -1464,6 +1465,7 @@ static int pxa3xx_nand_config_ident(struct\n> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\n> 0;\n> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1500,7 @@ static void pxa3xx_nand_detect_config(struct\n> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> NDCR_ND_ARB_EN : 0;\n> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }\n> @@ -1936,6 +1939,9 @@ static int pxa3xx_nand_probe_dt(struct\n> platform_device *pdev) pdata->enable_arbiter = 1;\n> \tif (of_get_property(np, \"marvell,nand-keep-config\", NULL))\n> \t\tpdata->keep_config = 1;\n> +\tif (of_get_property(np, \"marvell,nand-force-csx\", NULL))\n> +\t\t/* Ref#: GL-5830741 */\n> +\t\tpdata->force_csx = 1;\n> \tof_property_read_u32(np, \"num-cs\", &pdata->num_cs);\n> \n> \tpdev->dev.platform_data = pdata;\n> diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h\n> b/include/linux/platform_data/mtd-nand-pxa3xx.h index\n> 394d15597dc7..e7f2c8647c0e 100644 ---\n> a/include/linux/platform_data/mtd-nand-pxa3xx.h +++\n> b/include/linux/platform_data/mtd-nand-pxa3xx.h @@ -28,6 +28,9 @@\n> struct pxa3xx_nand_platform_data { /* allow platform code to keep\n> OBM/bootloader defined NFC config */ int\tkeep_config;\n> \n> +\t/* Force chip select false on busy */\n> +\tint\tforce_csx;\n> +\n> \t/* indicate how many chip selects will be used */\n> \tint\tnum_cs;\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_001915_126750_3F0E0ED3 ","X-CRM114-Status":"GOOD ( 20.73 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, boris.brezillon@free-electrons.com,\n\tdevicetree@vger.kernel.org, richard@nod.at,\n\tchris.packham@alliedtelesis.co.nz, \n\tlinux-kernel@vger.kernel.org, marek.vasut@gmail.com, robh+dt@kernel.org, \n\tlinux-mtd@lists.infradead.org, ezequiel.garcia@free-electrons.com,\n\tcyrille.pitchen@wedev4u.fr, computersforpeace@gmail.com,\n\tdwmw2@infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1775970,"web_url":"http://patchwork.ozlabs.org/comment/1775970/","msgid":"<7493494e-23f6-feed-73e7-59d6819d98db@alliedtelesis.co.nz>","list_archive_url":null,"date":"2017-09-27T00:54:05","subject":"Re: [PATCH 2/2] mtd: nand: pxa3xx: Handle \"marvell, nand-force-csx\"\n\tcompatible string","submitter":{"id":72417,"url":"http://patchwork.ozlabs.org/api/people/72417/","name":"Kalyan Kinthada","email":"kalyan.kinthada@alliedtelesis.co.nz"},"content":"On 26/09/17 20:18, Miquel RAYNAL wrote:\r\n> Hi Kalyan,\r\n>\r\n> On Tue, 26 Sep 2017 17:17:00 +1300\r\n> Kalyan Kinthada wrote:\r\n>\r\n>> When the arbitration between NOR and NAND flash is enabled\r\n>> the field bit[21] in the Data Flash Control Register\r\n>> needs to be set to 1 according to guidleine GL-5830741.\r\n> I do agree, the driver lacks the support of this bit, which\r\n> looks important when you effectively use the arbiter.\r\n> Nevertheless:\r\n>\r\n> - On PXA (marvell,pxa3xx-nand compatible), there is a ND_ARB_EN bit to\r\n> enable or disable the arbiter, but there is no FORCE_CSX bit (bit 21\r\n> of NDCR, the so called Control Register, is reserved).\r\n> - On Armada (marvell,armada370-nand), there is a FORCE_CSX bit, but\r\n> there is no ND_ARB_EN bit in the NDCR (moved to system registers) and\r\n> the arbitration is always enabled by default.\r\n>\r\n> I guess you should always set the FORCE_CSX bit when using the armada\r\n> compatible, because it is harmless, right? Thus, you could get rid\r\n> of the new DT property.\r\nOk. I will make changes to the driver to set FORCE_CSX bit for all\r\nvariants of ARMADA370 variants instead of creating a new compatible\r\nstring.\r\n\r\nI will send a new patch. Kindly ignore these changes.\r\nThanks for your time Miquel.\r\n\r\nThank You,\r\nKalyan\r\n>\r\n> Thank you,\r\n> Miquèl\r\n>\r\n>> This commit sets the FORCE_CSX bit to 1 if the compatible\r\n>> string \"marvell,nand-force-csx\" is enabled in the device tree\r\n>> of the corresponding boards.\r\n>>\r\n>> Signed-off-by: Kalyan Kinthada \r\n>> ---\r\n>> drivers/mtd/nand/pxa3xx_nand.c | 6 ++++++\r\n>> include/linux/platform_data/mtd-nand-pxa3xx.h | 3 +++\r\n>> 2 files changed, 9 insertions(+)\r\n>>\r\n>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\r\n>> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..4ad1f0601930\r\n>> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\r\n>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\r\n>> @@ -68,6 +68,7 @@\r\n>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\r\n>> #define NDCR_NCSX\t\t(0x1 << 23)\r\n>> #define NDCR_ND_MODE\t\t(0x3 << 21)\r\n>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\r\n>> #define NDCR_NAND_MODE \t(0x0)\r\n>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\r\n>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\r\n>> @@ -1464,6 +1465,7 @@ static int pxa3xx_nand_config_ident(struct\r\n>> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\r\n>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\r\n>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\r\n>> 0;\r\n>> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\r\n>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\r\n>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\r\n>> \r\n>> @@ -1498,6 +1500,7 @@ static void pxa3xx_nand_detect_config(struct\r\n>> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\r\n>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\r\n>> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\r\n>> NDCR_ND_ARB_EN : 0;\r\n>> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\r\n>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\r\n>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\r\n>> }\r\n>> @@ -1936,6 +1939,9 @@ static int pxa3xx_nand_probe_dt(struct\r\n>> platform_device *pdev) pdata->enable_arbiter = 1;\r\n>> \tif (of_get_property(np, \"marvell,nand-keep-config\", NULL))\r\n>> \t\tpdata->keep_config = 1;\r\n>> +\tif (of_get_property(np, \"marvell,nand-force-csx\", NULL))\r\n>> +\t\t/* Ref#: GL-5830741 */\r\n>> +\t\tpdata->force_csx = 1;\r\n>> \tof_property_read_u32(np, \"num-cs\", &pdata->num_cs);\r\n>> \r\n>> \tpdev->dev.platform_data = pdata;\r\n>> diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h\r\n>> b/include/linux/platform_data/mtd-nand-pxa3xx.h index\r\n>> 394d15597dc7..e7f2c8647c0e 100644 ---\r\n>> a/include/linux/platform_data/mtd-nand-pxa3xx.h +++\r\n>> b/include/linux/platform_data/mtd-nand-pxa3xx.h @@ -28,6 +28,9 @@\r\n>> struct pxa3xx_nand_platform_data { /* allow platform code to keep\r\n>> OBM/bootloader defined NFC config */ int\tkeep_config;\r\n>> \r\n>> +\t/* Force chip select false on busy */\r\n>> +\tint\tforce_csx;\r\n>> +\r\n>> \t/* indicate how many chip selects will be used */\r\n>> \tint\tnum_cs;\r\n>> \r\n>\r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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