[{"id":1775330,"web_url":"http://patchwork.ozlabs.org/comment/1775330/","msgid":"<20170926100109.GX6290@tbergstrom-lnx.Nvidia.com>","list_archive_url":null,"date":"2017-09-26T10:01:09","subject":"Re: [PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on\n\tTegra20","submitter":{"id":9849,"url":"http://patchwork.ozlabs.org/api/people/9849/","name":"Peter De Schrijver","email":"pdeschrijver@nvidia.com"},"content":"On Tue, Sep 26, 2017 at 02:22:03AM +0300, Dmitry Osipenko wrote:\n> AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate\n> results in an increased DMA transfer rate.\n> \n> Signed-off-by: Dmitry Osipenko \n\nAcked-By: Peter De Schrijver \n\n> ---\n> drivers/clk/tegra/clk-tegra20.c | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\n> index e76c0d292ca7..c511716093e2 100644\n> --- a/drivers/clk/tegra/clk-tegra20.c\n> +++ b/drivers/clk/tegra/clk-tegra20.c\n> @@ -1031,7 +1031,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {\n> \t{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },\n> \t{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },\n> \t{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },\n> -\t{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },\n> +\t{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },\n> \t{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },\n> \t{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },\n> \t{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },\n> -- \n> 2.14.1\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-tegra\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1c4H1J57z9tXc\n\tfor ;\n\tTue, 26 Sep 2017 20:04:15 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934942AbdIZKEC (ORCPT );\n\tTue, 26 Sep 2017 06:04:02 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:17429 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S934122AbdIZKEA (ORCPT\n\t);\n\tTue, 26 Sep 2017 06:04:00 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid ; Tue, 26 Sep 2017 03:03:37 -0700","from HQMAIL105.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 26 Sep 2017 03:03:39 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com\n\t(172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 26 Sep 2017 10:01:14 +0000","from tbergstrom-lnx.Nvidia.com (10.21.24.170) by\n\tUKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS)\n\tid 15.0.1293.2; Tue, 26 Sep 2017 10:01:11 +0000","by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1002)\n\tid B22AEF805F4; Tue, 26 Sep 2017 13:01:09 +0300 (EEST)"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 26 Sep 2017 03:03:39 -0700","Date":"Tue, 26 Sep 2017 13:01:09 +0300","From":"Peter De Schrijver ","To":"Dmitry Osipenko ","CC":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\t\"Prashant Gaikwad\" ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\t\"Vinod Koul\" , ,\n\t, ,\n\t, ","Subject":"Re: [PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on\n\tTegra20","Message-ID":"<20170926100109.GX6290@tbergstrom-lnx.Nvidia.com>","References":"\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Disposition":"inline","In-Reply-To":"","X-NVConfidentiality":"public","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[10.21.24.170]","X-ClientProxiedBy":"UKMAIL101.nvidia.com (10.26.138.13) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]