[{"id":1775602,"web_url":"http://patchwork.ozlabs.org/comment/1775602/","msgid":"","list_archive_url":null,"date":"2017-09-26T14:50:03","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 26/09/17 00:22, Dmitry Osipenko wrote:\n> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n> on Tegra20/30 SoC's.\n> \n> Signed-off-by: Dmitry Osipenko \n> ---\n> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n> 1 file changed, 23 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> \n> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> new file mode 100644\n> index 000000000000..2af9aa76ae11\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> @@ -0,0 +1,23 @@\n> +* NVIDIA Tegra AHB DMA controller\n> +\n> +Required properties:\n> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n> +- reg:\t\tShould contain registers base address and length.\n> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n> +- clocks:\tShould contain one entry, DMA controller clock.\n> +- resets :\tShould contain one entry, DMA controller reset.\n> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n> +\t\tdocumentation, in particular AHB DMA channel control register\n> +\t\tREQ_SEL field.\n\nWhat about the TRIG_SEL field? Do we need to handle this here as well?\n\nCheers\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1kSX30KLz9t1G\n\tfor ;\n\tWed, 27 Sep 2017 00:52:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S969660AbdIZOwL (ORCPT );\n\tTue, 26 Sep 2017 10:52:11 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:4319 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S967571AbdIZOwJ (ORCPT\n\t); Tue, 26 Sep 2017 10:52:09 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid ; Tue, 26 Sep 2017 07:51:47 -0700","from HQMAIL101.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 26 Sep 2017 07:51:49 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 26 Sep 2017 14:50:09 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 26 Sep 2017 14:50:06 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 26 Sep 2017 07:51:49 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\t\"Peter De Schrijver\" ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>","From":"Jon Hunter ","Message-ID":"","Date":"Tue, 26 Sep 2017 15:50:03 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL102.nvidia.com (10.26.138.15) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775627,"web_url":"http://patchwork.ozlabs.org/comment/1775627/","msgid":"<91112d33-2fd3-cb1c-a1db-5e5be9540d68@gmail.com>","list_archive_url":null,"date":"2017-09-26T15:16:50","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 26.09.2017 17:50, Jon Hunter wrote:\n> \n> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>> on Tegra20/30 SoC's.\n>>\n>> Signed-off-by: Dmitry Osipenko \n>> ---\n>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>> 1 file changed, 23 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>\n>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> new file mode 100644\n>> index 000000000000..2af9aa76ae11\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> @@ -0,0 +1,23 @@\n>> +* NVIDIA Tegra AHB DMA controller\n>> +\n>> +Required properties:\n>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>> +- reg:\t\tShould contain registers base address and length.\n>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>> +- clocks:\tShould contain one entry, DMA controller clock.\n>> +- resets :\tShould contain one entry, DMA controller reset.\n>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>> +\t\tdocumentation, in particular AHB DMA channel control register\n>> +\t\tREQ_SEL field.\n> \n> What about the TRIG_SEL field? Do we need to handle this here as well?\n> \n\nI've followed APB DMA here, that HW also has TRIG_SEL but ignores it for some\nreason. I think technically it should be present in the binding, yeah.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"gahnFRxQ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1l174qxjz9t3x\n\tfor ;\n\tWed, 27 Sep 2017 01:16:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S965161AbdIZPQ5 (ORCPT );\n\tTue, 26 Sep 2017 11:16:57 -0400","from mail-lf0-f67.google.com ([209.85.215.67]:36724 \"EHLO\n\tmail-lf0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S935062AbdIZPQz (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775986,"web_url":"http://patchwork.ozlabs.org/comment/1775986/","msgid":"<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>","list_archive_url":null,"date":"2017-09-27T01:57:06","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 26.09.2017 17:50, Jon Hunter wrote:\n> \n> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>> on Tegra20/30 SoC's.\n>>\n>> Signed-off-by: Dmitry Osipenko \n>> ---\n>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>> 1 file changed, 23 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>\n>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> new file mode 100644\n>> index 000000000000..2af9aa76ae11\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> @@ -0,0 +1,23 @@\n>> +* NVIDIA Tegra AHB DMA controller\n>> +\n>> +Required properties:\n>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>> +- reg:\t\tShould contain registers base address and length.\n>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>> +- clocks:\tShould contain one entry, DMA controller clock.\n>> +- resets :\tShould contain one entry, DMA controller reset.\n>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>> +\t\tdocumentation, in particular AHB DMA channel control register\n>> +\t\tREQ_SEL field.\n> \n> What about the TRIG_SEL field? Do we need to handle this here as well?\n> \n\nActually, DMA transfer trigger isn't related a hardware description. It's up to\nsoftware to decide what trigger to select. So it shouldn't be in the binding.\n\nAnd I think the same applies to requester... any objections?","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"tSmtvghD\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y21DH4XDdz9t3x\n\tfor ;\n\tWed, 27 Sep 2017 11:57:35 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1033291AbdI0B5c (ORCPT\n\t);\n\tTue, 26 Sep 2017 21:57:32 -0400","from mail-lf0-f66.google.com ([209.85.215.66]:34357 \"EHLO\n\tmail-lf0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1033069AbdI0B5K (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776124,"web_url":"http://patchwork.ozlabs.org/comment/1776124/","msgid":"<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","list_archive_url":null,"date":"2017-09-27T08:34:37","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 27/09/17 02:57, Dmitry Osipenko wrote:\n> On 26.09.2017 17:50, Jon Hunter wrote:\n>>\n>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>> on Tegra20/30 SoC's.\n>>>\n>>> Signed-off-by: Dmitry Osipenko \n>>> ---\n>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>> 1 file changed, 23 insertions(+)\n>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>\n>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>> new file mode 100644\n>>> index 000000000000..2af9aa76ae11\n>>> --- /dev/null\n>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>> @@ -0,0 +1,23 @@\n>>> +* NVIDIA Tegra AHB DMA controller\n>>> +\n>>> +Required properties:\n>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>> +- reg:\t\tShould contain registers base address and length.\n>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>> +\t\tREQ_SEL field.\n>>\n>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>\n> \n> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n> software to decide what trigger to select. So it shouldn't be in the binding.\n\nI think it could be, if say a board wanted a GPIO to trigger a transfer.\n\n> And I think the same applies to requester... any objections?\n\nWell, the REQ_SEL should definitely be in the binding.\n\nLaxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\nlike we never bothered with it for the APB DMA and so maybe no ones uses\nthis.\n\nCheers\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2B3k6zlpz9t3x\n\tfor ;\n\tWed, 27 Sep 2017 18:35:46 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752319AbdI0Ifo (ORCPT\n\t);\n\tWed, 27 Sep 2017 04:35:44 -0400","from hqemgate14.nvidia.com ([216.228.121.143]:13252 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752306AbdI0Ifm (ORCPT\n\t); Wed, 27 Sep 2017 04:35:42 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid ; Wed, 27 Sep 2017 01:35:25 -0700","from HQMAIL104.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 01:35:30 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 08:34:41 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 08:34:37 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Wed, 27 Sep 2017 01:35:30 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\t\"Peter De Schrijver\" ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>","From":"Jon Hunter ","Message-ID":"<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","Date":"Wed, 27 Sep 2017 09:34:37 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL102.nvidia.com (10.26.138.15) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776292,"web_url":"http://patchwork.ozlabs.org/comment/1776292/","msgid":"<69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4@gmail.com>","list_archive_url":null,"date":"2017-09-27T12:12:50","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 27.09.2017 11:34, Jon Hunter wrote:\n> \n> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>\n>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>> on Tegra20/30 SoC's.\n>>>>\n>>>> Signed-off-by: Dmitry Osipenko \n>>>> ---\n>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>>> 1 file changed, 23 insertions(+)\n>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>\n>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>> new file mode 100644\n>>>> index 000000000000..2af9aa76ae11\n>>>> --- /dev/null\n>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>> @@ -0,0 +1,23 @@\n>>>> +* NVIDIA Tegra AHB DMA controller\n>>>> +\n>>>> +Required properties:\n>>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>>> +- reg:\t\tShould contain registers base address and length.\n>>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>>> +\t\tREQ_SEL field.\n>>>\n>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>\n>>\n>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>> software to decide what trigger to select. So it shouldn't be in the binding.\n> \n> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n> \n\nGPIO isn't a very good example, there is no \"GPIO\" trigger. To me all triggers\nare software-defined, so that software could create transfer chains.\n\n>> And I think the same applies to requester... any objections?\n> \n> Well, the REQ_SEL should definitely be in the binding.\n> \n\nOkay.\n\n> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n> like we never bothered with it for the APB DMA and so maybe no ones uses\n> this.\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"adz7LuZN\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2GtM3Jg0z9tXf\n\tfor ;\n\tWed, 27 Sep 2017 22:12:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752667AbdI0MM5 (ORCPT\n\t);\n\tWed, 27 Sep 2017 08:12:57 -0400","from mail-wr0-f195.google.com ([209.85.128.195]:37592 \"EHLO\n\tmail-wr0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752546AbdI0MMz (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776361,"web_url":"http://patchwork.ozlabs.org/comment/1776361/","msgid":"<96f28cc6-7cbf-308f-bc87-d96d3e7fe045@nvidia.com>","list_archive_url":null,"date":"2017-09-27T13:44:38","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 27/09/17 13:12, Dmitry Osipenko wrote:\n> On 27.09.2017 11:34, Jon Hunter wrote:\n>>\n>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>\n>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>> on Tegra20/30 SoC's.\n>>>>>\n>>>>> Signed-off-by: Dmitry Osipenko \n>>>>> ---\n>>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>>>> 1 file changed, 23 insertions(+)\n>>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>\n>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>> new file mode 100644\n>>>>> index 000000000000..2af9aa76ae11\n>>>>> --- /dev/null\n>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>> @@ -0,0 +1,23 @@\n>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>> +\n>>>>> +Required properties:\n>>>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>>>> +- reg:\t\tShould contain registers base address and length.\n>>>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>>>> +\t\tREQ_SEL field.\n>>>>\n>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>\n>>>\n>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>\n>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>\n> \n> GPIO isn't a very good example, there is no \"GPIO\" trigger. To me all triggers\n> are software-defined, so that software could create transfer chains.\n\nTRM shows the following in the APBDMA_TRIG_REG_0 ...\n\n\"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)\"\n\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Jx96zQPz9sRm\n\tfor ;\n\tWed, 27 Sep 2017 23:45:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753037AbdI0NpV (ORCPT\n\t);\n\tWed, 27 Sep 2017 09:45:21 -0400","from hqemgate14.nvidia.com ([216.228.121.143]:18125 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752406AbdI0NpT (ORCPT\n\t); Wed, 27 Sep 2017 09:45:19 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid ; Wed, 27 Sep 2017 06:44:52 -0700","from HQMAIL104.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 06:44:57 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 13:44:43 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 13:44:40 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Wed, 27 Sep 2017 06:44:57 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\t\"Peter De Schrijver\" ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4@gmail.com>","From":"Jon Hunter ","Message-ID":"<96f28cc6-7cbf-308f-bc87-d96d3e7fe045@nvidia.com>","Date":"Wed, 27 Sep 2017 14:44:38 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4@gmail.com>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL102.nvidia.com (10.26.138.15) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776367,"web_url":"http://patchwork.ozlabs.org/comment/1776367/","msgid":"<432fff47-6750-08c4-a91d-1a5d154245bc@nvidia.com>","list_archive_url":null,"date":"2017-09-27T13:46:11","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 27/09/17 14:44, Jon Hunter wrote:\n> \n> On 27/09/17 13:12, Dmitry Osipenko wrote:\n>> On 27.09.2017 11:34, Jon Hunter wrote:\n>>>\n>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>\n>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>> on Tegra20/30 SoC's.\n>>>>>>\n>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>> ---\n>>>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>>>>> 1 file changed, 23 insertions(+)\n>>>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>\n>>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>> new file mode 100644\n>>>>>> index 000000000000..2af9aa76ae11\n>>>>>> --- /dev/null\n>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>> @@ -0,0 +1,23 @@\n>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>> +\n>>>>>> +Required properties:\n>>>>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>>>>> +- reg:\t\tShould contain registers base address and length.\n>>>>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>>>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>>>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>>>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>>>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>>>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>>>>> +\t\tREQ_SEL field.\n>>>>>\n>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>\n>>>>\n>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>\n>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>\n>>\n>> GPIO isn't a very good example, there is no \"GPIO\" trigger. To me all triggers\n>> are software-defined, so that software could create transfer chains.\n> \n> TRM shows the following in the APBDMA_TRIG_REG_0 ...\n> \n> \"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)\"\n\nFurthermore there are timer and hw-semaphore triggers as well.\n\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2K0M08pRz9sRm\n\tfor ;\n\tWed, 27 Sep 2017 23:48:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932068AbdI0NsE (ORCPT );\n\tWed, 27 Sep 2017 09:48:04 -0400","from hqemgate14.nvidia.com ([216.228.121.143]:18223 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752949AbdI0NsB (ORCPT\n\t); Wed, 27 Sep 2017 09:48:01 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid ; Wed, 27 Sep 2017 06:47:24 -0700","from HQMAIL104.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 06:47:29 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 13:46:15 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 13:46:11 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Wed, 27 Sep 2017 06:47:29 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","From":"Jon Hunter ","To":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\t\"Peter De Schrijver\" ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4@gmail.com>\n\t<96f28cc6-7cbf-308f-bc87-d96d3e7fe045@nvidia.com>","Message-ID":"<432fff47-6750-08c4-a91d-1a5d154245bc@nvidia.com>","Date":"Wed, 27 Sep 2017 14:46:11 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<96f28cc6-7cbf-308f-bc87-d96d3e7fe045@nvidia.com>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL102.nvidia.com (10.26.138.15) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776392,"web_url":"http://patchwork.ozlabs.org/comment/1776392/","msgid":"","list_archive_url":null,"date":"2017-09-27T14:29:19","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 27.09.2017 16:46, Jon Hunter wrote:\n> \n> On 27/09/17 14:44, Jon Hunter wrote:\n>>\n>> On 27/09/17 13:12, Dmitry Osipenko wrote:\n>>> On 27.09.2017 11:34, Jon Hunter wrote:\n>>>>\n>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>\n>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>\n>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>> ---\n>>>>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>>>>>> 1 file changed, 23 insertions(+)\n>>>>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>\n>>>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>> new file mode 100644\n>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>> --- /dev/null\n>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>> +\n>>>>>>> +Required properties:\n>>>>>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>>>>>> +- reg:\t\tShould contain registers base address and length.\n>>>>>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>>>>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>>>>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>>>>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>>>>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>>>>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>>>>>> +\t\tREQ_SEL field.\n>>>>>>\n>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>\n>>>>>\n>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>\n>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>\n>>>\n>>> GPIO isn't a very good example, there is no \"GPIO\" trigger. To me all triggers\n>>> are software-defined, so that software could create transfer chains.\n>>\n>> TRM shows the following in the APBDMA_TRIG_REG_0 ...\n>>\n>> \"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)\"\n> \n> Furthermore there are timer and hw-semaphore triggers as well.\n> \n\nAha, I wasn't sure about what XRQ is. AHB DMA doesn't have XRQ.A as a trigger,\nbut XRQ.C/D which I suppose corresponds to GPIO C/D.\n\nTimer and hw-semaphore are more questionable, aren't semaphores software-only\ntriggerable?","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"N5EeOHky\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Kvv3qwLz9sBd\n\tfor ;\n\tThu, 28 Sep 2017 00:29:31 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932144AbdI0O33 (ORCPT );\n\tWed, 27 Sep 2017 10:29:29 -0400","from mail-wr0-f196.google.com ([209.85.128.196]:34075 \"EHLO\n\tmail-wr0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932141AbdI0O30 (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<432fff47-6750-08c4-a91d-1a5d154245bc@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776698,"web_url":"http://patchwork.ozlabs.org/comment/1776698/","msgid":"<20170927233240.GI457@codeaurora.org>","list_archive_url":null,"date":"2017-09-27T23:32:40","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/27, Jon Hunter wrote:\n> \n> \n> Well, the REQ_SEL should definitely be in the binding.\n> \n> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n\nWrong Stephen?","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"GYGPgS6Z\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"c40FtCPT\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Yyz13DDz9t6C\n\tfor ;\n\tThu, 28 Sep 2017 09:32:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752477AbdI0Xcp (ORCPT\n\t);\n\tWed, 27 Sep 2017 19:32:45 -0400","from smtp.codeaurora.org ([198.145.29.96]:35926 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752446AbdI0Xcm (ORCPT\n\t); Wed, 27 Sep 2017 19:32:42 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 124CD609F2; Wed, 27 Sep 2017 23:32:42 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 6116F609F2;\n\tWed, 27 Sep 2017 23:32:41 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506555162;\n\tbh=wsDop5h2WulKYSIGhNXFme5W965OjKasAghXPGBoJ+o=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=GYGPgS6ZgkNn8NwhUvmcB4iqs+LfNmOSwtcd7N+vs3qrEyO3LXr4GTgAC+tm/W3tg\n\tGjh1xPdgZTEbHTJhA9ww/6RvPwsFHvPTsO7cHmViPNfls9sfuX8VpPqIbs+SAWcFME\n\teMickBhBVM7F2riz3yfluJ3ggo13DWVAgGDhGHgI=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506555161;\n\tbh=wsDop5h2WulKYSIGhNXFme5W965OjKasAghXPGBoJ+o=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=c40FtCPTu3CHCVmeHeN0WaH5zl9vCn7hGmioGk4o026ND8EAG8raEjyektLsWvJV6\n\t8KdIwPWaplazpHNgjOjIVOEE/qCpyyOAKLQH0toVCwePocD27w1YyBYPwyFdrEp7ZM\n\tCTsR8QV+IeSsC0A2oKnexoNzdMmrTR/IriNK1uWg="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6116F609F2","Date":"Wed, 27 Sep 2017 16:32:40 -0700","From":"Stephen Boyd ","To":"Jon Hunter ","Cc":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tRob Herring ,\n\tVinod Koul , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","Message-ID":"<20170927233240.GI457@codeaurora.org>","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776864,"web_url":"http://patchwork.ozlabs.org/comment/1776864/","msgid":"<1748ef0f-3461-75c9-61fe-4cbe1fa66a9a@nvidia.com>","list_archive_url":null,"date":"2017-09-28T08:33:49","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 28/09/17 00:32, Stephen Boyd wrote:\n> On 09/27, Jon Hunter wrote:\n>>\n>>\n>> Well, the REQ_SEL should definitely be in the binding.\n>>\n>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n> \n> Wrong Stephen?\n\nIndeed! With all the folks in copy, I assumed we had the right one :-)\n\nCheers\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2p0J1dMWz9rxl\n\tfor ;\n\tThu, 28 Sep 2017 18:34:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752154AbdI1Iey (ORCPT\n\t);\n\tThu, 28 Sep 2017 04:34:54 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:18145 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751592AbdI1Iew (ORCPT\n\t); Thu, 28 Sep 2017 04:34:52 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid ; Thu, 28 Sep 2017 01:34:39 -0700","from HQMAIL103.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tThu, 28 Sep 2017 01:34:42 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL103.nvidia.com\n\t(172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tThu, 28 Sep 2017 08:33:54 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tThu, 28 Sep 2017 08:33:50 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Thu, 28 Sep 2017 01:34:42 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Stephen Boyd ","CC":"Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\t\"Peter De Schrijver\" ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tRob Herring , Vinod Koul , \n\t, ,\n\t, ,\n\t, Stephen Warren ","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<20170927233240.GI457@codeaurora.org>","From":"Jon Hunter ","Message-ID":"<1748ef0f-3461-75c9-61fe-4cbe1fa66a9a@nvidia.com>","Date":"Thu, 28 Sep 2017 09:33:49 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927233240.GI457@codeaurora.org>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL102.nvidia.com (10.26.138.15) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777738,"web_url":"http://patchwork.ozlabs.org/comment/1777738/","msgid":"<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>","list_archive_url":null,"date":"2017-09-29T19:30:51","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":12517,"url":"http://patchwork.ozlabs.org/api/people/12517/","name":"Stephen Warren","email":"swarren@wwwdotorg.org"},"content":"On 09/27/2017 02:34 AM, Jon Hunter wrote:\n> \n> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>\n>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>> on Tegra20/30 SoC's.\n>>>>\n>>>> Signed-off-by: Dmitry Osipenko \n>>>> ---\n>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>>>> 1 file changed, 23 insertions(+)\n>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>\n>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>> new file mode 100644\n>>>> index 000000000000..2af9aa76ae11\n>>>> --- /dev/null\n>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>> @@ -0,0 +1,23 @@\n>>>> +* NVIDIA Tegra AHB DMA controller\n>>>> +\n>>>> +Required properties:\n>>>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>>>> +- reg:\t\tShould contain registers base address and length.\n>>>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>>>> +- clocks:\tShould contain one entry, DMA controller clock.\n>>>> +- resets :\tShould contain one entry, DMA controller reset.\n>>>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>>>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>>>> +\t\tdocumentation, in particular AHB DMA channel control register\n>>>> +\t\tREQ_SEL field.\n>>>\n>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>\n>>\n>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>> software to decide what trigger to select. So it shouldn't be in the binding.\n> \n> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n> \n>> And I think the same applies to requester... any objections?\n> \n> Well, the REQ_SEL should definitely be in the binding.\n> \n> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n> like we never bothered with it for the APB DMA and so maybe no ones uses\n> this.\n\nI don't think TRIG_SEL should be in the binding, at least at present. \nWhile TRIG_SEL certainly is something used to configure the transfer, I \nbelieve the semantics of the current DMA binding only cover DMA \ntransfers that are initiated when SW desires, rather than being a \ncombination of after SW programs the transfer plus some other HW event. \nSo, we always use a default/hard-coded TRIG_SEL value. As such, there's \nno need for a TRIG_SEL value in DT. There's certainly no known use-case \nthat requires a non-default TRIG_SEL value at present. We could add an \nextra #dma-cells value later if we find a use for it, and the semantics \nof that use-case make sense to add it to the DMA specifier, rather than \nsome other separate higher-level property/driver/...\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y3hVn3mcGz9t42\n\tfor ;\n\tSat, 30 Sep 2017 05:30:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752280AbdI2Taz (ORCPT\n\t);\n\tFri, 29 Sep 2017 15:30:55 -0400","from avon.wwwdotorg.org ([104.237.132.123]:42476 \"EHLO\n\tavon.wwwdotorg.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751972AbdI2Tay (ORCPT\n\t); Fri, 29 Sep 2017 15:30:54 -0400","from [10.20.204.51] (thunderhill.nvidia.com [216.228.112.22])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby avon.wwwdotorg.org (Postfix) with ESMTPSA id 8DA261C03B8;\n\tFri, 29 Sep 2017 13:30:52 -0600 (MDT)"],"X-Virus-Status":"Clean","X-Virus-Scanned":"clamav-milter 0.99.2 at avon.wwwdotorg.org","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Jon Hunter , Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","Cc":"linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,\n\tdmaengine@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","From":"Stephen Warren ","Message-ID":"<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>","Date":"Fri, 29 Sep 2017 13:30:51 -0600","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-GB","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777856,"web_url":"http://patchwork.ozlabs.org/comment/1777856/","msgid":"<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>","list_archive_url":null,"date":"2017-09-30T03:11:07","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 29.09.2017 22:30, Stephen Warren wrote:\n> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>\n>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>\n>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>> on Tegra20/30 SoC's.\n>>>>>\n>>>>> Signed-off-by: Dmitry Osipenko \n>>>>> ---\n>>>>>   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>> ++++++++++++++++++++++\n>>>>>   1 file changed, 23 insertions(+)\n>>>>>   create mode 100644\n>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>\n>>>>> diff --git\n>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>> new file mode 100644\n>>>>> index 000000000000..2af9aa76ae11\n>>>>> --- /dev/null\n>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>> @@ -0,0 +1,23 @@\n>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>> +\n>>>>> +Required properties:\n>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>> +- reg:        Should contain registers base address and length.\n>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select value\n>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>> +        REQ_SEL field.\n>>>>\n>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>\n>>>\n>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>\n>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>\n>>> And I think the same applies to requester... any objections?\n>>\n>> Well, the REQ_SEL should definitely be in the binding.\n>>\n>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>> this.\n> \n> I don't think TRIG_SEL should be in the binding, at least at present. While\n> TRIG_SEL certainly is something used to configure the transfer, I believe the\n> semantics of the current DMA binding only cover DMA transfers that are initiated\n> when SW desires, rather than being a combination of after SW programs the\n> transfer plus some other HW event. So, we always use a default/hard-coded\n> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n> certainly no known use-case that requires a non-default TRIG_SEL value at\n> present. We could add an extra #dma-cells value later if we find a use for it,\n> and the semantics of that use-case make sense to add it to the DMA specifier,\n> rather than some other separate higher-level property/driver/...\n\nThank you for the comment. If we'd want to extend the binding further with the\ntrigger, how to differentiate trigger from the requester in a case of a single\n#data-cell?\n\nOf course realistically a chance that the further extension would be needed is\nvery-very low, so we may defer the efforts to solve that question and for now\nmake driver aware of the potential #dma-cells extension.\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"O/6CmgZD\"; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778464,"web_url":"http://patchwork.ozlabs.org/comment/1778464/","msgid":"<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>","list_archive_url":null,"date":"2017-10-02T17:05:11","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":12517,"url":"http://patchwork.ozlabs.org/api/people/12517/","name":"Stephen Warren","email":"swarren@wwwdotorg.org"},"content":"On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n> On 29.09.2017 22:30, Stephen Warren wrote:\n>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>\n>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>\n>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>> on Tegra20/30 SoC's.\n>>>>>>\n>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>> ---\n>>>>>>   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>> ++++++++++++++++++++++\n>>>>>>   1 file changed, 23 insertions(+)\n>>>>>>   create mode 100644\n>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>\n>>>>>> diff --git\n>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>> new file mode 100644\n>>>>>> index 000000000000..2af9aa76ae11\n>>>>>> --- /dev/null\n>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>> @@ -0,0 +1,23 @@\n>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>> +\n>>>>>> +Required properties:\n>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select value\n>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>> +        REQ_SEL field.\n>>>>>\n>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>\n>>>>\n>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to\n>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>\n>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>\n>>>> And I think the same applies to requester... any objections?\n>>>\n>>> Well, the REQ_SEL should definitely be in the binding.\n>>>\n>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>> this.\n>>\n>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>> when SW desires, rather than being a combination of after SW programs the\n>> transfer plus some other HW event. So, we always use a default/hard-coded\n>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>> present. We could add an extra #dma-cells value later if we find a use for it,\n>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>> rather than some other separate higher-level property/driver/...\n> \n> Thank you for the comment. If we'd want to extend the binding further with the\n> trigger, how to differentiate trigger from the requester in a case of a single\n> #data-cell?\n> \n> Of course realistically a chance that the further extension would be needed is\n> very-very low, so we may defer the efforts to solve that question and for now\n> make driver aware of the potential #dma-cells extension.\n\nThe request selector cell isn't optional, so is always present. If we \nlater add an optional trig_sel cell, we'll either have:\n\n#dma-cells=<1>: req_sel\n\nor:\n\n#dma-cells=<2>: req_sel, trig_sel\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5T7c13Y0z9t7v\n\tfor ;\n\tTue, 3 Oct 2017 04:05:32 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751305AbdJBRFW (ORCPT\n\t);\n\tMon, 2 Oct 2017 13:05:22 -0400","from avon.wwwdotorg.org ([104.237.132.123]:49298 \"EHLO\n\tavon.wwwdotorg.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750957AbdJBRFU (ORCPT\n\t); Mon, 2 Oct 2017 13:05:20 -0400","from [10.20.204.51] (thunderhill.nvidia.com [216.228.112.22])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby avon.wwwdotorg.org (Postfix) with ESMTPSA id 6168B1C05C7;\n\tMon, 2 Oct 2017 11:05:18 -0600 (MDT)"],"X-Virus-Status":"Clean","X-Virus-Scanned":"clamav-milter 0.99.2 at avon.wwwdotorg.org","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko , Jon Hunter ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","Cc":"linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,\n\tdmaengine@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>\n\t<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>","From":"Stephen Warren ","Message-ID":"<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>","Date":"Mon, 2 Oct 2017 11:05:11 -0600","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-GB","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778654,"web_url":"http://patchwork.ozlabs.org/comment/1778654/","msgid":"<795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com>","list_archive_url":null,"date":"2017-10-02T23:02:56","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 02.10.2017 20:05, Stephen Warren wrote:\n> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>\n>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>\n>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>\n>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>> ---\n>>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>> ++++++++++++++++++++++\n>>>>>>>    1 file changed, 23 insertions(+)\n>>>>>>>    create mode 100644\n>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>\n>>>>>>> diff --git\n>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>> new file mode 100644\n>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>> --- /dev/null\n>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>> +\n>>>>>>> +Required properties:\n>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>> value\n>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>> +        REQ_SEL field.\n>>>>>>\n>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>\n>>>>>\n>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>> up to\n>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>\n>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>\n>>>>> And I think the same applies to requester... any objections?\n>>>>\n>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>\n>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>> this.\n>>>\n>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>>> when SW desires, rather than being a combination of after SW programs the\n>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>> present. We could add an extra #dma-cells value later if we find a use for it,\n>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>> rather than some other separate higher-level property/driver/...\n>>\n>> Thank you for the comment. If we'd want to extend the binding further with the\n>> trigger, how to differentiate trigger from the requester in a case of a single\n>> #data-cell?\n>>\n>> Of course realistically a chance that the further extension would be needed is\n>> very-very low, so we may defer the efforts to solve that question and for now\n>> make driver aware of the potential #dma-cells extension.\n> \n> The request selector cell isn't optional, so is always present. If we later add\n> an optional trig_sel cell, we'll either have:\n> \n> #dma-cells=<1>: req_sel\n> \n> or:\n> \n> #dma-cells=<2>: req_sel, trig_sel\n\nWhy request sel. couldn't be optional? Could you please elaborate a bit more?\n\nI think possible options are:\n\n#dma-cells=<1>: req_sel\n#dma-cells=<1>: trig_sel\n#dma-cells=<2>: req_sel, trig_sel\n\nThe only difference between request and trigger is that trigger issues the whole\ntransfer, while request only a single burst. Isn't it possible to have a case in\nHW for the \"trigger-only\" option? If not or it's a rareness, then I agree that\nREQ_SEL must be mandatory.\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"NOg5ROpe\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5d4R0wc7z9t5q\n\tfor ;\n\tTue, 3 Oct 2017 10:03:19 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751247AbdJBXDE (ORCPT\n\t);\n\tMon, 2 Oct 2017 19:03:04 -0400","from mail-wr0-f171.google.com ([209.85.128.171]:54859 \"EHLO\n\tmail-wr0-f171.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751075AbdJBXDB (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778826,"web_url":"http://patchwork.ozlabs.org/comment/1778826/","msgid":"<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>","list_archive_url":null,"date":"2017-10-03T10:32:25","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 03/10/17 00:02, Dmitry Osipenko wrote:\n> On 02.10.2017 20:05, Stephen Warren wrote:\n>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>>\n>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>>\n>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>>\n>>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>>> ---\n>>>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>>> ++++++++++++++++++++++\n>>>>>>>>    1 file changed, 23 insertions(+)\n>>>>>>>>    create mode 100644\n>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>\n>>>>>>>> diff --git\n>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>> new file mode 100644\n>>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>>> --- /dev/null\n>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>>> +\n>>>>>>>> +Required properties:\n>>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>>> value\n>>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>>> +        REQ_SEL field.\n>>>>>>>\n>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>>\n>>>>>>\n>>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>>> up to\n>>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>>\n>>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>>\n>>>>>> And I think the same applies to requester... any objections?\n>>>>>\n>>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>>\n>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>>> this.\n>>>>\n>>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>>>> when SW desires, rather than being a combination of after SW programs the\n>>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>>> present. We could add an extra #dma-cells value later if we find a use for it,\n>>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>>> rather than some other separate higher-level property/driver/...\n>>>\n>>> Thank you for the comment. If we'd want to extend the binding further with the\n>>> trigger, how to differentiate trigger from the requester in a case of a single\n>>> #data-cell?\n>>>\n>>> Of course realistically a chance that the further extension would be needed is\n>>> very-very low, so we may defer the efforts to solve that question and for now\n>>> make driver aware of the potential #dma-cells extension.\n>>\n>> The request selector cell isn't optional, so is always present. If we later add\n>> an optional trig_sel cell, we'll either have:\n>>\n>> #dma-cells=<1>: req_sel\n>>\n>> or:\n>>\n>> #dma-cells=<2>: req_sel, trig_sel\n> \n> Why request sel. couldn't be optional? Could you please elaborate a bit more?\n> \n> I think possible options are:\n> \n> #dma-cells=<1>: req_sel\n> #dma-cells=<1>: trig_sel\n\nWith the above, how would you know that it is the req_sel or trig_sel\nthat is specified?\n\n> #dma-cells=<2>: req_sel, trig_sel\n> \n> The only difference between request and trigger is that trigger issues the whole\n> transfer, while request only a single burst. Isn't it possible to have a case in\n> HW for the \"trigger-only\" option? If not or it's a rareness, then I agree that\n> REQ_SEL must be mandatory.\n\nI think that what Stephen is proposing is that for now we go with\n'#dma-cells=<1>' and if we ever need to support the trigger cell we\ncould add support for '#dma-cells=<2>'. So with this proposal the\n'req_sel' would always be required for both '#dma-cells=<1>' and\n'#dma-cells=<2>'. Even if the req_sel is not actually used but the\n'trig_sel' is, the user would have to set 'req_sel' to some pre-defined\nvalue (eg. -1) where we know to ignore it.\n\nCheers\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5wQB48Mzz9s81\n\tfor ;\n\tTue, 3 Oct 2017 21:34:42 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751001AbdJCKeY convert rfc822-to-8bit (ORCPT\n\t);\n\tTue, 3 Oct 2017 06:34:24 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:3925 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750767AbdJCKeX (ORCPT\n\t); Tue, 3 Oct 2017 06:34:23 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid ; Tue, 03 Oct 2017 03:33:47 -0700","from HQMAIL101.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 03 Oct 2017 03:33:52 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 3 Oct 2017 10:32:35 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 3 Oct 2017 10:32:30 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 03 Oct 2017 03:33:52 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko ,\n\tStephen Warren , \n\tThierry Reding ,\n\t\"Laxman Dewangan\" ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\t\"Michael Turquette\" ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>\n\t<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>\n\t<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>\n\t<795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com>","From":"Jon Hunter ","Message-ID":"<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>","Date":"Tue, 3 Oct 2017 11:32:25 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com>","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL101.nvidia.com (10.26.138.13) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778870,"web_url":"http://patchwork.ozlabs.org/comment/1778870/","msgid":"","list_archive_url":null,"date":"2017-10-03T12:07:17","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 03.10.2017 13:32, Jon Hunter wrote:\n> \n> \n> On 03/10/17 00:02, Dmitry Osipenko wrote:\n>> On 02.10.2017 20:05, Stephen Warren wrote:\n>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>>>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>>>\n>>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>>>\n>>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>>>\n>>>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>>>> ---\n>>>>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>>>> ++++++++++++++++++++++\n>>>>>>>>>    1 file changed, 23 insertions(+)\n>>>>>>>>>    create mode 100644\n>>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>\n>>>>>>>>> diff --git\n>>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> new file mode 100644\n>>>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>>>> --- /dev/null\n>>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>>>> +\n>>>>>>>>> +Required properties:\n>>>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>>>> value\n>>>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>>>> +        REQ_SEL field.\n>>>>>>>>\n>>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>>>\n>>>>>>>\n>>>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>>>> up to\n>>>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>>>\n>>>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>>>\n>>>>>>> And I think the same applies to requester... any objections?\n>>>>>>\n>>>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>>>\n>>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>>>> this.\n>>>>>\n>>>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>>>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>>>>> when SW desires, rather than being a combination of after SW programs the\n>>>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>>>> present. We could add an extra #dma-cells value later if we find a use for it,\n>>>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>>>> rather than some other separate higher-level property/driver/...\n>>>>\n>>>> Thank you for the comment. If we'd want to extend the binding further with the\n>>>> trigger, how to differentiate trigger from the requester in a case of a single\n>>>> #data-cell?\n>>>>\n>>>> Of course realistically a chance that the further extension would be needed is\n>>>> very-very low, so we may defer the efforts to solve that question and for now\n>>>> make driver aware of the potential #dma-cells extension.\n>>>\n>>> The request selector cell isn't optional, so is always present. If we later add\n>>> an optional trig_sel cell, we'll either have:\n>>>\n>>> #dma-cells=<1>: req_sel\n>>>\n>>> or:\n>>>\n>>> #dma-cells=<2>: req_sel, trig_sel\n>>\n>> Why request sel. couldn't be optional? Could you please elaborate a bit more?\n>>\n>> I think possible options are:\n>>\n>> #dma-cells=<1>: req_sel\n>> #dma-cells=<1>: trig_sel\n> \n> With the above, how would you know that it is the req_sel or trig_sel\n> that is specified?\n> \n>> #dma-cells=<2>: req_sel, trig_sel\n>>\n>> The only difference between request and trigger is that trigger issues the whole\n>> transfer, while request only a single burst. Isn't it possible to have a case in\n>> HW for the \"trigger-only\" option? If not or it's a rareness, then I agree that\n>> REQ_SEL must be mandatory.\n> \n> I think that what Stephen is proposing is that for now we go with\n> '#dma-cells=<1>' and if we ever need to support the trigger cell we\n> could add support for '#dma-cells=<2>'. So with this proposal the\n> 'req_sel' would always be required for both '#dma-cells=<1>' and\n> '#dma-cells=<2>'. Even if the req_sel is not actually used but the\n> 'trig_sel' is, the user would have to set 'req_sel' to some pre-defined\n> value (eg. -1) where we know to ignore it.\n> \n\nOkay, I see now. Thank you for the clarification, but then we should have that\npre-defined value declared in the binding?\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"NQFQwEZ2\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5yTF0Crkz9t2h\n\tfor ;\n\tTue, 3 Oct 2017 23:07:29 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751116AbdJCMH0 (ORCPT\n\t);\n\tTue, 3 Oct 2017 08:07:26 -0400","from mail-lf0-f66.google.com ([209.85.215.66]:50361 \"EHLO\n\tmail-lf0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750865AbdJCMHX (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778891,"web_url":"http://patchwork.ozlabs.org/comment/1778891/","msgid":"","list_archive_url":null,"date":"2017-10-03T12:19:31","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 03/10/17 13:07, Dmitry Osipenko wrote:\n> On 03.10.2017 13:32, Jon Hunter wrote:\n>>\n>>\n>> On 03/10/17 00:02, Dmitry Osipenko wrote:\n>>> On 02.10.2017 20:05, Stephen Warren wrote:\n>>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>>>>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>>>>\n>>>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>>>>\n>>>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>>>>\n>>>>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>>>>> ---\n>>>>>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>>>>> ++++++++++++++++++++++\n>>>>>>>>>>    1 file changed, 23 insertions(+)\n>>>>>>>>>>    create mode 100644\n>>>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>>\n>>>>>>>>>> diff --git\n>>>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> new file mode 100644\n>>>>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>>>>> --- /dev/null\n>>>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>>>>> +\n>>>>>>>>>> +Required properties:\n>>>>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>>>>> value\n>>>>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>>>>> +        REQ_SEL field.\n>>>>>>>>>\n>>>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>>>>\n>>>>>>>>\n>>>>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>>>>> up to\n>>>>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>>>>\n>>>>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>>>>\n>>>>>>>> And I think the same applies to requester... any objections?\n>>>>>>>\n>>>>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>>>>\n>>>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>>>>> this.\n>>>>>>\n>>>>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>>>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>>>>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>>>>>> when SW desires, rather than being a combination of after SW programs the\n>>>>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>>>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>>>>> present. We could add an extra #dma-cells value later if we find a use for it,\n>>>>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>>>>> rather than some other separate higher-level property/driver/...\n>>>>>\n>>>>> Thank you for the comment. If we'd want to extend the binding further with the\n>>>>> trigger, how to differentiate trigger from the requester in a case of a single\n>>>>> #data-cell?\n>>>>>\n>>>>> Of course realistically a chance that the further extension would be needed is\n>>>>> very-very low, so we may defer the efforts to solve that question and for now\n>>>>> make driver aware of the potential #dma-cells extension.\n>>>>\n>>>> The request selector cell isn't optional, so is always present. If we later add\n>>>> an optional trig_sel cell, we'll either have:\n>>>>\n>>>> #dma-cells=<1>: req_sel\n>>>>\n>>>> or:\n>>>>\n>>>> #dma-cells=<2>: req_sel, trig_sel\n>>>\n>>> Why request sel. couldn't be optional? Could you please elaborate a bit more?\n>>>\n>>> I think possible options are:\n>>>\n>>> #dma-cells=<1>: req_sel\n>>> #dma-cells=<1>: trig_sel\n>>\n>> With the above, how would you know that it is the req_sel or trig_sel\n>> that is specified?\n>>\n>>> #dma-cells=<2>: req_sel, trig_sel\n>>>\n>>> The only difference between request and trigger is that trigger issues the whole\n>>> transfer, while request only a single burst. Isn't it possible to have a case in\n>>> HW for the \"trigger-only\" option? If not or it's a rareness, then I agree that\n>>> REQ_SEL must be mandatory.\n>>\n>> I think that what Stephen is proposing is that for now we go with\n>> '#dma-cells=<1>' and if we ever need to support the trigger cell we\n>> could add support for '#dma-cells=<2>'. So with this proposal the\n>> 'req_sel' would always be required for both '#dma-cells=<1>' and\n>> '#dma-cells=<2>'. Even if the req_sel is not actually used but the\n>> 'trig_sel' is, the user would have to set 'req_sel' to some pre-defined\n>> value (eg. -1) where we know to ignore it.\n>>\n> \n> Okay, I see now. Thank you for the clarification, but then we should have that\n> pre-defined value declared in the binding?\n\nI would have thought it should be in the dt-binding header.\n\nCheers\nJon","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5ynV26FFz9t2Z\n\tfor ;\n\tTue, 3 Oct 2017 23:21:34 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752256AbdJCMUG convert rfc822-to-8bit (ORCPT\n\t);\n\tTue, 3 Oct 2017 08:20:06 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:2544 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752248AbdJCMUC (ORCPT\n\t); Tue, 3 Oct 2017 08:20:02 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid ; Tue, 03 Oct 2017 05:19:31 -0700","from HQMAIL108.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 03 Oct 2017 05:19:36 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com\n\t(172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 3 Oct 2017 12:19:36 +0000","from [10.21.132.144] (10.21.132.144) by UKMAIL101.nvidia.com\n\t(10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 3 Oct 2017 12:19:32 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 03 Oct 2017 05:19:36 -0700","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Dmitry Osipenko ,\n\tStephen Warren , \n\tThierry Reding ,\n\t\"Laxman Dewangan\" ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\t\"Michael Turquette\" ,\n\tStephen Boyd , \"Rob Herring\" , \n\tVinod Koul ","CC":", ,\n\t, ,\n\t","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>\n\t<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>\n\t<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>\n\t<795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com>\n\t<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>\n\t","From":"Jon Hunter ","Message-ID":"","Date":"Tue, 3 Oct 2017 13:19:31 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","X-Originating-IP":"[10.21.132.144]","X-ClientProxiedBy":"UKMAIL101.nvidia.com (10.26.138.13) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1779091,"web_url":"http://patchwork.ozlabs.org/comment/1779091/","msgid":"","list_archive_url":null,"date":"2017-10-03T15:38:07","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":12517,"url":"http://patchwork.ozlabs.org/api/people/12517/","name":"Stephen Warren","email":"swarren@wwwdotorg.org"},"content":"On 10/03/2017 04:32 AM, Jon Hunter wrote:\n> \n> \n> On 03/10/17 00:02, Dmitry Osipenko wrote:\n>> On 02.10.2017 20:05, Stephen Warren wrote:\n>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>>>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>>>\n>>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>>>\n>>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>>>\n>>>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>>>> ---\n>>>>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>>>> ++++++++++++++++++++++\n>>>>>>>>>    1 file changed, 23 insertions(+)\n>>>>>>>>>    create mode 100644\n>>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>\n>>>>>>>>> diff --git\n>>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> new file mode 100644\n>>>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>>>> --- /dev/null\n>>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>>>> +\n>>>>>>>>> +Required properties:\n>>>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>>>> value\n>>>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>>>> +        REQ_SEL field.\n>>>>>>>>\n>>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>>>\n>>>>>>>\n>>>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>>>> up to\n>>>>>>> software to decide what trigger to select. So it shouldn't be in the binding.\n>>>>>>\n>>>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>>>\n>>>>>>> And I think the same applies to requester... any objections?\n>>>>>>\n>>>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>>>\n>>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>>>> this.\n>>>>>\n>>>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>>>> semantics of the current DMA binding only cover DMA transfers that are initiated\n>>>>> when SW desires, rather than being a combination of after SW programs the\n>>>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>>>> present. We could add an extra #dma-cells value later if we find a use for it,\n>>>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>>>> rather than some other separate higher-level property/driver/...\n>>>>\n>>>> Thank you for the comment. If we'd want to extend the binding further with the\n>>>> trigger, how to differentiate trigger from the requester in a case of a single\n>>>> #data-cell?\n>>>>\n>>>> Of course realistically a chance that the further extension would be needed is\n>>>> very-very low, so we may defer the efforts to solve that question and for now\n>>>> make driver aware of the potential #dma-cells extension.\n>>>\n>>> The request selector cell isn't optional, so is always present. If we later add\n>>> an optional trig_sel cell, we'll either have:\n>>>\n>>> #dma-cells=<1>: req_sel\n>>>\n>>> or:\n>>>\n>>> #dma-cells=<2>: req_sel, trig_sel\n>>\n>> Why request sel. couldn't be optional? Could you please elaborate a bit more?\n\nThe documentation currently says it's mandatory, and DT bindings must be \nevolved in a backwards-compatible fashion.\n\n>> I think possible options are:\n>>\n>> #dma-cells=<1>: req_sel\n>> #dma-cells=<1>: trig_sel\n> \n> With the above, how would you know that it is the req_sel or trig_sel\n> that is specified?\n\nAlso, if req_sel were optional, then it'd be impossible to distinguish \nbetween those cases, so we can't design a binding like that. In general, \nwhen adding extra optional cells to an #xxx-cells style binding, then \nwhenever cell N is present, all cells before cell N must be present even \nif optional.\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y638g61p6z9sNw\n\tfor ;\n\tWed, 4 Oct 2017 02:38:27 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752477AbdJCPiM (ORCPT\n\t);\n\tTue, 3 Oct 2017 11:38:12 -0400","from avon.wwwdotorg.org ([104.237.132.123]:53322 \"EHLO\n\tavon.wwwdotorg.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751962AbdJCPiL (ORCPT\n\t); Tue, 3 Oct 2017 11:38:11 -0400","from [10.20.204.51] (thunderhill.nvidia.com [216.228.112.22])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby avon.wwwdotorg.org (Postfix) with ESMTPSA id 4F5851C03B8;\n\tTue, 3 Oct 2017 09:38:09 -0600 (MDT)"],"X-Virus-Status":"Clean","X-Virus-Scanned":"clamav-milter 0.99.2 at avon.wwwdotorg.org","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Jon Hunter , Dmitry Osipenko ,\n\tThierry Reding ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","Cc":"linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,\n\tdmaengine@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t\n\t<96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com>\n\t<0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>\n\t<9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org>\n\t<5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com>\n\t<788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org>\n\t<795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com>\n\t<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>","From":"Stephen Warren ","Message-ID":"","Date":"Tue, 3 Oct 2017 09:38:07 -0600","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-GB","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1779145,"web_url":"http://patchwork.ozlabs.org/comment/1779145/","msgid":"<93be2eb5-617a-f681-0a55-c2bbef46d08b@gmail.com>","list_archive_url":null,"date":"2017-10-03T17:04:09","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 03.10.2017 18:38, Stephen Warren wrote:\n> On 10/03/2017 04:32 AM, Jon Hunter wrote:\n>>\n>>\n>> On 03/10/17 00:02, Dmitry Osipenko wrote:\n>>> On 02.10.2017 20:05, Stephen Warren wrote:\n>>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:\n>>>>> On 29.09.2017 22:30, Stephen Warren wrote:\n>>>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:\n>>>>>>>\n>>>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:\n>>>>>>>> On 26.09.2017 17:50, Jon Hunter wrote:\n>>>>>>>>>\n>>>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:\n>>>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>>>>>>>>>> on Tegra20/30 SoC's.\n>>>>>>>>>>\n>>>>>>>>>> Signed-off-by: Dmitry Osipenko \n>>>>>>>>>> ---\n>>>>>>>>>>     .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23\n>>>>>>>>>> ++++++++++++++++++++++\n>>>>>>>>>>     1 file changed, 23 insertions(+)\n>>>>>>>>>>     create mode 100644\n>>>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>>\n>>>>>>>>>> diff --git\n>>>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> new file mode 100644\n>>>>>>>>>> index 000000000000..2af9aa76ae11\n>>>>>>>>>> --- /dev/null\n>>>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>>>>>>>>> @@ -0,0 +1,23 @@\n>>>>>>>>>> +* NVIDIA Tegra AHB DMA controller\n>>>>>>>>>> +\n>>>>>>>>>> +Required properties:\n>>>>>>>>>> +- compatible:    Must be \"nvidia,tegra20-ahbdma\"\n>>>>>>>>>> +- reg:        Should contain registers base address and length.\n>>>>>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.\n>>>>>>>>>> +- clocks:    Should contain one entry, DMA controller clock.\n>>>>>>>>>> +- resets :    Should contain one entry, DMA controller reset.\n>>>>>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select\n>>>>>>>>>> value\n>>>>>>>>>> +        for the peripheral. For more details consult the Tegra TRM's\n>>>>>>>>>> +        documentation, in particular AHB DMA channel control register\n>>>>>>>>>> +        REQ_SEL field.\n>>>>>>>>>\n>>>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?\n>>>>>>>>>\n>>>>>>>>\n>>>>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's\n>>>>>>>> up to\n>>>>>>>> software to decide what trigger to select. So it shouldn't be in the\n>>>>>>>> binding.\n>>>>>>>\n>>>>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.\n>>>>>>>\n>>>>>>>> And I think the same applies to requester... any objections?\n>>>>>>>\n>>>>>>> Well, the REQ_SEL should definitely be in the binding.\n>>>>>>>\n>>>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks\n>>>>>>> like we never bothered with it for the APB DMA and so maybe no ones uses\n>>>>>>> this.\n>>>>>>\n>>>>>> I don't think TRIG_SEL should be in the binding, at least at present. While\n>>>>>> TRIG_SEL certainly is something used to configure the transfer, I believe the\n>>>>>> semantics of the current DMA binding only cover DMA transfers that are\n>>>>>> initiated\n>>>>>> when SW desires, rather than being a combination of after SW programs the\n>>>>>> transfer plus some other HW event. So, we always use a default/hard-coded\n>>>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's\n>>>>>> certainly no known use-case that requires a non-default TRIG_SEL value at\n>>>>>> present. We could add an extra #dma-cells value later if we find a use for\n>>>>>> it,\n>>>>>> and the semantics of that use-case make sense to add it to the DMA specifier,\n>>>>>> rather than some other separate higher-level property/driver/...\n>>>>>\n>>>>> Thank you for the comment. If we'd want to extend the binding further with the\n>>>>> trigger, how to differentiate trigger from the requester in a case of a single\n>>>>> #data-cell?\n>>>>>\n>>>>> Of course realistically a chance that the further extension would be needed is\n>>>>> very-very low, so we may defer the efforts to solve that question and for now\n>>>>> make driver aware of the potential #dma-cells extension.\n>>>>\n>>>> The request selector cell isn't optional, so is always present. If we later add\n>>>> an optional trig_sel cell, we'll either have:\n>>>>\n>>>> #dma-cells=<1>: req_sel\n>>>>\n>>>> or:\n>>>>\n>>>> #dma-cells=<2>: req_sel, trig_sel\n>>>\n>>> Why request sel. couldn't be optional? Could you please elaborate a bit more?\n> \n> The documentation currently says it's mandatory, and DT bindings must be evolved\n> in a backwards-compatible fashion.\n> \n>>> I think possible options are:\n>>>\n>>> #dma-cells=<1>: req_sel\n>>> #dma-cells=<1>: trig_sel\n>>\n>> With the above, how would you know that it is the req_sel or trig_sel\n>> that is specified?\n> \n> Also, if req_sel were optional, then it'd be impossible to distinguish between\n> those cases, so we can't design a binding like that. In general, when adding\n> extra optional cells to an #xxx-cells style binding, then whenever cell N is\n> present, all cells before cell N must be present even if optional.\n\nI've checked how extending of #dma-cells looks like and it is indeed a good\nvariant since it preserves backward compatibility. Thank you and Jon for the\ncomments and suggestions, I'll send out v2 soon.\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"o+3VOO3L\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y653l3DZsz9t6n\n\tfor ;\n\tWed, 4 Oct 2017 04:04:19 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751120AbdJCRER (ORCPT\n\t);\n\tTue, 3 Oct 2017 13:04:17 -0400","from mail-wm0-f47.google.com ([74.125.82.47]:49110 \"EHLO\n\tmail-wm0-f47.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751090AbdJCREP (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1780976,"web_url":"http://patchwork.ozlabs.org/comment/1780976/","msgid":"<20171005203355.5lftjytx5f6rhe2d@rob-hp-laptop>","list_archive_url":null,"date":"2017-10-05T20:33:55","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Tue, Sep 26, 2017 at 02:22:04AM +0300, Dmitry Osipenko wrote:\n> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n> on Tegra20/30 SoC's.\n> \n> Signed-off-by: Dmitry Osipenko \n> ---\n> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n> 1 file changed, 23 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> \n> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> new file mode 100644\n> index 000000000000..2af9aa76ae11\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n> @@ -0,0 +1,23 @@\n> +* NVIDIA Tegra AHB DMA controller\n> +\n> +Required properties:\n> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n> +- reg:\t\tShould contain registers base address and length.\n> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n> +- clocks:\tShould contain one entry, DMA controller clock.\n> +- resets :\tShould contain one entry, DMA controller reset.\n> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n> +\t\tdocumentation, in particular AHB DMA channel control register\n> +\t\tREQ_SEL field.\n> +\n> +Example:\n> +\n> +ahbdma: ahbdma@60008000 {\n\nUse standard node names. dma-controller in this case.\n\n> +\tcompatible = \"nvidia,tegra20-ahbdma\";\n> +\treg = <0x60008000 0x2000>;\n> +\tinterrupts = ;\n> +\tclocks = <&tegra_car TEGRA20_CLK_AHBDMA>;\n> +\tresets = <&tegra_car 33>;\n> +\t#dma-cells = <1>;\n> +};\n> -- \n> 2.14.1\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; 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\n\tThu, 05 Oct 2017 13:33:57 -0700 (PDT)","Date":"Thu, 5 Oct 2017 15:33:55 -0500","From":"Rob Herring ","To":"Dmitry Osipenko ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tVinod Koul , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","Message-ID":"<20171005203355.5lftjytx5f6rhe2d@rob-hp-laptop>","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1781040,"web_url":"http://patchwork.ozlabs.org/comment/1781040/","msgid":"<4cb9745d-4bc1-57f0-f4ee-c12089d0c190@gmail.com>","list_archive_url":null,"date":"2017-10-05T21:30:59","subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 05.10.2017 23:33, Rob Herring wrote:\n> On Tue, Sep 26, 2017 at 02:22:04AM +0300, Dmitry Osipenko wrote:\n>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents\n>> on Tegra20/30 SoC's.\n>>\n>> Signed-off-by: Dmitry Osipenko \n>> ---\n>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++\n>> 1 file changed, 23 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>>\n>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> new file mode 100644\n>> index 000000000000..2af9aa76ae11\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n>> @@ -0,0 +1,23 @@\n>> +* NVIDIA Tegra AHB DMA controller\n>> +\n>> +Required properties:\n>> +- compatible:\tMust be \"nvidia,tegra20-ahbdma\"\n>> +- reg:\t\tShould contain registers base address and length.\n>> +- interrupts:\tShould contain one entry, DMA controller interrupt.\n>> +- clocks:\tShould contain one entry, DMA controller clock.\n>> +- resets :\tShould contain one entry, DMA controller reset.\n>> +- #dma-cells:\tShould be <1>. The cell represents DMA request select value\n>> +\t\tfor the peripheral. For more details consult the Tegra TRM's\n>> +\t\tdocumentation, in particular AHB DMA channel control register\n>> +\t\tREQ_SEL field.\n>> +\n>> +Example:\n>> +\n>> +ahbdma: ahbdma@60008000 {\n> \n> Use standard node names. dma-controller in this case.\n> \n\nOkay, I'll change it in v3. Thank you for the comment.\n\n>> +\tcompatible = \"nvidia,tegra20-ahbdma\";\n>> +\treg = <0x60008000 0x2000>;\n>> +\tinterrupts = ;\n>> +\tclocks = <&tegra_car TEGRA20_CLK_AHBDMA>;\n>> +\tresets = <&tegra_car 33>;\n>> +\t#dma-cells = <1>;\n>> +};\n>> -- \n>> 2.14.1\n>>\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"bMEWfCYD\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7Qtz0BKpz9t2Z\n\tfor ;\n\tFri, 6 Oct 2017 08:31:23 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751831AbdJEVbI (ORCPT\n\t);\n\tThu, 5 Oct 2017 17:31:08 -0400","from mail-wm0-f65.google.com ([74.125.82.65]:33401 \"EHLO\n\tmail-wm0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751776AbdJEVbF (ORCPT\n\t); Thu, 5 Oct 2017 17:31:05 -0400","by mail-wm0-f65.google.com with SMTP id u138so9826441wmu.0;\n\tThu, 05 Oct 2017 14:31:04 -0700 (PDT)","from [192.168.1.145] (ppp109-252-55-163.pppoe.spdop.ru.\n\t[109.252.55.163]) by smtp.googlemail.com with ESMTPSA id\n\tn7sm178708edl.12.2017.10.05.14.31.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 05 Oct 2017 14:31:02 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=sTVAAPXqlUwKHSBv6/RH4rZ7umiJVkbl5cgsa9GaXlg=;\n\tb=bMEWfCYDwKvvHjGa8ueVrXK6Cvdm/eQ2YoCRHEjulfvF5Ya0rwdK2K0bDy7mTd1T1o\n\tr0FScfKf5siGVmfqnuFRSHYkDu4V9vhJD1Q2jpzk2p7WUIgk6Lf4QiunG5fSEG4RBHl3\n\tyA0X51bdq3De7sQtxJLoIyngwy/RvrYhYf/eqBMZYFNIFx86oSxd4Ib5yJrugvTmGfU+\n\tSKIiWCotvxJvZyfSzlk0CkpJr2BYVx7WkjvYcEEcnPUVhZy8vMwdCBKvD0kqRbrjxrjS\n\tRnUQf3rPXhNAv81Zs5CdKXIV5ngnGfxIogtafbYLwNZslQ3VYYepKQzR9YgFTBZoq5M6\n\tQMOw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=sTVAAPXqlUwKHSBv6/RH4rZ7umiJVkbl5cgsa9GaXlg=;\n\tb=DbSOs5133BlpZrgxxUMKpC7/6d892FiS3lMcHbhfg2Da7WFlA731WKmgt9nHBgjXrL\n\tM29XaYJu07UeJGIsdCQR0Fxbkiqed+q6Pm1LMNeWaz9ukyNYS5oganhvpZ0nkKFHrv27\n\tMN1mllszVN3ghF67D+x+Z8OoilBU7NytQ4dzf5xcGbsopNYEjWNJewq3MoqNWFDO3Dd5\n\t8h9wg0xHrKvVxJDSArVxpcLgNeImPhRUzFUrR/5sGvWhbGAC711RMSKE/WmwOSEsJZQ8\n\tyckEvFoa0DhQwy2SR0+ZVShfwmH6YWcDeo2ZlCl/nripOsPTcLYagi+adgscvNa1xdZT\n\tPu3A==","X-Gm-Message-State":"AMCzsaVpb8sdl57p+NpEhgqjilSyYuUGCCaD3Xa/AvW03TyWnW9xLFMi\n\t3Biw646xGbtF5tproxKQFyBpw2EE","X-Google-Smtp-Source":"AOwi7QBXpVy3MFvHx3rTbXtdMrEUI4sw7ZioIyigP4XARadnT3eoTRKZiI4TbScfItmGq+e/0fFkjw==","X-Received":"by 10.80.173.185 with SMTP id a54mr519814edd.70.1507239063572;\n\tThu, 05 Oct 2017 14:31:03 -0700 (PDT)","Subject":"Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB\n\tDMA controller","To":"Rob Herring ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tVinod Koul , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","References":"\n\t<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>\n\t<20171005203355.5lftjytx5f6rhe2d@rob-hp-laptop>","From":"Dmitry Osipenko ","Message-ID":"<4cb9745d-4bc1-57f0-f4ee-c12089d0c190@gmail.com>","Date":"Fri, 6 Oct 2017 00:30:59 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171005203355.5lftjytx5f6rhe2d@rob-hp-laptop>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]