[{"id":1774607,"web_url":"http://patchwork.ozlabs.org/comment/1774607/","msgid":"<995ab037-992e-5782-4faf-8965d039c841@denx.de>","list_archive_url":null,"date":"2017-09-25T09:14:01","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> These drivers handle FPGA program operation from flash loading\n> RBF to memory and then to program FPGA.\n> \n> Signed-off-by: Tien Fong Chee \n\nDid you run checkpatch on this before submitting ? I presume no ...\n\n> ---\n> .../include/mach/fpga_manager_arria10.h | 27 ++\n> drivers/fpga/socfpga_arria10.c | 391 ++++++++++++++++++++-\n> include/altera.h | 6 +\n> include/configs/socfpga_common.h | 4 +\n> 4 files changed, 425 insertions(+), 3 deletions(-)\n[...]\n\n> @@ -112,13 +122,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)\n> \tunsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\n> \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;\n> \n> -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,\n> -\t * timeout at 1000ms\n> +\t/*\n> +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until\n> +\t * de-asserted, timeout at 1000ms\n> \t */\n> \treturn wait_for_bit(__func__,\n> \t\t\t &fpga_manager_base->imgcfg_stat,\n> \t\t\t mask,\n> -\t\t\t false, FPGA_TIMEOUT_MSEC, false);\n> +\t\t\t true, FPGA_TIMEOUT_MSEC, false);\n> }\n\nSeems more like a fix, split this out.\n\n> static int wait_for_f2s_nstatus_pin(unsigned long value)\n> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)\n> \n> \t/* Initialize the FPGA Manager */\n> \tstatus = fpgamgr_program_init((u32 *)rbf_data, rbf_size);\n> +\n> \tif (status)\n> \t\treturn status;\n> \n> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)\n> \n> \treturn fpgamgr_program_finish();\n> }\n> +\n> +#if defined(CONFIG_CMD_FPGA_LOADFS)\n> +const char *get_cff_filename(const void *fdt, int *len, u32 core)\n> +{\n> +\tconst char *cff_filename = NULL;\n> +\tconst char *cell;\n> +\tint nodeoffset;\n> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n> +\n> +\tif (nodeoffset >= 0) {\n> +\t\tif (core)\n> +\t\t\tcell = fdt_getprop(fdt,\n> +\t\t\t\t\tnodeoffset,\n> +\t\t\t\t\t\"bitstream_core\",\n> +\t\t\t\t\tlen);\n> +\t\telse\n> +\t\t\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_periph\",\n> +\t\t\t\t\t len);\n> +\n> +\t\tif (cell)\n> +\t\t\tcff_filename = cell;\n> +\t}\n> +\n> +\treturn cff_filename;\n> +}\n> +\n> +const char *get_cff_devpart(const void *fdt, int *len)\n> +{\n> +\tconst char *cff_devpart = NULL;\n> +\tconst char *cell;\n> +\tint nodeoffset;\n> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n> +\n> +\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\", len);\n> +\n> +\tif (cell)\n> +\t\tcff_devpart = cell;\n> +\n> +\treturn cff_devpart;\n> +}\n\nTake a look at splash*.c , I believe that can be reworked into generic\nfirmware loader , which you could then use here.\n\n[...]\n\n> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\n> index 9897e11..eadce2d 100644\n> --- a/include/configs/socfpga_common.h\n> +++ b/include/configs/socfpga_common.h\n> @@ -27,7 +27,11 @@\n> */\n> #define CONFIG_NR_DRAM_BANKS\t\t1\n> #define PHYS_SDRAM_1\t\t\t0x0\n> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 * 1024)\n> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 * 1024)\n> +#endif\n\nYou definitely don't need 128 MiB of malloc area.\n\n> #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\n> #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE\n> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:30 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:30 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"GEyJncVsl2oVY9JCVh/vTjAEvL80T8RnFk3ZwHfNfXk=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<995ab037-992e-5782-4faf-8965d039c841@denx.de>","Date":"Mon, 25 Sep 2017 11:14:01 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775259,"web_url":"http://patchwork.ozlabs.org/comment/1775259/","msgid":"<1506414635.27760.26.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T08:30:35","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > These drivers handle FPGA program operation from flash loading\r\n> > RBF to memory and then to program FPGA.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> Did you run checkpatch on this before submitting ? I presume no ...\r\n> \r\nYeah, i run checkpatch for all patches. What's the issue here?\r\n> > \r\n> > ---\r\n> >  .../include/mach/fpga_manager_arria10.h            |  27 ++\r\n> >  drivers/fpga/socfpga_arria10.c                     | 391\r\n> > ++++++++++++++++++++-\r\n> >  include/altera.h                                   |   6 +\r\n> >  include/configs/socfpga_common.h                   |   4 +\r\n> >  4 files changed, 425 insertions(+), 3 deletions(-)\r\n> [...]\r\n> \r\n> > \r\n> > @@ -112,13 +122,14 @@ static int\r\n> > wait_for_nconfig_pin_and_nstatus_pin(void)\r\n> >  \tunsigned long mask =\r\n> > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\r\n> >  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU\r\n> > S_PIN_SET_MSK;\r\n> >  \r\n> > -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\r\n> > until de-asserted,\r\n> > -\t * timeout at 1000ms\r\n> > +\t/*\r\n> > +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\r\n> > until\r\n> > +\t * de-asserted, timeout at 1000ms\r\n> >  \t */\r\n> >  \treturn wait_for_bit(__func__,\r\n> >  \t\t\t    &fpga_manager_base->imgcfg_stat,\r\n> >  \t\t\t    mask,\r\n> > -\t\t\t    false, FPGA_TIMEOUT_MSEC, false);\r\n> > +\t\t\t    true, FPGA_TIMEOUT_MSEC, false);\r\n> >  }\r\n> Seems more like a fix, split this out.\r\n> \r\nOkay.\r\n> > \r\n> >  static int wait_for_f2s_nstatus_pin(unsigned long value)\r\n> > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void\r\n> > *rbf_data, size_t rbf_size)\r\n> >  \r\n> >  \t/* Initialize the FPGA Manager */\r\n> >  \tstatus = fpgamgr_program_init((u32 *)rbf_data, rbf_size);\r\n> > +\r\n> >  \tif (status)\r\n> >  \t\treturn status;\r\n> >  \r\n> > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const\r\n> > void *rbf_data, size_t rbf_size)\r\n> >  \r\n> >  \treturn fpgamgr_program_finish();\r\n> >  }\r\n> > +\r\n> > +#if defined(CONFIG_CMD_FPGA_LOADFS)\r\n> > +const char *get_cff_filename(const void *fdt, int *len, u32 core)\r\n> > +{\r\n> > +\tconst char *cff_filename = NULL;\r\n> > +\tconst char *cell;\r\n> > +\tint nodeoffset;\r\n> > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > +\r\n> > +\tif (nodeoffset >= 0) {\r\n> > +\t\tif (core)\r\n> > +\t\t\tcell = fdt_getprop(fdt,\r\n> > +\t\t\t\t\tnodeoffset,\r\n> > +\t\t\t\t\t\"bitstream_core\",\r\n> > +\t\t\t\t\tlen);\r\n> > +\t\telse\r\n> > +\t\t\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > \"bitstream_periph\",\r\n> > +\t\t\t\t\t len);\r\n> > +\r\n> > +\t\tif (cell)\r\n> > +\t\t\tcff_filename = cell;\r\n> > +\t}\r\n> > +\r\n> > +\treturn cff_filename;\r\n> > +}\r\n> > +\r\n> > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > +{\r\n> > +\tconst char *cff_devpart = NULL;\r\n> > +\tconst char *cell;\r\n> > +\tint nodeoffset;\r\n> > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > +\r\n> > +\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\",\r\n> > len);\r\n> > +\r\n> > +\tif (cell)\r\n> > +\t\tcff_devpart = cell;\r\n> > +\r\n> > +\treturn cff_devpart;\r\n> > +}\r\n> Take a look at splash*.c , I believe that can be reworked into\r\n> generic\r\n> firmware loader , which you could then use here.\r\n> \r\n> [...]\r\n> \r\n> > \r\n> > diff --git a/include/configs/socfpga_common.h\r\n> > b/include/configs/socfpga_common.h\r\n> > index 9897e11..eadce2d 100644\r\n> > --- a/include/configs/socfpga_common.h\r\n> > +++ b/include/configs/socfpga_common.h\r\n> > @@ -27,7 +27,11 @@\r\n> >   */\r\n> >  #define CONFIG_NR_DRAM_BANKS\t\t1\r\n> >  #define PHYS_SDRAM_1\t\t\t0x0\r\n> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 * 1024)\r\n> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 * 1024)\r\n> > +#endif\r\n> You definitely don't need 128 MiB of malloc area.\r\n> \r\nOkay, i will try out with smaller size.\r\n> > \r\n> >  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\r\n> >  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE\r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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26 Sep 2017 01:30:37 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX106.gar.corp.intel.com ([169.254.9.199]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 16:30:36 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,440,1500966000\"; d=\"scan'208\";a=\"903906148\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGGMoA=","Date":"Tue, 26 Sep 2017 08:30:35 +0000","Message-ID":"<1506414635.27760.26.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>","In-Reply-To":"<995ab037-992e-5782-4faf-8965d039c841@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<85D5872A15BE8D4EAA99632C0833EA9A@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775306,"web_url":"http://patchwork.ozlabs.org/comment/1775306/","msgid":"<1506419533.2109.2.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T09:52:16","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > These drivers handle FPGA program operation from flash loading\r\n> > RBF to memory and then to program FPGA.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> Did you run checkpatch on this before submitting ? I presume no ...\r\n> \r\n> > \r\n> > ---\r\n> >  .../include/mach/fpga_manager_arria10.h            |  27 ++\r\n> >  drivers/fpga/socfpga_arria10.c                     | 391\r\n> > ++++++++++++++++++++-\r\n> >  include/altera.h                                   |   6 +\r\n> >  include/configs/socfpga_common.h                   |   4 +\r\n> >  4 files changed, 425 insertions(+), 3 deletions(-)\r\n> [...]\r\n> \r\n> > \r\n> > @@ -112,13 +122,14 @@ static int\r\n> > wait_for_nconfig_pin_and_nstatus_pin(void)\r\n> >  \tunsigned long mask =\r\n> > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\r\n> >  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU\r\n> > S_PIN_SET_MSK;\r\n> >  \r\n> > -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\r\n> > until de-asserted,\r\n> > -\t * timeout at 1000ms\r\n> > +\t/*\r\n> > +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\r\n> > until\r\n> > +\t * de-asserted, timeout at 1000ms\r\n> >  \t */\r\n> >  \treturn wait_for_bit(__func__,\r\n> >  \t\t\t    &fpga_manager_base->imgcfg_stat,\r\n> >  \t\t\t    mask,\r\n> > -\t\t\t    false, FPGA_TIMEOUT_MSEC, false);\r\n> > +\t\t\t    true, FPGA_TIMEOUT_MSEC, false);\r\n> >  }\r\n> Seems more like a fix, split this out.\r\n> \r\n> > \r\n> >  static int wait_for_f2s_nstatus_pin(unsigned long value)\r\n> > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void\r\n> > *rbf_data, size_t rbf_size)\r\n> >  \r\n> >  \t/* Initialize the FPGA Manager */\r\n> >  \tstatus = fpgamgr_program_init((u32 *)rbf_data, rbf_size);\r\n> > +\r\n> >  \tif (status)\r\n> >  \t\treturn status;\r\n> >  \r\n> > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const\r\n> > void *rbf_data, size_t rbf_size)\r\n> >  \r\n> >  \treturn fpgamgr_program_finish();\r\n> >  }\r\n> > +\r\n> > +#if defined(CONFIG_CMD_FPGA_LOADFS)\r\n> > +const char *get_cff_filename(const void *fdt, int *len, u32 core)\r\n> > +{\r\n> > +\tconst char *cff_filename = NULL;\r\n> > +\tconst char *cell;\r\n> > +\tint nodeoffset;\r\n> > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > +\r\n> > +\tif (nodeoffset >= 0) {\r\n> > +\t\tif (core)\r\n> > +\t\t\tcell = fdt_getprop(fdt,\r\n> > +\t\t\t\t\tnodeoffset,\r\n> > +\t\t\t\t\t\"bitstream_core\",\r\n> > +\t\t\t\t\tlen);\r\n> > +\t\telse\r\n> > +\t\t\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > \"bitstream_periph\",\r\n> > +\t\t\t\t\t len);\r\n> > +\r\n> > +\t\tif (cell)\r\n> > +\t\t\tcff_filename = cell;\r\n> > +\t}\r\n> > +\r\n> > +\treturn cff_filename;\r\n> > +}\r\n> > +\r\n> > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > +{\r\n> > +\tconst char *cff_devpart = NULL;\r\n> > +\tconst char *cell;\r\n> > +\tint nodeoffset;\r\n> > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > +\r\n> > +\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\",\r\n> > len);\r\n> > +\r\n> > +\tif (cell)\r\n> > +\t\tcff_devpart = cell;\r\n> > +\r\n> > +\treturn cff_devpart;\r\n> > +}\r\n> Take a look at splash*.c , I believe that can be reworked into\r\n> generic\r\n> firmware loader , which you could then use here.\r\n> \r\nthe devpart is hard coded in splash*.c. The function here is getting\r\ndevpart info from DTS. So, is there any similar function in splash*.c?\r\nMay be you can share more about your idea.\r\n> [...]\r\n> \r\n> > \r\n> > diff --git a/include/configs/socfpga_common.h\r\n> > b/include/configs/socfpga_common.h\r\n> > index 9897e11..eadce2d 100644\r\n> > --- a/include/configs/socfpga_common.h\r\n> > +++ b/include/configs/socfpga_common.h\r\n> > @@ -27,7 +27,11 @@\r\n> >   */\r\n> >  #define CONFIG_NR_DRAM_BANKS\t\t1\r\n> >  #define PHYS_SDRAM_1\t\t\t0x0\r\n> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 * 1024)\r\n> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 * 1024)\r\n> > +#endif\r\n> You definitely don't need 128 MiB of malloc area.\r\n> \r\n> > \r\n> >  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\r\n> >  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE\r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1bpn40kvz9tXb\n\tfor ;\n\tTue, 26 Sep 2017 19:52:33 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 6A092C21E43; Tue, 26 Sep 2017 09:52:26 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4025BC21D5B;\n\tTue, 26 Sep 2017 09:52:24 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 7835EC21D5B; Tue, 26 Sep 2017 09:52:22 +0000 (UTC)","from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby lists.denx.de (Postfix) with ESMTPS id 63B33C21C93\n\tfor ; Tue, 26 Sep 2017 09:52:21 +0000 (UTC)","from orsmga004.jf.intel.com ([10.7.209.38])\n\tby orsmga104.jf.intel.com with ESMTP; 26 Sep 2017 02:52:19 -0700","from pgsmsx101.gar.corp.intel.com ([10.221.44.78])\n\tby orsmga004.jf.intel.com with ESMTP; 26 Sep 2017 02:52:17 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX101.gar.corp.intel.com ([169.254.1.141]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 17:52:16 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,440,1500966000\"; d=\"scan'208\";a=\"132406156\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGdAYA=","Date":"Tue, 26 Sep 2017 09:52:16 +0000","Message-ID":"<1506419533.2109.2.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>","In-Reply-To":"<995ab037-992e-5782-4faf-8965d039c841@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775371,"web_url":"http://patchwork.ozlabs.org/comment/1775371/","msgid":"","list_archive_url":null,"date":"2017-09-26T10:32:41","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> These drivers handle FPGA program operation from flash loading\n>>> RBF to memory and then to program FPGA.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>> Did you run checkpatch on this before submitting ? I presume no ...\n>>\n> Yeah, i run checkpatch for all patches. What's the issue here?\n\nIt should definitely indicate problem with ie. yoda-notation\n+if (0 == flashinfo->remaining) {\nand indent ...\n\n>>>\n>>> ---\n>>>  .../include/mach/fpga_manager_arria10.h            |  27 ++\n>>>  drivers/fpga/socfpga_arria10.c                     | 391\n>>> ++++++++++++++++++++-\n>>>  include/altera.h                                   |   6 +\n>>>  include/configs/socfpga_common.h                   |   4 +\n>>>  4 files changed, 425 insertions(+), 3 deletions(-)\n>> [...]\n>>\n>>>\n>>> @@ -112,13 +122,14 @@ static int\n>>> wait_for_nconfig_pin_and_nstatus_pin(void)\n>>>  \tunsigned long mask =\n>>> ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\n>>>  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU\n>>> S_PIN_SET_MSK;\n>>>  \n>>> -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\n>>> until de-asserted,\n>>> -\t * timeout at 1000ms\n>>> +\t/*\n>>> +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop\n>>> until\n>>> +\t * de-asserted, timeout at 1000ms\n>>>  \t */\n>>>  \treturn wait_for_bit(__func__,\n>>>  \t\t\t    &fpga_manager_base->imgcfg_stat,\n>>>  \t\t\t    mask,\n>>> -\t\t\t    false, FPGA_TIMEOUT_MSEC, false);\n>>> +\t\t\t    true, FPGA_TIMEOUT_MSEC, false);\n>>>  }\n>> Seems more like a fix, split this out.\n>>\n> Okay.\n>>>\n>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)\n>>> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void\n>>> *rbf_data, size_t rbf_size)\n>>>  \n>>>  \t/* Initialize the FPGA Manager */\n>>>  \tstatus = fpgamgr_program_init((u32 *)rbf_data, rbf_size);\n>>> +\n>>>  \tif (status)\n>>>  \t\treturn status;\n>>>  \n>>> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const\n>>> void *rbf_data, size_t rbf_size)\n>>>  \n>>>  \treturn fpgamgr_program_finish();\n>>>  }\n>>> +\n>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)\n>>> +const char *get_cff_filename(const void *fdt, int *len, u32 core)\n>>> +{\n>>> +\tconst char *cff_filename = NULL;\n>>> +\tconst char *cell;\n>>> +\tint nodeoffset;\n>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>> +\n>>> +\tif (nodeoffset >= 0) {\n>>> +\t\tif (core)\n>>> +\t\t\tcell = fdt_getprop(fdt,\n>>> +\t\t\t\t\tnodeoffset,\n>>> +\t\t\t\t\t\"bitstream_core\",\n>>> +\t\t\t\t\tlen);\n>>> +\t\telse\n>>> +\t\t\tcell = fdt_getprop(fdt, nodeoffset,\n>>> \"bitstream_periph\",\n>>> +\t\t\t\t\t len);\n>>> +\n>>> +\t\tif (cell)\n>>> +\t\t\tcff_filename = cell;\n>>> +\t}\n>>> +\n>>> +\treturn cff_filename;\n>>> +}\n>>> +\n>>> +const char *get_cff_devpart(const void *fdt, int *len)\n>>> +{\n>>> +\tconst char *cff_devpart = NULL;\n>>> +\tconst char *cell;\n>>> +\tint nodeoffset;\n>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>> +\n>>> +\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\",\n>>> len);\n>>> +\n>>> +\tif (cell)\n>>> +\t\tcff_devpart = cell;\n>>> +\n>>> +\treturn cff_devpart;\n>>> +}\n>> Take a look at splash*.c , I believe that can be reworked into\n>> generic\n>> firmware loader , which you could then use here.\n\nThis is important here, I don't want yet another ad-hoc loader ...\n\n>> [...]\n>>\n>>>\n>>> diff --git a/include/configs/socfpga_common.h\n>>> b/include/configs/socfpga_common.h\n>>> index 9897e11..eadce2d 100644\n>>> --- a/include/configs/socfpga_common.h\n>>> +++ b/include/configs/socfpga_common.h\n>>> @@ -27,7 +27,11 @@\n>>>   */\n>>>  #define CONFIG_NR_DRAM_BANKS\t\t1\n>>>  #define PHYS_SDRAM_1\t\t\t0x0\n>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 * 1024)\n>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>> +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 * 1024)\n>>> +#endif\n>> You definitely don't need 128 MiB of malloc area.\n>>\n> Okay, i will try out with smaller size.\n\nWhy do you need such massive area ? It's not a matter of \"try out\", you\nshould know why this change was needed for your use-case.\n\n>>>\n>>>  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\n>>>  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE\n>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1dV41qrcz9tXP\n\tfor ;\n\tTue, 26 Sep 2017 21:08:12 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E851EC21F1D; Tue, 26 Sep 2017 11:07:47 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 81692C21DC6;\n\tTue, 26 Sep 2017 11:07:37 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 2B0ADC21F03; Tue, 26 Sep 2017 11:07:33 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id 6784DC21E24\n\tfor ; Tue, 26 Sep 2017 11:07:29 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y1dTF1Khmz1qsjl;\n\tTue, 26 Sep 2017 13:07:29 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y1dTD70m9z1r0wb;\n\tTue, 26 Sep 2017 13:07:26 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id pLcv80AsriXk; Tue, 26 Sep 2017 13:07:24 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:24 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"UHkm2EMmwKNrb/LSK1ae/d+cnh+hQcZt4jEHGPb0JNg=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506414635.27760.26.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Tue, 26 Sep 2017 12:32:41 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506414635.27760.26.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775379,"web_url":"http://patchwork.ozlabs.org/comment/1775379/","msgid":"<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>","list_archive_url":null,"date":"2017-09-26T10:39:35","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> These drivers handle FPGA program operation from flash loading\n>>> RBF to memory and then to program FPGA.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n\n[...]\n\n>>> +const char *get_cff_devpart(const void *fdt, int *len)\n>>> +{\n>>> +\tconst char *cff_devpart = NULL;\n>>> +\tconst char *cell;\n>>> +\tint nodeoffset;\n>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>> +\n>>> +\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\",\n>>> len);\n>>> +\n>>> +\tif (cell)\n>>> +\t\tcff_devpart = cell;\n>>> +\n>>> +\treturn cff_devpart;\n>>> +}\n>> Take a look at splash*.c , I believe that can be reworked into\n>> generic\n>> firmware loader , which you could then use here.\n>>\n> the devpart is hard coded in splash*.c. The function here is getting\n> devpart info from DTS. So, is there any similar function in splash*.c?\n> May be you can share more about your idea.\n\nThe generic loader could use some work of course ...\n\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1dc44mF8z9tXf\n\tfor ;\n\tTue, 26 Sep 2017 21:13:24 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 7568FC21F47; Tue, 26 Sep 2017 11:12:45 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C8401C21EC9;\n\tTue, 26 Sep 2017 11:08:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 9E395C21F1F; Tue, 26 Sep 2017 11:07:46 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10])\n\tby lists.denx.de (Postfix) with ESMTPS id 9A5A3C21F05\n\tfor ; Tue, 26 Sep 2017 11:07:43 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y1dTW2t0wz1qtXX;\n\tTue, 26 Sep 2017 13:07:43 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y1dTW25bZz1r0wd;\n\tTue, 26 Sep 2017 13:07:43 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id bDDvnzSKoNw3; Tue, 26 Sep 2017 13:07:42 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:42 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"uESHAQslWO9YY7XOHM00+0bNyzhpu1Gfh18cdIQqa9A=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506419533.2109.2.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>","Date":"Tue, 26 Sep 2017 12:39:35 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506419533.2109.2.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776045,"web_url":"http://patchwork.ozlabs.org/comment/1776045/","msgid":"<1506492302.3589.26.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T06:05:06","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > These drivers handle FPGA program operation from flash loading\r\n> > > > RBF to memory and then to program FPGA.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > Did you run checkpatch on this before submitting ? I presume no\r\n> > > ...\r\n> > > \r\n> > Yeah, i run checkpatch for all patches. What's the issue here?\r\n> It should definitely indicate problem with ie. yoda-notation\r\n> +if (0 == flashinfo->remaining) {\r\n> and indent ...\r\n> \r\nNo complaint from checkpath. I know someone saying bad for readbility,\r\nbut yoda-notation at this simple implementation doesn't impact the\r\nreadbility, and having benefit to leverage detection of compiler on\r\nmissing \"=\". Overall, this can help to improve coding quality. I can\r\nremove it if this doesn't favored in U-boot.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > ---\r\n> > > >  .../include/mach/fpga_manager_arria10.h            |  27 ++\r\n> > > >  drivers/fpga/socfpga_arria10.c                     | 391\r\n> > > > ++++++++++++++++++++-\r\n> > > >  include/altera.h                                   |   6 +\r\n> > > >  include/configs/socfpga_common.h                   |   4 +\r\n> > > >  4 files changed, 425 insertions(+), 3 deletions(-)\r\n> > > [...]\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > @@ -112,13 +122,14 @@ static int\r\n> > > > wait_for_nconfig_pin_and_nstatus_pin(void)\r\n> > > >  \tunsigned long mask =\r\n> > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\r\n> > > >  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NS\r\n> > > > TATU\r\n> > > > S_PIN_SET_MSK;\r\n> > > >  \r\n> > > > -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;\r\n> > > > loop\r\n> > > > until de-asserted,\r\n> > > > -\t * timeout at 1000ms\r\n> > > > +\t/*\r\n> > > > +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin;\r\n> > > > loop\r\n> > > > until\r\n> > > > +\t * de-asserted, timeout at 1000ms\r\n> > > >  \t */\r\n> > > >  \treturn wait_for_bit(__func__,\r\n> > > >  \t\t\t    &fpga_manager_base->imgcfg_stat,\r\n> > > >  \t\t\t    mask,\r\n> > > > -\t\t\t    false, FPGA_TIMEOUT_MSEC, false);\r\n> > > > +\t\t\t    true, FPGA_TIMEOUT_MSEC, false);\r\n> > > >  }\r\n> > > Seems more like a fix, split this out.\r\n> > > \r\n> > Okay.\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)\r\n> > > > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const\r\n> > > > void\r\n> > > > *rbf_data, size_t rbf_size)\r\n> > > >  \r\n> > > >  \t/* Initialize the FPGA Manager */\r\n> > > >  \tstatus = fpgamgr_program_init((u32 *)rbf_data,\r\n> > > > rbf_size);\r\n> > > > +\r\n> > > >  \tif (status)\r\n> > > >  \t\treturn status;\r\n> > > >  \r\n> > > > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const\r\n> > > > void *rbf_data, size_t rbf_size)\r\n> > > >  \r\n> > > >  \treturn fpgamgr_program_finish();\r\n> > > >  }\r\n> > > > +\r\n> > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)\r\n> > > > +const char *get_cff_filename(const void *fdt, int *len, u32\r\n> > > > core)\r\n> > > > +{\r\n> > > > +\tconst char *cff_filename = NULL;\r\n> > > > +\tconst char *cell;\r\n> > > > +\tint nodeoffset;\r\n> > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > +\r\n> > > > +\tif (nodeoffset >= 0) {\r\n> > > > +\t\tif (core)\r\n> > > > +\t\t\tcell = fdt_getprop(fdt,\r\n> > > > +\t\t\t\t\tnodeoffset,\r\n> > > > +\t\t\t\t\t\"bitstream_core\",\r\n> > > > +\t\t\t\t\tlen);\r\n> > > > +\t\telse\r\n> > > > +\t\t\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > > > \"bitstream_periph\",\r\n> > > > +\t\t\t\t\t len);\r\n> > > > +\r\n> > > > +\t\tif (cell)\r\n> > > > +\t\t\tcff_filename = cell;\r\n> > > > +\t}\r\n> > > > +\r\n> > > > +\treturn cff_filename;\r\n> > > > +}\r\n> > > > +\r\n> > > > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > > > +{\r\n> > > > +\tconst char *cff_devpart = NULL;\r\n> > > > +\tconst char *cell;\r\n> > > > +\tint nodeoffset;\r\n> > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > +\r\n> > > > +\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > > > \"bitstream_devpart\",\r\n> > > > len);\r\n> > > > +\r\n> > > > +\tif (cell)\r\n> > > > +\t\tcff_devpart = cell;\r\n> > > > +\r\n> > > > +\treturn cff_devpart;\r\n> > > > +}\r\n> > > Take a look at splash*.c , I believe that can be reworked into\r\n> > > generic\r\n> > > firmware loader , which you could then use here.\r\n> This is important here, I don't want yet another ad-hoc loader ...\r\n> \r\nDisucss in another email reply separately. I need time to think.\r\n> > \r\n> > > \r\n> > > [...]\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > b/include/configs/socfpga_common.h\r\n> > > > index 9897e11..eadce2d 100644\r\n> > > > --- a/include/configs/socfpga_common.h\r\n> > > > +++ b/include/configs/socfpga_common.h\r\n> > > > @@ -27,7 +27,11 @@\r\n> > > >   */\r\n> > > >  #define CONFIG_NR_DRAM_BANKS\t\t1\r\n> > > >  #define PHYS_SDRAM_1\t\t\t0x0\r\n> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > >  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 *\r\n> > > > 1024)\r\n> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 *\r\n> > > > 1024)\r\n> > > > +#endif\r\n> > > You definitely don't need 128 MiB of malloc area.\r\n> > > \r\n> > Okay, i will try out with smaller size.\r\n> Why do you need such massive area ? It's not a matter of \"try out\",\r\n> you\r\n> should know why this change was needed for your use-case.\r\n> \r\nI forgot what reason i put this value. I need to find out.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > >  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\r\n> > > >  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZ\r\n> > > > E\r\n> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y26kT48hpz9t3F\n\tfor ;\n\tWed, 27 Sep 2017 16:05:37 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid A9620C21C93; Wed, 27 Sep 2017 06:05:33 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3AA8BC21C45;\n\tWed, 27 Sep 2017 06:05:28 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 72C49C21C45; Wed, 27 Sep 2017 06:05:26 +0000 (UTC)","from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby lists.denx.de (Postfix) with ESMTPS id 5C6FDC21C40\n\tfor ; Wed, 27 Sep 2017 06:05:22 +0000 (UTC)","from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 23:05:19 -0700","from pgsmsx102.gar.corp.intel.com ([10.221.44.80])\n\tby FMSMGA003.fm.intel.com with ESMTP; 26 Sep 2017 23:05:18 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX102.gar.corp.intel.com ([169.254.6.144]) with mapi id\n\t14.03.0319.002; Wed, 27 Sep 2017 14:05:13 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,443,1500966000\"; d=\"scan'208\";a=\"904252348\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGGMoCAACIdgIABR40A","Date":"Wed, 27 Sep 2017 06:05:06 +0000","Message-ID":"<1506492302.3589.26.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506414635.27760.26.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<6C463455AF0FE24D9316012F44A29CD4@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776177,"web_url":"http://patchwork.ozlabs.org/comment/1776177/","msgid":"","list_archive_url":null,"date":"2017-09-27T08:30:34","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/27/2017 08:05 AM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:\n>> On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> These drivers handle FPGA program operation from flash loading\n>>>>> RBF to memory and then to program FPGA.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>>>> Did you run checkpatch on this before submitting ? I presume no\n>>>> ...\n>>>>\n>>> Yeah, i run checkpatch for all patches. What's the issue here?\n>> It should definitely indicate problem with ie. yoda-notation\n>> +if (0 == flashinfo->remaining) {\n>> and indent ...\n>>\n> No complaint from checkpath. I know someone saying bad for readbility,\n> but yoda-notation at this simple implementation doesn't impact the\n> readbility, and having benefit to leverage detection of compiler on\n> missing \"=\". Overall, this can help to improve coding quality. I can\n> remove it if this doesn't favored in U-boot.\n\nIt is not welcome and modern gcc warns you about such things .\n\n>>>\n>>>>\n>>>>>\n>>>>>\n>>>>> ---\n>>>>>  .../include/mach/fpga_manager_arria10.h            |  27 ++\n>>>>>  drivers/fpga/socfpga_arria10.c                     | 391\n>>>>> ++++++++++++++++++++-\n>>>>>  include/altera.h                                   |   6 +\n>>>>>  include/configs/socfpga_common.h                   |   4 +\n>>>>>  4 files changed, 425 insertions(+), 3 deletions(-)\n>>>> [...]\n>>>>\n>>>>>\n>>>>>\n>>>>> @@ -112,13 +122,14 @@ static int\n>>>>> wait_for_nconfig_pin_and_nstatus_pin(void)\n>>>>>  \tunsigned long mask =\n>>>>> ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\n>>>>>  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NS\n>>>>> TATU\n>>>>> S_PIN_SET_MSK;\n>>>>>  \n>>>>> -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;\n>>>>> loop\n>>>>> until de-asserted,\n>>>>> -\t * timeout at 1000ms\n>>>>> +\t/*\n>>>>> +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin;\n>>>>> loop\n>>>>> until\n>>>>> +\t * de-asserted, timeout at 1000ms\n>>>>>  \t */\n>>>>>  \treturn wait_for_bit(__func__,\n>>>>>  \t\t\t    &fpga_manager_base->imgcfg_stat,\n>>>>>  \t\t\t    mask,\n>>>>> -\t\t\t    false, FPGA_TIMEOUT_MSEC, false);\n>>>>> +\t\t\t    true, FPGA_TIMEOUT_MSEC, false);\n>>>>>  }\n>>>> Seems more like a fix, split this out.\n>>>>\n>>> Okay.\n>>>>\n>>>>>\n>>>>>\n>>>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)\n>>>>> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const\n>>>>> void\n>>>>> *rbf_data, size_t rbf_size)\n>>>>>  \n>>>>>  \t/* Initialize the FPGA Manager */\n>>>>>  \tstatus = fpgamgr_program_init((u32 *)rbf_data,\n>>>>> rbf_size);\n>>>>> +\n>>>>>  \tif (status)\n>>>>>  \t\treturn status;\n>>>>>  \n>>>>> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const\n>>>>> void *rbf_data, size_t rbf_size)\n>>>>>  \n>>>>>  \treturn fpgamgr_program_finish();\n>>>>>  }\n>>>>> +\n>>>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)\n>>>>> +const char *get_cff_filename(const void *fdt, int *len, u32\n>>>>> core)\n>>>>> +{\n>>>>> +\tconst char *cff_filename = NULL;\n>>>>> +\tconst char *cell;\n>>>>> +\tint nodeoffset;\n>>>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>>>> +\n>>>>> +\tif (nodeoffset >= 0) {\n>>>>> +\t\tif (core)\n>>>>> +\t\t\tcell = fdt_getprop(fdt,\n>>>>> +\t\t\t\t\tnodeoffset,\n>>>>> +\t\t\t\t\t\"bitstream_core\",\n>>>>> +\t\t\t\t\tlen);\n>>>>> +\t\telse\n>>>>> +\t\t\tcell = fdt_getprop(fdt, nodeoffset,\n>>>>> \"bitstream_periph\",\n>>>>> +\t\t\t\t\t len);\n>>>>> +\n>>>>> +\t\tif (cell)\n>>>>> +\t\t\tcff_filename = cell;\n>>>>> +\t}\n>>>>> +\n>>>>> +\treturn cff_filename;\n>>>>> +}\n>>>>> +\n>>>>> +const char *get_cff_devpart(const void *fdt, int *len)\n>>>>> +{\n>>>>> +\tconst char *cff_devpart = NULL;\n>>>>> +\tconst char *cell;\n>>>>> +\tint nodeoffset;\n>>>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>>>> +\n>>>>> +\tcell = fdt_getprop(fdt, nodeoffset,\n>>>>> \"bitstream_devpart\",\n>>>>> len);\n>>>>> +\n>>>>> +\tif (cell)\n>>>>> +\t\tcff_devpart = cell;\n>>>>> +\n>>>>> +\treturn cff_devpart;\n>>>>> +}\n>>>> Take a look at splash*.c , I believe that can be reworked into\n>>>> generic\n>>>> firmware loader , which you could then use here.\n>> This is important here, I don't want yet another ad-hoc loader ...\n>>\n> Disucss in another email reply separately. I need time to think.\n>>>\n>>>>\n>>>> [...]\n>>>>\n>>>>>\n>>>>>\n>>>>> diff --git a/include/configs/socfpga_common.h\n>>>>> b/include/configs/socfpga_common.h\n>>>>> index 9897e11..eadce2d 100644\n>>>>> --- a/include/configs/socfpga_common.h\n>>>>> +++ b/include/configs/socfpga_common.h\n>>>>> @@ -27,7 +27,11 @@\n>>>>>   */\n>>>>>  #define CONFIG_NR_DRAM_BANKS\t\t1\n>>>>>  #define PHYS_SDRAM_1\t\t\t0x0\n>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>>>  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 *\n>>>>> 1024)\n>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>>>> +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 *\n>>>>> 1024)\n>>>>> +#endif\n>>>> You definitely don't need 128 MiB of malloc area.\n>>>>\n>>> Okay, i will try out with smaller size.\n>> Why do you need such massive area ? It's not a matter of \"try out\",\n>> you\n>> should know why this change was needed for your use-case.\n>>\n> I forgot what reason i put this value. I need to find out.\n\nIf this was properly documented in the commit message, you would not\nhave to ...\n\n>>>\n>>>>\n>>>>>\n>>>>>\n>>>>>  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\n>>>>>  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZ\n>>>>> E\n>>>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2C8k4Pp7z9tXT\n\tfor ;\n\tWed, 27 Sep 2017 19:25:09 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 11618C21DEB; Wed, 27 Sep 2017 09:25:06 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 2B277C21E2C;\n\tWed, 27 Sep 2017 08:59:39 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid EE222C21DE7; Wed, 27 Sep 2017 08:59:36 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id 513B9C21E06\n\tfor ; Wed, 27 Sep 2017 08:58:17 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y2BYh6QzGz1qqyj;\n\tWed, 27 Sep 2017 10:58:16 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y2BYh5hzzz1qrlq;\n\tWed, 27 Sep 2017 10:58:16 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id CdLeGr423sq7; Wed, 27 Sep 2017 10:58:15 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tWed, 27 Sep 2017 10:58:15 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"2nlPU9GCgetfmThc6dj8813IwbROpZ0jfXUOkTLHW5o=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506414635.27760.26.camel@intel.com>\n\t\n\t<1506492302.3589.26.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Wed, 27 Sep 2017 10:30:34 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506492302.3589.26.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776195,"web_url":"http://patchwork.ozlabs.org/comment/1776195/","msgid":"<1506503592.3589.37.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T09:13:12","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > These drivers handle FPGA program operation from flash loading\r\n> > > > RBF to memory and then to program FPGA.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> [...]\r\n> \r\n> > \r\n> > > \r\n> > > > \r\n> > > > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > > > +{\r\n> > > > +\tconst char *cff_devpart = NULL;\r\n> > > > +\tconst char *cell;\r\n> > > > +\tint nodeoffset;\r\n> > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > +\r\n> > > > +\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > > > \"bitstream_devpart\",\r\n> > > > len);\r\n> > > > +\r\n> > > > +\tif (cell)\r\n> > > > +\t\tcff_devpart = cell;\r\n> > > > +\r\n> > > > +\treturn cff_devpart;\r\n> > > > +}\r\n> > > Take a look at splash*.c , I believe that can be reworked into\r\n> > > generic\r\n> > > firmware loader , which you could then use here.\r\n> > > \r\n> > the devpart is hard coded in splash*.c. The function here is\r\n> > getting\r\n> > devpart info from DTS. So, is there any similar function in\r\n> > splash*.c?\r\n> > May be you can share more about your idea.\r\n> The generic loader could use some work of course ...\r\n> \r\nSorry, i am still confusing. Allow me to ask you more:\r\n1. Is the generic firmware loader already exists in splash*.c?\r\n2. Are you talking about get_cff_devpart or whole fpga laodfs?\r\n3. You want me integrate get_cff_devpart function into splash*.c?\r\n4. Are you means to hard code the devpart instead providing dynamic\r\ndevpart described in DTS?\r\n\r\nCurrent implementation are located in spl_board_init func\r\n(arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc, nand\r\nand QSPI, then reading some info from DTS, setting dev and partition\r\nwith generic fs functions, and reading with generic fs function before\r\nprogramming RBF into FPGA. All these are in patch 19.\r\n\r\nThanks.\r\n> [...]\r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Cmy4nV2z9tXs\n\tfor ;\n\tWed, 27 Sep 2017 19:53:06 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 44662C21DE7; Wed, 27 Sep 2017 09:53:05 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DD2FCC21DF4;\n\tWed, 27 Sep 2017 09:15:32 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 69EBBC21D99; Wed, 27 Sep 2017 09:15:31 +0000 (UTC)","from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 3475BC21D8C\n\tfor ; Wed, 27 Sep 2017 09:13:18 +0000 (UTC)","from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Sep 2017 02:13:15 -0700","from pgsmsx108.gar.corp.intel.com ([10.221.44.103])\n\tby fmsmga001.fm.intel.com with ESMTP; 27 Sep 2017 02:13:14 -0700","from pgsmsx112.gar.corp.intel.com (10.108.55.201) by\n\tPGSMSX108.gar.corp.intel.com (10.221.44.103) with Microsoft SMTP\n\tServer (TLS) id 14.3.319.2; Wed, 27 Sep 2017 17:13:13 +0800","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX112.gar.corp.intel.com ([10.108.55.201]) with mapi id\n\t14.03.0248.002; Wed, 27 Sep 2017 17:13:13 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,444,1500966000\"; d=\"scan'208\";\n\ta=\"1199530688\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGdAYCAAA08gIABejIA","Date":"Wed, 27 Sep 2017 09:13:12 +0000","Message-ID":"<1506503592.3589.37.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506419533.2109.2.camel@intel.com>\n\t<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>","In-Reply-To":"<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<4599F66513ECC3458A6D13BAB513CDE0@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776210,"web_url":"http://patchwork.ozlabs.org/comment/1776210/","msgid":"","list_archive_url":null,"date":"2017-09-27T09:23:41","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:\n>> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> These drivers handle FPGA program operation from flash loading\n>>>>> RBF to memory and then to program FPGA.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>> [...]\n>>\n>>>\n>>>>\n>>>>>\n>>>>> +const char *get_cff_devpart(const void *fdt, int *len)\n>>>>> +{\n>>>>> +\tconst char *cff_devpart = NULL;\n>>>>> +\tconst char *cell;\n>>>>> +\tint nodeoffset;\n>>>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>>>> +\n>>>>> +\tcell = fdt_getprop(fdt, nodeoffset,\n>>>>> \"bitstream_devpart\",\n>>>>> len);\n>>>>> +\n>>>>> +\tif (cell)\n>>>>> +\t\tcff_devpart = cell;\n>>>>> +\n>>>>> +\treturn cff_devpart;\n>>>>> +}\n>>>> Take a look at splash*.c , I believe that can be reworked into\n>>>> generic\n>>>> firmware loader , which you could then use here.\n>>>>\n>>> the devpart is hard coded in splash*.c. The function here is\n>>> getting\n>>> devpart info from DTS. So, is there any similar function in\n>>> splash*.c?\n>>> May be you can share more about your idea.\n>> The generic loader could use some work of course ...\n>>\n> Sorry, i am still confusing. Allow me to ask you more:\n> 1. Is the generic firmware loader already exists in splash*.c?\n\nNo\n\n> 2. Are you talking about get_cff_devpart or whole fpga laodfs?\n> 3. You want me integrate get_cff_devpart function into splash*.c?\n> 4. Are you means to hard code the devpart instead providing dynamic\n> devpart described in DTS?\n\nI am talking about factoring out generic firmware loader from splash*c ,\nsince it already contains most of the parts for such a thing.\n\n> Current implementation are located in spl_board_init func\n> (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc, nand\n> and QSPI, then reading some info from DTS, setting dev and partition\n> with generic fs functions, and reading with generic fs function before\n> programming RBF into FPGA. All these are in patch 19.\n\nThat's what splash*c also does, so adding separate parallel\nimplementation of the same functionality is a no-no.\n\n> Thanks.\n>> [...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2DHt6jNxz9t66\n\tfor ;\n\tWed, 27 Sep 2017 20:16:26 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid A05ADC21E65; Wed, 27 Sep 2017 10:16:25 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4CF63C21E6C;\n\tWed, 27 Sep 2017 09:25:18 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid E3FE4C21E40; Wed, 27 Sep 2017 09:25:16 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id DE49AC21E51\n\tfor ; Wed, 27 Sep 2017 09:23:43 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y2C733XzXz1qsDQ;\n\tWed, 27 Sep 2017 11:23:43 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y2C732ljyz1qrm1;\n\tWed, 27 Sep 2017 11:23:43 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id yHWV9igw-0Mp; Wed, 27 Sep 2017 11:23:42 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tWed, 27 Sep 2017 11:23:42 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"vkiZpuqX4FhQsmfPlsxUsGOqT5KErKsdUwnDRvxIjh4=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506419533.2109.2.camel@intel.com>\n\t<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>\n\t<1506503592.3589.37.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Wed, 27 Sep 2017 11:23:41 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506503592.3589.37.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776728,"web_url":"http://patchwork.ozlabs.org/comment/1776728/","msgid":"<1506566738.3589.38.camel@intel.com>","list_archive_url":null,"date":"2017-09-28T02:45:46","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Rab, 2017-09-27 at 10:30 +0200, Marek Vasut wrote:\r\n> On 09/27/2017 08:05 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > These drivers handle FPGA program operation from flash\r\n> > > > > > loading\r\n> > > > > > RBF to memory and then to program FPGA.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > > > Did you run checkpatch on this before submitting ? I presume\r\n> > > > > no\r\n> > > > > ...\r\n> > > > > \r\n> > > > Yeah, i run checkpatch for all patches. What's the issue here?\r\n> > > It should definitely indicate problem with ie. yoda-notation\r\n> > > +if (0 == flashinfo->remaining) {\r\n> > > and indent ...\r\n> > > \r\n> > No complaint from checkpath. I know someone saying bad for\r\n> > readbility,\r\n> > but yoda-notation at this simple implementation doesn't impact the\r\n> > readbility, and having benefit to leverage detection of compiler on\r\n> > missing \"=\". Overall, this can help to improve coding quality. I\r\n> > can\r\n> > remove it if this doesn't favored in U-boot.\r\n> It is not welcome and modern gcc warns you about such things .\r\n> \r\nOkay.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > ---\r\n> > > > > >  .../include/mach/fpga_manager_arria10.h            |  27\r\n> > > > > > ++\r\n> > > > > >  drivers/fpga/socfpga_arria10.c                     | 391\r\n> > > > > > ++++++++++++++++++++-\r\n> > > > > >  include/altera.h                                   |   6 +\r\n> > > > > >  include/configs/socfpga_common.h                   |   4 +\r\n> > > > > >  4 files changed, 425 insertions(+), 3 deletions(-)\r\n> > > > > [...]\r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > @@ -112,13 +122,14 @@ static int\r\n> > > > > > wait_for_nconfig_pin_and_nstatus_pin(void)\r\n> > > > > >  \tunsigned long mask =\r\n> > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\r\n> > > > > >  \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2\r\n> > > > > > S_NS\r\n> > > > > > TATU\r\n> > > > > > S_PIN_SET_MSK;\r\n> > > > > >  \r\n> > > > > > -\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;\r\n> > > > > > loop\r\n> > > > > > until de-asserted,\r\n> > > > > > -\t * timeout at 1000ms\r\n> > > > > > +\t/*\r\n> > > > > > +\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin;\r\n> > > > > > loop\r\n> > > > > > until\r\n> > > > > > +\t * de-asserted, timeout at 1000ms\r\n> > > > > >  \t */\r\n> > > > > >  \treturn wait_for_bit(__func__,\r\n> > > > > >  \t\t\t    &fpga_manager_base-\r\n> > > > > > >imgcfg_stat,\r\n> > > > > >  \t\t\t    mask,\r\n> > > > > > -\t\t\t    false, FPGA_TIMEOUT_MSEC,\r\n> > > > > > false);\r\n> > > > > > +\t\t\t    true, FPGA_TIMEOUT_MSEC,\r\n> > > > > > false);\r\n> > > > > >  }\r\n> > > > > Seems more like a fix, split this out.\r\n> > > > > \r\n> > > > Okay.\r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)\r\n> > > > > > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc,\r\n> > > > > > const\r\n> > > > > > void\r\n> > > > > > *rbf_data, size_t rbf_size)\r\n> > > > > >  \r\n> > > > > >  \t/* Initialize the FPGA Manager */\r\n> > > > > >  \tstatus = fpgamgr_program_init((u32 *)rbf_data,\r\n> > > > > > rbf_size);\r\n> > > > > > +\r\n> > > > > >  \tif (status)\r\n> > > > > >  \t\treturn status;\r\n> > > > > >  \r\n> > > > > > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc,\r\n> > > > > > const\r\n> > > > > > void *rbf_data, size_t rbf_size)\r\n> > > > > >  \r\n> > > > > >  \treturn fpgamgr_program_finish();\r\n> > > > > >  }\r\n> > > > > > +\r\n> > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)\r\n> > > > > > +const char *get_cff_filename(const void *fdt, int *len,\r\n> > > > > > u32\r\n> > > > > > core)\r\n> > > > > > +{\r\n> > > > > > +\tconst char *cff_filename = NULL;\r\n> > > > > > +\tconst char *cell;\r\n> > > > > > +\tint nodeoffset;\r\n> > > > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > > > +\r\n> > > > > > +\tif (nodeoffset >= 0) {\r\n> > > > > > +\t\tif (core)\r\n> > > > > > +\t\t\tcell = fdt_getprop(fdt,\r\n> > > > > > +\t\t\t\t\tnodeoffset,\r\n> > > > > > +\t\t\t\t\t\"bitstream_core\",\r\n> > > > > > +\t\t\t\t\tlen);\r\n> > > > > > +\t\telse\r\n> > > > > > +\t\t\tcell = fdt_getprop(fdt,\r\n> > > > > > nodeoffset,\r\n> > > > > > \"bitstream_periph\",\r\n> > > > > > +\t\t\t\t\t len);\r\n> > > > > > +\r\n> > > > > > +\t\tif (cell)\r\n> > > > > > +\t\t\tcff_filename = cell;\r\n> > > > > > +\t}\r\n> > > > > > +\r\n> > > > > > +\treturn cff_filename;\r\n> > > > > > +}\r\n> > > > > > +\r\n> > > > > > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > > > > > +{\r\n> > > > > > +\tconst char *cff_devpart = NULL;\r\n> > > > > > +\tconst char *cell;\r\n> > > > > > +\tint nodeoffset;\r\n> > > > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > > > +\r\n> > > > > > +\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > > > > > \"bitstream_devpart\",\r\n> > > > > > len);\r\n> > > > > > +\r\n> > > > > > +\tif (cell)\r\n> > > > > > +\t\tcff_devpart = cell;\r\n> > > > > > +\r\n> > > > > > +\treturn cff_devpart;\r\n> > > > > > +}\r\n> > > > > Take a look at splash*.c , I believe that can be reworked\r\n> > > > > into\r\n> > > > > generic\r\n> > > > > firmware loader , which you could then use here.\r\n> > > This is important here, I don't want yet another ad-hoc loader\r\n> > > ...\r\n> > > \r\n> > Disucss in another email reply separately. I need time to think.\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > [...]\r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > > > b/include/configs/socfpga_common.h\r\n> > > > > > index 9897e11..eadce2d 100644\r\n> > > > > > --- a/include/configs/socfpga_common.h\r\n> > > > > > +++ b/include/configs/socfpga_common.h\r\n> > > > > > @@ -27,7 +27,11 @@\r\n> > > > > >   */\r\n> > > > > >  #define CONFIG_NR_DRAM_BANKS\t\t1\r\n> > > > > >  #define PHYS_SDRAM_1\t\t\t0x0\r\n> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > > > >  #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 *\r\n> > > > > > 1024)\r\n> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > > > +#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 *\r\n> > > > > > 1024)\r\n> > > > > > +#endif\r\n> > > > > You definitely don't need 128 MiB of malloc area.\r\n> > > > > \r\n> > > > Okay, i will try out with smaller size.\r\n> > > Why do you need such massive area ? It's not a matter of \"try\r\n> > > out\",\r\n> > > you\r\n> > > should know why this change was needed for your use-case.\r\n> > > \r\n> > I forgot what reason i put this value. I need to find out.\r\n> If this was properly documented in the commit message, you would not\r\n> have to ...\r\n> \r\nOkay.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > >  #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\r\n> > > > > >  #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1\r\n> > > > > > _SIZ\r\n> > > > > > E\r\n> > > > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2fHR62xwz9t5C\n\tfor ;\n\tThu, 28 Sep 2017 12:47:31 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid AE934C21D78; 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d=\"scan'208\";a=\"156936947\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGGMoCAACIdgIABR40AgAAoqQCAATH2AA==","Date":"Thu, 28 Sep 2017 02:45:46 +0000","Message-ID":"<1506566738.3589.38.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506414635.27760.26.camel@intel.com>\n\t\n\t<1506492302.3589.26.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<9F8CB5AE6380F64C9C64F0AFB1A83615@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777097,"web_url":"http://patchwork.ozlabs.org/comment/1777097/","msgid":"<1506611647.3589.70.camel@intel.com>","list_archive_url":null,"date":"2017-09-28T15:14:09","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Rab, 2017-09-27 at 11:23 +0200, Marek Vasut wrote:\r\n> On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > These drivers handle FPGA program operation from flash\r\n> > > > > > loading\r\n> > > > > > RBF to memory and then to program FPGA.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > [...]\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > +const char *get_cff_devpart(const void *fdt, int *len)\r\n> > > > > > +{\r\n> > > > > > +\tconst char *cff_devpart = NULL;\r\n> > > > > > +\tconst char *cell;\r\n> > > > > > +\tint nodeoffset;\r\n> > > > > > +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\r\n> > > > > > +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\r\n> > > > > > +\r\n> > > > > > +\tcell = fdt_getprop(fdt, nodeoffset,\r\n> > > > > > \"bitstream_devpart\",\r\n> > > > > > len);\r\n> > > > > > +\r\n> > > > > > +\tif (cell)\r\n> > > > > > +\t\tcff_devpart = cell;\r\n> > > > > > +\r\n> > > > > > +\treturn cff_devpart;\r\n> > > > > > +}\r\n> > > > > Take a look at splash*.c , I believe that can be reworked\r\n> > > > > into\r\n> > > > > generic\r\n> > > > > firmware loader , which you could then use here.\r\n> > > > > \r\n> > > > the devpart is hard coded in splash*.c. The function here is\r\n> > > > getting\r\n> > > > devpart info from DTS. So, is there any similar function in\r\n> > > > splash*.c?\r\n> > > > May be you can share more about your idea.\r\n> > > The generic loader could use some work of course ...\r\n> > > \r\n> > Sorry, i am still confusing. Allow me to ask you more:\r\n> > 1. Is the generic firmware loader already exists in splash*.c?\r\n> No\r\n> \r\n> > \r\n> > 2. Are you talking about get_cff_devpart or whole fpga laodfs?\r\n> > 3. You want me integrate get_cff_devpart function into splash*.c?\r\n> > 4. Are you means to hard code the devpart instead providing dynamic\r\n> > devpart described in DTS?\r\n> I am talking about factoring out generic firmware loader from\r\n> splash*c ,\r\n> since it already contains most of the parts for such a thing.\r\n> \r\n> > \r\n> > Current implementation are located in spl_board_init func\r\n> > (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc,\r\n> > nand\r\n> > and QSPI, then reading some info from DTS, setting dev and\r\n> > partition\r\n> > with generic fs functions, and reading with generic fs function\r\n> > before\r\n> > programming RBF into FPGA. All these are in patch 19.\r\n> That's what splash*c also does, so adding separate parallel\r\n> implementation of the same functionality is a no-no.\r\n> \r\nAfter reading through splash*c, i found there are two functions bear a\r\nclose similarity to.\r\n1st function -->\r\nIn /common/splash.c : \r\nstatic struct splash_location default_splash_locations[] = {\r\n\t{\r\n\t\t.name = \"sf\",\r\n\t\t.storage = SPLASH_STORAGE_SF,\r\n\t\t.flags = SPLASH_STORAGE_RAW,\r\n\t\t.offset = 0x0,\r\n\t},\r\n\t{\r\n\t\t.name = \"mmc_fs\",\r\n\t\t.storage = SPLASH_STORAGE_MMC,\r\n\t\t.flags = SPLASH_STORAGE_FS,\r\n\t\t.devpart = \"0:1\",\r\n\t},\r\n\t{\r\n\t\t.name = \"usb_fs\",\r\n\t\t.storage = SPLASH_STORAGE_USB,\r\n\t\t.flags = SPLASH_STORAGE_FS,\r\n\t\t.devpart = \"0:1\",\r\n\t},\r\n\t{\r\n\t\t.name = \"sata_fs\",\r\n\t\t.storage = SPLASH_STORAGE_SATA,\r\n\t\t.flags = SPLASH_STORAGE_FS,\r\n\t\t.devpart = \"0:1\",\r\n\t},\r\n};\r\n\r\nIn my /arch/arm/mach-socfpga/spl.c (spl_board_init(void))\r\nbootdev.boot_device = spl_boot_device();\r\n\r\n\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\r\n\t\tstruct mmc *mmc = NULL;\r\n\t\tint err = 0;\r\n\r\n\t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\r\n\r\n\t\terr = mmc_init(mmc);\r\n\r\n\t\tif (err) {\r\n#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\r\n\t\t\tprintf(\"spl: mmc init failed with error: %d\\n\",\r\nerr);\r\n#endif\r\n\t\t}\r\n\r\n\t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-\r\n>fdt_blob,\r\n\t\t\t\t\t\t\t\t &len);\r\n\r\n\t\tfpga_fsinfo.filename = (char *)get_cff_filename(gd-\r\n>fdt_blob,\r\n\t\t\t\t\t\t\t\t &len,\r\n\t\t\t\t\t\t\t\tPERIPH_\r\nRBF);\r\n\r\n\t\tfpga_fsinfo.interface = \"mmc\";\r\n\r\n\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\r\n\t} else {\r\n\t\tprintf(\"Invalid boot device!\\n\");\r\n\t\treturn;\r\n\t}\r\n\r\n\t/* Program peripheral RBF */\r\n\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))\r\n\t\trval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);\r\n\r\nIn /common/splash.c, dev_Part and flash type everything are hard coded\r\nin struct splash_location. In my spl.c, flash type are determined on\r\nrun time and dev_part are retrived from DTS, and then assigned to\r\nstruct fpga_fsinfo. Please note that this is in SPL, mmc need to be\r\ninitialized 1st before loading raw file into memory. In SPL, raw file\r\nare coppied to OCRAM chunk by chunk, but In u-boot it would normally\r\ndone in one big chunk to DRAM. This would be handled by fpga loadfs.\r\n\r\nSo, you want me hard code everthing like in splash.c?\r\n\r\n2nd function -->\r\nIn /common/splash_source.c\r\nstatic int splash_select_fs_dev(struct splash_location *location)\r\n{\r\n\tint res;\r\n\r\n\tswitch (location->storage) {\r\n\tcase SPLASH_STORAGE_MMC:\r\n\t\tres = fs_set_blk_dev(\"mmc\", location->devpart,\r\nFS_TYPE_ANY);\r\n\t\tbreak;\r\n\tcase SPLASH_STORAGE_USB:\r\n\t\tres = fs_set_blk_dev(\"usb\", location->devpart,\r\nFS_TYPE_ANY);\r\n\t\tbreak;\r\n\tcase SPLASH_STORAGE_SATA:\r\n\t\tres = fs_set_blk_dev(\"sata\", location->devpart,\r\nFS_TYPE_ANY);\r\n\t\tbreak;\r\n\tcase SPLASH_STORAGE_NAND:\r\n\t\tif (location->ubivol != NULL)\r\n\t\t\tres = fs_set_blk_dev(\"ubi\", NULL,\r\nFS_TYPE_UBIFS);\r\n\t\telse\r\n\t\t\tres = -ENODEV;\r\n\t\tbreak;\r\n\tdefault:\r\n\t\tprintf(\"Error: unsupported location storage.\\n\");\r\n\t\treturn -ENODEV;\r\n\t}\r\n\r\n\tif (res)\r\n\t\tprintf(\"Error: could not access storage.\\n\");\r\n\r\n\treturn res;\r\n}\r\n\r\nIn my /drivers/fpga/socfpga_arria10.c\r\nstatic int flash_read(struct flash_info *flashinfo,\r\n\tu32 size_read,\r\n\tu32 *buffer_ptr)\r\n{\r\n\tsize_t ret = EEXIST;\r\n\tloff_t actread = 0;\r\n\r\n\tif (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,\r\n\t\t\t\tflashinfo->fstype))\r\n\t\treturn FPGA_FAIL;\r\n\r\n\tret = fs_read(flashinfo->filename,\r\n\t\t\t(u32) buffer_ptr, flashinfo->flash_offset,\r\n\t\t\tsize_read, &actread);\r\n\r\n\tif (ret || actread != size_read) {\r\n\t\tprintf(\"Failed to read %s from flash %d \",\r\n\t\t\tflashinfo->filename,\r\n\t\t\t ret);\r\n\t\tprintf(\"!= %d.\\n\", size_read);\r\n\t\treturn -EPERM;\r\n\t\t} else\r\n\t\t\tret = actread;\r\n\r\n\treturn ret;\r\n}\r\n\r\nSome attributes like flash type is determined on run time and and\r\ndev_part is retrieved from DTS, so every infos driver need to know are\r\nassinged into struct flashinfo and passed to fs_set_blk_dev as\r\narguments. I found that function in splash_source.c some like flash\r\ntype are getting from env variable, but we are still in SPL phase,\r\nthose env variable is not set up yet. So, i think that is very\r\nineffcient to factor out them as common.\r\n\r\nIf you want me create a generic firmware loader which is generic enough\r\nloading content for all components like flashes, FPGA, splash ....etc,\r\ni don't think that is effient enough, as fpga loadfs has different\r\nhandling in both SPL and U-boot like copying raw into memory.\r\n\r\nIt would be good you can direct point me out which functions have\r\nsimilirity and how to factor them out as common.\r\n\r\nThanks a lot.\r\n> > \r\n> > Thanks.\r\n> > > \r\n> > > [...]\r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2ysP47qfz9t33\n\tfor ;\n\tFri, 29 Sep 2017 01:14:32 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 43DCFC21DB2; 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d=\"scan'208\";a=\"157147536\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA\n\tfrom flash","Thread-Index":"AQHTNdoBZF62bYhP5UuLVrK/MQr2/KLEy3CAgAGdAYCAAA08gIABejIAgAAC7oCAAfQ9gA==","Date":"Thu, 28 Sep 2017 15:14:09 +0000","Message-ID":"<1506611647.3589.70.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506419533.2109.2.camel@intel.com>\n\t<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>\n\t<1506503592.3589.37.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.255.138.174]","Content-ID":"<3942B74B493BC04D9FB4CF8FAEC4B278@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777098,"web_url":"http://patchwork.ozlabs.org/comment/1777098/","msgid":"<6245ed89-5b34-40b2-9065-a586b07d2ee4@denx.de>","list_archive_url":null,"date":"2017-09-28T15:18:40","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/28/2017 05:14 PM, Chee, Tien Fong wrote:\n> On Rab, 2017-09-27 at 11:23 +0200, Marek Vasut wrote:\n>> On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:\n>>>>>\n>>>>>\n>>>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:\n>>>>>>\n>>>>>>\n>>>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>>>\n>>>>>>>\n>>>>>>>\n>>>>>>> From: Tien Fong Chee \n>>>>>>>\n>>>>>>> These drivers handle FPGA program operation from flash\n>>>>>>> loading\n>>>>>>> RBF to memory and then to program FPGA.\n>>>>>>>\n>>>>>>> Signed-off-by: Tien Fong Chee \n>>>> [...]\n>>>>\n>>>>>\n>>>>>\n>>>>>>\n>>>>>>\n>>>>>>>\n>>>>>>>\n>>>>>>> +const char *get_cff_devpart(const void *fdt, int *len)\n>>>>>>> +{\n>>>>>>> +\tconst char *cff_devpart = NULL;\n>>>>>>> +\tconst char *cell;\n>>>>>>> +\tint nodeoffset;\n>>>>>>> +\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n>>>>>>> +\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n>>>>>>> +\n>>>>>>> +\tcell = fdt_getprop(fdt, nodeoffset,\n>>>>>>> \"bitstream_devpart\",\n>>>>>>> len);\n>>>>>>> +\n>>>>>>> +\tif (cell)\n>>>>>>> +\t\tcff_devpart = cell;\n>>>>>>> +\n>>>>>>> +\treturn cff_devpart;\n>>>>>>> +}\n>>>>>> Take a look at splash*.c , I believe that can be reworked\n>>>>>> into\n>>>>>> generic\n>>>>>> firmware loader , which you could then use here.\n>>>>>>\n>>>>> the devpart is hard coded in splash*.c. The function here is\n>>>>> getting\n>>>>> devpart info from DTS. So, is there any similar function in\n>>>>> splash*.c?\n>>>>> May be you can share more about your idea.\n>>>> The generic loader could use some work of course ...\n>>>>\n>>> Sorry, i am still confusing. Allow me to ask you more:\n>>> 1. Is the generic firmware loader already exists in splash*.c?\n>> No\n>>\n>>>\n>>> 2. Are you talking about get_cff_devpart or whole fpga laodfs?\n>>> 3. You want me integrate get_cff_devpart function into splash*.c?\n>>> 4. Are you means to hard code the devpart instead providing dynamic\n>>> devpart described in DTS?\n>> I am talking about factoring out generic firmware loader from\n>> splash*c ,\n>> since it already contains most of the parts for such a thing.\n>>\n>>>\n>>> Current implementation are located in spl_board_init func\n>>> (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc,\n>>> nand\n>>> and QSPI, then reading some info from DTS, setting dev and\n>>> partition\n>>> with generic fs functions, and reading with generic fs function\n>>> before\n>>> programming RBF into FPGA. All these are in patch 19.\n>> That's what splash*c also does, so adding separate parallel\n>> implementation of the same functionality is a no-no.\n>>\n> After reading through splash*c, i found there are two functions bear a\n> close similarity to.\n> 1st function -->\n> In /common/splash.c : \n> static struct splash_location default_splash_locations[] = {\n> \t{\n> \t\t.name = \"sf\",\n> \t\t.storage = SPLASH_STORAGE_SF,\n> \t\t.flags = SPLASH_STORAGE_RAW,\n> \t\t.offset = 0x0,\n> \t},\n> \t{\n> \t\t.name = \"mmc_fs\",\n> \t\t.storage = SPLASH_STORAGE_MMC,\n> \t\t.flags = SPLASH_STORAGE_FS,\n> \t\t.devpart = \"0:1\",\n> \t},\n> \t{\n> \t\t.name = \"usb_fs\",\n> \t\t.storage = SPLASH_STORAGE_USB,\n> \t\t.flags = SPLASH_STORAGE_FS,\n> \t\t.devpart = \"0:1\",\n> \t},\n> \t{\n> \t\t.name = \"sata_fs\",\n> \t\t.storage = SPLASH_STORAGE_SATA,\n> \t\t.flags = SPLASH_STORAGE_FS,\n> \t\t.devpart = \"0:1\",\n> \t},\n> };\n> \n> In my /arch/arm/mach-socfpga/spl.c (spl_board_init(void))\n> bootdev.boot_device = spl_boot_device();\n> \n> \tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\n> \t\tstruct mmc *mmc = NULL;\n> \t\tint err = 0;\n> \n> \t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\n> \n> \t\terr = mmc_init(mmc);\n> \n> \t\tif (err) {\n> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\n> \t\t\tprintf(\"spl: mmc init failed with error: %d\\n\",\n> err);\n> #endif\n> \t\t}\n> \n> \t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-\n>> fdt_blob,\n> \t\t\t\t\t\t\t\t &len);\n> \n> \t\tfpga_fsinfo.filename = (char *)get_cff_filename(gd-\n>> fdt_blob,\n> \t\t\t\t\t\t\t\t &len,\n> \t\t\t\t\t\t\t\tPERIPH_\n> RBF);\n> \n> \t\tfpga_fsinfo.interface = \"mmc\";\n> \n> \t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\n> \t} else {\n> \t\tprintf(\"Invalid boot device!\\n\");\n> \t\treturn;\n> \t}\n> \n> \t/* Program peripheral RBF */\n> \tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))\n> \t\trval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);\n> \n> In /common/splash.c, dev_Part and flash type everything are hard coded\n> in struct splash_location. In my spl.c, flash type are determined on\n> run time and dev_part are retrived from DTS, and then assigned to\n> struct fpga_fsinfo. Please note that this is in SPL, mmc need to be\n> initialized 1st before loading raw file into memory. In SPL, raw file\n> are coppied to OCRAM chunk by chunk, but In u-boot it would normally\n> done in one big chunk to DRAM. This would be handled by fpga loadfs.\n> \n> So, you want me hard code everthing like in splash.c?\n\nNo, I need you to play around with this and come up with generic\nfirmware loader that's flexible enough.\n\n> 2nd function -->\n> In /common/splash_source.c\n> static int splash_select_fs_dev(struct splash_location *location)\n> {\n> \tint res;\n> \n> \tswitch (location->storage) {\n> \tcase SPLASH_STORAGE_MMC:\n> \t\tres = fs_set_blk_dev(\"mmc\", location->devpart,\n> FS_TYPE_ANY);\n> \t\tbreak;\n> \tcase SPLASH_STORAGE_USB:\n> \t\tres = fs_set_blk_dev(\"usb\", location->devpart,\n> FS_TYPE_ANY);\n> \t\tbreak;\n> \tcase SPLASH_STORAGE_SATA:\n> \t\tres = fs_set_blk_dev(\"sata\", location->devpart,\n> FS_TYPE_ANY);\n> \t\tbreak;\n> \tcase SPLASH_STORAGE_NAND:\n> \t\tif (location->ubivol != NULL)\n> \t\t\tres = fs_set_blk_dev(\"ubi\", NULL,\n> FS_TYPE_UBIFS);\n> \t\telse\n> \t\t\tres = -ENODEV;\n> \t\tbreak;\n> \tdefault:\n> \t\tprintf(\"Error: unsupported location storage.\\n\");\n> \t\treturn -ENODEV;\n> \t}\n> \n> \tif (res)\n> \t\tprintf(\"Error: could not access storage.\\n\");\n> \n> \treturn res;\n> }\n> \n> In my /drivers/fpga/socfpga_arria10.c\n> static int flash_read(struct flash_info *flashinfo,\n> \tu32 size_read,\n> \tu32 *buffer_ptr)\n> {\n> \tsize_t ret = EEXIST;\n> \tloff_t actread = 0;\n> \n> \tif (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,\n> \t\t\t\tflashinfo->fstype))\n> \t\treturn FPGA_FAIL;\n> \n> \tret = fs_read(flashinfo->filename,\n> \t\t\t(u32) buffer_ptr, flashinfo->flash_offset,\n> \t\t\tsize_read, &actread);\n> \n> \tif (ret || actread != size_read) {\n> \t\tprintf(\"Failed to read %s from flash %d \",\n> \t\t\tflashinfo->filename,\n> \t\t\t ret);\n> \t\tprintf(\"!= %d.\\n\", size_read);\n> \t\treturn -EPERM;\n> \t\t} else\n> \t\t\tret = actread;\n> \n> \treturn ret;\n> }\n> \n> Some attributes like flash type is determined on run time and and\n> dev_part is retrieved from DTS, so every infos driver need to know are\n> assinged into struct flashinfo and passed to fs_set_blk_dev as\n> arguments. I found that function in splash_source.c some like flash\n> type are getting from env variable, but we are still in SPL phase,\n> those env variable is not set up yet. So, i think that is very\n> ineffcient to factor out them as common.\n> \n> If you want me create a generic firmware loader which is generic enough\n> loading content for all components like flashes, FPGA, splash ....etc,\n> i don't think that is effient enough, as fpga loadfs has different\n> handling in both SPL and U-boot like copying raw into memory.\n\nDuplicating code is nonsense and I believe generic firmware loader would\nbe the way to go here.\n\n> It would be good you can direct point me out which functions have\n> similirity and how to factor them out as common.\n> \n> Thanks a lot.\n>>>\n>>> Thanks.\n>>>>\n>>>> [...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2yyW12BDz9tX5\n\tfor ;\n\tFri, 29 Sep 2017 01:18:59 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E0E5BC21DA9; Thu, 28 Sep 2017 15:18:55 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C7A5BC21CB3;\n\tThu, 28 Sep 2017 15:18:51 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 32420C21CB3; Thu, 28 Sep 2017 15:18:50 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id D84FEC21CB1\n\tfor ; Thu, 28 Sep 2017 15:18:49 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y2yyJ68HLz1qs0B;\n\tThu, 28 Sep 2017 17:18:48 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y2yyJ5C6tz1r0xj;\n\tThu, 28 Sep 2017 17:18:48 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id Gn8LjdXG4VAT; Thu, 28 Sep 2017 17:18:41 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tThu, 28 Sep 2017 17:18:41 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"vaWI6D30qD9YpD1GAGG7pmuebQPMt0gGEPLVdV8dhHI=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>\n\t<995ab037-992e-5782-4faf-8965d039c841@denx.de>\n\t<1506419533.2109.2.camel@intel.com>\n\t<79d6500b-646a-a6a3-c211-3b04b57866f9@denx.de>\n\t<1506503592.3589.37.camel@intel.com>\n\t\n\t<1506611647.3589.70.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<6245ed89-5b34-40b2-9065-a586b07d2ee4@denx.de>","Date":"Thu, 28 Sep 2017 17:18:40 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506611647.3589.70.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" ,\n\tMichal Simek ,\n\t\"skywindctf@gmail.com\" , \"Westergreen,\n\tDalon\" ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1782467,"web_url":"http://patchwork.ozlabs.org/comment/1782467/","msgid":"","list_archive_url":null,"date":"2017-10-09T04:47:08","subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi,\n\nOn 25 September 2017 at 02:40, wrote:\n> From: Tien Fong Chee \n>\n> These drivers handle FPGA program operation from flash loading\n> RBF to memory and then to program FPGA.\n>\n> Signed-off-by: Tien Fong Chee \n> ---\n> .../include/mach/fpga_manager_arria10.h | 27 ++\n> drivers/fpga/socfpga_arria10.c | 391 ++++++++++++++++++++-\n> include/altera.h | 6 +\n> include/configs/socfpga_common.h | 4 +\n> 4 files changed, 425 insertions(+), 3 deletions(-)\n\nAgreed on the generic loader, but also, can you please use driver\nmodel? Am I missing something?\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"iD4Ydii0\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=chromium.org header.i=@chromium.org\n\theader.b=\"jYKns6wI\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9Svx0wbbz9tY5\n\tfor ;\n\tMon, 9 Oct 2017 16:09:17 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid D39E5C21D74; Mon, 9 Oct 2017 04:52:22 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 97419C21D55;\n\tMon, 9 Oct 2017 04:52:05 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 1E301C21D19; Mon, 9 Oct 2017 04:47:33 +0000 (UTC)","from mail-qt0-f176.google.com (mail-qt0-f176.google.com\n\t[209.85.216.176])\n\tby lists.denx.de (Postfix) with ESMTPS id 567F7C21DDA\n\tfor ; Mon, 9 Oct 2017 04:47:30 +0000 (UTC)","by mail-qt0-f176.google.com with SMTP id 1so807820qtn.3\n\tfor ; Sun, 08 Oct 2017 21:47:30 -0700 (PDT)","by 10.200.63.170 with HTTP; Sun, 8 Oct 2017 21:47:08 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;\n\ts=20161025; \n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=ZeLDGgE8kz3b1xXAv/UgBGFyv0WyCBToqqO5y4yePmU=;\n\tb=iD4Ydii0q8LDzkTZl2ajm3DZ7CfU814ZDxHWGOLTrOpDapzS8HOqcnmUaV6Zi+rggw\n\tTmvuErl8QOrok7nB3JQaC/ULbWAmEQuPzETEhUPpss3y0rwczrpsVDA+aHBYAs2E6dlV\n\tzjnwYYOQOS233/j2MR3WCO0scrd+CXm8SebEbGlWCDGFLBYQDKfGjgWEadjKoXC634xw\n\tv+SvUVply3LC5L9epZxGN7+uo0bY/yoc1HmhsJJd1IeZicukgfKob25gubYgvXoa/NOu\n\t+a3o3nr8BhehS29eEM2B7kmLYM3eJPyfhfTz92wh7qm9Mz2yDpYUeEiknZSXiXzq1Gsi\n\tFRfw==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org;\n\ts=google; \n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=ZeLDGgE8kz3b1xXAv/UgBGFyv0WyCBToqqO5y4yePmU=;\n\tb=jYKns6wIdYW0mgprs5v2ENtnubOOwS7agqtlUS6I1A9+b0ZhoFGBtcM1N3xo0SZFAe\n\tA6kU4bdDcsZt3i0lWAEYFdFpCS3L8T0dVCHmj4hiip7iGTFf8Hj1+NY1CTs9KxOT7dPU\n\tyB7Wd6NVBbaPUO7klSGdUNF+RtcY7iZxjpd2k="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:sender:in-reply-to:references:from\n\t:date:message-id:subject:to:cc;\n\tbh=ZeLDGgE8kz3b1xXAv/UgBGFyv0WyCBToqqO5y4yePmU=;\n\tb=KGzROJFQpxRCZYpTTDB2BLlgfzQijiVTJhBLoWlOscqWaVGddj8J7nXn3qWTXoQu39\n\tBSOXIxWdWEOxJvBL5H5vZ1e3ZTuWdZBKzvrdLNioIRTwwhgw/Z6cQTfLF2OeOhxyOZEO\n\tOT2iOjXce4wdKWW4Ss8z0wzb1hCIeb4Imy0R30aCcOU2ozq6PsZu/H4M0A5QeQOHZHBN\n\t8H++0mNpJSlSdprFuzFzzptyYgEUekG6iMseTaK9/Ks+sAZxuKpPO2Wn1bXQ+RXO+mZX\n\twQty14X5+bWlUMcScM9ILtn8v2QI808QZ92d0/339yGGcyynTOG3gmU+tHrilO1vl/Dl\n\t+t8A==","X-Gm-Message-State":"AMCzsaW1Yh8aGmBeMFaeFlnOCZhgQO9+xbebdjnFNtv6sn0bkO7Ufr3X\n\tihpoVJ05Nqi6sb5pthgeNSjqRdn9iQjpuYfK+QKzBTP4","X-Google-Smtp-Source":"AOwi7QD1FjHghlmYOQa2KggtVqYpeilc6SyCJkJ8PAOpPc1oWjzUkIts9QKVAMRGFBIHrImj72C+wEkN96eZZB2B/AY=","X-Received":"by 10.237.33.33 with SMTP id 30mr11892718qtc.138.1507524449108; \n\tSun, 08 Oct 2017 21:47:29 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","From":"Simon Glass ","Date":"Sun, 8 Oct 2017 22:47:08 -0600","X-Google-Sender-Auth":"_8n1tsz_6biEMVrZZl6mY0FKmWo","Message-ID":"","To":"Tien Fong Chee ","Cc":"Marek Vasut , U-Boot Mailing List , \n\tChing Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for\n\tprograming FPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]