[{"id":1774618,"web_url":"http://patchwork.ozlabs.org/comment/1774618/","msgid":"","list_archive_url":null,"date":"2017-09-25T09:23:29","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Clock frequency info is required in U-boot.\n> \n> Signed-off-by: Tien Fong Chee \n\nI want a TB on Gen 5\n\n> ---\n> arch/arm/mach-socfpga/board.c | 6 ++++++\n> 1 file changed, 6 insertions(+)\n> \n> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c\n> index 965f9dc..a00f63b 100644\n> --- a/arch/arm/mach-socfpga/board.c\n> +++ b/arch/arm/mach-socfpga/board.c\n> @@ -8,7 +8,10 @@\n> \n> #include \n> #include \n> +#include \n> #include \n> +#include \n> +#include \n> #include \n> \n> #include \n> @@ -26,6 +29,9 @@ int board_init(void)\n> \t/* Address of boot parameters for ATAG (if ATAG is used) */\n> \tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\n> \n> +\t/* configuring the clock based on handoff */\n> +\tcm_basic_init(gd->fdt_blob);\n> +\n> \treturn 0;\n> }\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 12:00:23 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 12:00:23 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"CTJlNdP25Jd6clGmImQexQX7KW4ybMnAAJvtFbVxaRY=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Mon, 25 Sep 2017 11:23:29 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775146,"web_url":"http://patchwork.ozlabs.org/comment/1775146/","msgid":"<1506400339.27760.4.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T04:32:19","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Clock frequency info is required in U-boot.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> I want a TB on Gen 5\r\n> \r\nWhat is TB?\r\n> > \r\n> > ---\r\n> >  arch/arm/mach-socfpga/board.c | 6 ++++++\r\n> >  1 file changed, 6 insertions(+)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > socfpga/board.c\r\n> > index 965f9dc..a00f63b 100644\r\n> > --- a/arch/arm/mach-socfpga/board.c\r\n> > +++ b/arch/arm/mach-socfpga/board.c\r\n> > @@ -8,7 +8,10 @@\r\n> >  \r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> >  #include \r\n> > +#include \r\n> > +#include \r\n> >  #include \r\n> >  \r\n> >  #include \r\n> > @@ -26,6 +29,9 @@ int board_init(void)\r\n> >  \t/* Address of boot parameters for ATAG (if ATAG is used)\r\n> > */\r\n> >  \tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\r\n> >  \r\n> > +\t/* configuring the clock based on handoff */\r\n> > +\tcm_basic_init(gd->fdt_blob);\r\n> > +\r\n> >  \treturn 0;\r\n> >  }\r\n> >  \r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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25 Sep 2017 21:32:21 -0700","from pgsmsx110.gar.corp.intel.com (10.221.44.111) by\n\tPGSMSX108.gar.corp.intel.com (10.221.44.103) with Microsoft SMTP\n\tServer (TLS) id 14.3.319.2; Tue, 26 Sep 2017 12:32:20 +0800","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX110.gar.corp.intel.com ([169.254.13.249]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 12:32:20 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,439,1500966000\"; d=\"scan'208\";a=\"153325041\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 17/19] arm: socfpga: Adding clock frequency info for\n\tU-boot","Thread-Index":"AQHTNdoOIwB5PwMtVESDdJVKjtW4LqLEzhWAgAFA+4A=","Date":"Tue, 26 Sep 2017 04:32:19 +0000","Message-ID":"<1506400339.27760.4.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776007,"web_url":"http://patchwork.ozlabs.org/comment/1776007/","msgid":"<1506482659.3589.7.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T03:24:20","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Clock frequency info is required in U-boot.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> I want a TB on Gen 5\r\n> \r\nOkay.\r\n> > \r\n> > ---\r\n> >  arch/arm/mach-socfpga/board.c | 6 ++++++\r\n> >  1 file changed, 6 insertions(+)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > socfpga/board.c\r\n> > index 965f9dc..a00f63b 100644\r\n> > --- a/arch/arm/mach-socfpga/board.c\r\n> > +++ b/arch/arm/mach-socfpga/board.c\r\n> > @@ -8,7 +8,10 @@\r\n> >  \r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> >  #include \r\n> > +#include \r\n> > +#include \r\n> >  #include \r\n> >  \r\n> >  #include \r\n> > @@ -26,6 +29,9 @@ int board_init(void)\r\n> >  \t/* Address of boot parameters for ATAG (if ATAG is used)\r\n> > */\r\n> >  \tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\r\n> >  \r\n> > +\t/* configuring the clock based on handoff */\r\n> > +\tcm_basic_init(gd->fdt_blob);\r\n> > +\r\n> >  \treturn 0;\r\n> >  }\r\n> >  \r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y238l5tRcz9t3m\n\tfor ;\n\tWed, 27 Sep 2017 13:24:38 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 5482CC21C4E; Wed, 27 Sep 2017 03:24:29 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 06066C21C45;\n\tWed, 27 Sep 2017 03:24:27 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid C33B5C21C45; Wed, 27 Sep 2017 03:24:25 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id E97EAC21C40\n\tfor ; Wed, 27 Sep 2017 03:24:24 +0000 (UTC)","from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 20:24:23 -0700","from kmsmsx153.gar.corp.intel.com ([172.21.73.88])\n\tby fmsmga006.fm.intel.com with ESMTP; 26 Sep 2017 20:24:22 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX153.gar.corp.intel.com ([169.254.5.166]) with mapi id\n\t14.03.0319.002; Wed, 27 Sep 2017 11:24:21 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,442,1500966000\"; d=\"scan'208\";a=\"156455946\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 17/19] arm: socfpga: Adding clock frequency info for\n\tU-boot","Thread-Index":"AQHTNdoOIwB5PwMtVESDdJVKjtW4LqLEzhWAgALAUIA=","Date":"Wed, 27 Sep 2017 03:24:20 +0000","Message-ID":"<1506482659.3589.7.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<58A8FA4259D6D743AF0BF88658458181@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778231,"web_url":"http://patchwork.ozlabs.org/comment/1778231/","msgid":"<1506938668.2178.3.camel@intel.com>","list_archive_url":null,"date":"2017-10-02T10:04:32","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Clock frequency info is required in U-boot.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> I want a TB on Gen 5\r\n> \r\nThis patch break the gen5, because cm_basic_init is exclusive for Arria\r\n10. #ifdef is required.\r\n> > \r\n> > ---\r\n> >  arch/arm/mach-socfpga/board.c | 6 ++++++\r\n> >  1 file changed, 6 insertions(+)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > socfpga/board.c\r\n> > index 965f9dc..a00f63b 100644\r\n> > --- a/arch/arm/mach-socfpga/board.c\r\n> > +++ b/arch/arm/mach-socfpga/board.c\r\n> > @@ -8,7 +8,10 @@\r\n> >  \r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> >  #include \r\n> > +#include \r\n> > +#include \r\n> >  #include \r\n> >  \r\n> >  #include \r\n> > @@ -26,6 +29,9 @@ int board_init(void)\r\n> >  \t/* Address of boot parameters for ATAG (if ATAG is used)\r\n> > */\r\n> >  \tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\r\n> >  \r\n> > +\t/* configuring the clock based on handoff */\r\n> > +\tcm_basic_init(gd->fdt_blob);\r\n> > +\r\n> >  \treturn 0;\r\n> >  }\r\n> >  \r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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02 Oct 2017 03:04:34 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX154.gar.corp.intel.com ([169.254.12.132]) with mapi id\n\t14.03.0319.002; Mon, 2 Oct 2017 18:04:33 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,468,1500966000\"; d=\"scan'208\";a=\"141672770\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 17/19] arm: socfpga: Adding clock frequency info for\n\tU-boot","Thread-Index":"AQHTNdoOIwB5PwMtVESDdJVKjtW4LqLEzhWAgAsLxQA=","Date":"Mon, 2 Oct 2017 10:04:32 +0000","Message-ID":"<1506938668.2178.3.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.168]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778236,"web_url":"http://patchwork.ozlabs.org/comment/1778236/","msgid":"<0f36b514-8e8d-c0db-649f-a1ae4cea18eb@denx.de>","list_archive_url":null,"date":"2017-10-02T10:10:15","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 10/02/2017 12:04 PM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Clock frequency info is required in U-boot.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>> I want a TB on Gen 5\n>>\n> This patch break the gen5, because cm_basic_init is exclusive for Arria\n> 10. #ifdef is required.\n\nCan you at least build-test your patches before submitting ?\nHeck, you can also set up the travisci [1] to do all that stuff for you.\n\n[1] https://travis-ci.org/marex/u-boot-socfpga/branches","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5Hwh5xsWz9t4X\n\tfor ;\n\tMon, 2 Oct 2017 21:10:28 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 6DD7AC21E6C; Mon, 2 Oct 2017 10:10:21 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 582E1C21C41;\n\tMon, 2 Oct 2017 10:10:19 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 45D22C21C41; Mon, 2 Oct 2017 10:10:18 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id EDEE0C21C29\n\tfor ; Mon, 2 Oct 2017 10:10:17 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y5HwT503Sz1qqyT;\n\tMon, 2 Oct 2017 12:10:17 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y5HwT443mz1qql6;\n\tMon, 2 Oct 2017 12:10:17 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id XI7MFOFIdIno; Mon, 2 Oct 2017 12:10:15 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 2 Oct 2017 12:10:15 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"kuh7eL97lSqBp741oA/b71otgkC6H0Elf64rMWmzYng=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506938668.2178.3.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<0f36b514-8e8d-c0db-649f-a1ae4cea18eb@denx.de>","Date":"Mon, 2 Oct 2017 12:10:15 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506938668.2178.3.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778243,"web_url":"http://patchwork.ozlabs.org/comment/1778243/","msgid":"<1506939945.2178.5.camel@intel.com>","list_archive_url":null,"date":"2017-10-02T10:25:45","subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-10-02 at 12:10 +0200, Marek Vasut wrote:\r\n> On 10/02/2017 12:04 PM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Clock frequency info is required in U-boot.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > I want a TB on Gen 5\r\n> > > \r\n> > This patch break the gen5, because cm_basic_init is exclusive for\r\n> > Arria\r\n> > 10. #ifdef is required.\r\n> Can you at least build-test your patches before submitting ?\r\n> Heck, you can also set up the travisci [1] to do all that stuff for\r\n> you.\r\n> \r\n> [1] https://travis-ci.org/marex/u-boot-socfpga/branches\r\n> \r\nOkay.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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02 Oct 2017 03:25:47 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX107.gar.corp.intel.com ([169.254.7.200]) with mapi id\n\t14.03.0319.002; Mon, 2 Oct 2017 18:25:45 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,469,1500966000\"; d=\"scan'208\";\n\ta=\"1201203720\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 17/19] arm: socfpga: Adding clock frequency info for\n\tU-boot","Thread-Index":"AQHTNdoOIwB5PwMtVESDdJVKjtW4LqLEzhWAgAsLxQCAAAGdgIAABFWA","Date":"Mon, 2 Oct 2017 10:25:45 +0000","Message-ID":"<1506939945.2178.5.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506938668.2178.3.camel@intel.com>\n\t<0f36b514-8e8d-c0db-649f-a1ae4cea18eb@denx.de>","In-Reply-To":"<0f36b514-8e8d-c0db-649f-a1ae4cea18eb@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.168]","Content-ID":"<10ED8124948EED4EA9D3D26022DBA2A1@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency\n\tinfo for U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; 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