[{"id":1774606,"web_url":"http://patchwork.ozlabs.org/comment/1774606/","msgid":"<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>","list_archive_url":null,"date":"2017-09-25T09:19:58","subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Add DDR driver suppport for Arria 10.\n> \n> Signed-off-by: Tien Fong Chee \n> ---\n> arch/arm/mach-socfpga/include/mach/sdram.h | 2 +\n> arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-\n> drivers/ddr/altera/sdram_arria10.c | 735 +++++++++++++++++++++\n> 3 files changed, 839 insertions(+), 1 deletion(-)\n> create mode 100644 drivers/ddr/altera/sdram_arria10.c\n> \n> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h\n> index 4a9754e..b833fc2 100644\n> --- a/arch/arm/mach-socfpga/include/mach/sdram.h\n> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h\n> @@ -10,6 +10,8 @@\n> \n> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> #include \n> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +#include \n> #endif\n> \n> #endif\n> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n> index 1d7b7c1..7af9431 100644\n> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n> @@ -1,5 +1,5 @@\n> /*\n> - * Copyright (C) 2015-2017 Intel Corporation \n> + * Copyright (C) 2017 Intel Corporation \n> *\n> * SPDX-License-Identifier:\tGPL-2.0\n> */\n> @@ -8,6 +8,7 @@\n> #define _SOCFPGA_SDRAM_ARRIA10_H_\n> \n> #ifndef __ASSEMBLY__\n> +int ddr_calibration_sequence(void);\n> \n> struct socfpga_ecc_hmc {\n> \tu32 ip_rev_id;\n> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {\n> \tu32 niosreserve1;\n> \tu32 niosreserve2;\n> };\n> +\n> +union dramaddrw_reg {\n> +\tstruct {\n> +\t\tu32 cfg_col_addr_width:5;\n> +\t\tu32 cfg_row_addr_width:5;\n> +\t\tu32 cfg_bank_addr_width:4;\n> +\t\tu32 cfg_bank_group_addr_width:2;\n> +\t\tu32 cfg_cs_addr_width:3;\n> +\t\tu32 reserved:13;\n> +\t};\n\nUse regular macros for bitfields, not this crap.\n\n> +\tu32 word;\n> +};\n> +\n> +union ctrlcfg0_reg {\n> +\tstruct {\n> +\t\tu32 cfg_mem_type:4;\n> +\t\tu32 cfg_dimm_type:3;\n> +\t\tu32 cfg_ac_pos:2;\n> +\t\tu32 cfg_ctrl_burst_len:5;\n> +\t\tu32 reserved:18; /* Other fields unused */\n> +\t};\n> +\tu32 word;\n> +};\n\n[...]\n\n> diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c\n> new file mode 100644\n> index 0000000..f22a726\n> --- /dev/null\n> +++ b/drivers/ddr/altera/sdram_arria10.c\n> @@ -0,0 +1,735 @@\n> +/*\n> + * Copyright (C) 2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n\nWhy does an SDRAM init driver need access to ns16550 UART , MMC and NAND ?\n\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +DECLARE_GLOBAL_DATA_PTR;\n> +\n> +static void sdram_mmr_init(void);\n> +static unsigned long long sdram_size_calc(void);\n> +\n> +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */\n> +#define ARRIA10_SDR_ACTIVATE_FAWBANK\t(0x1)\n> +\n> +#define ARRIA_DDR_CONFIG(A, B, C, R)\t((A<<24)|(B<<16)|(C<<8)|R)\n\nMissing parenthesis around (A), (B) etc. ...\n\n> +#define DDR_CONFIG_ELEMENTS\t(sizeof(ddr_config)/sizeof(u32))\n\nSo this is ARRAY_SIZE() ?\n\n> +#define DDR_REG_SEQ2CORE 0xFFD0507C\n> +#define DDR_REG_CORE2SEQ 0xFFD05078\n> +#define DDR_READ_LATENCY_DELAY\t40\n> +#define DDR_SIZE_2GB_HEX\t0x80000000\n> +#define DDR_MAX_TRIES\t\t0x00100000\n> +\n> +#define IO48_MMR_DRAMSTS\t0xFFCFA0EC\n> +#define IO48_MMR_NIOS2_RESERVE0\t0xFFCFA110\n> +#define IO48_MMR_NIOS2_RESERVE1\t0xFFCFA114\n> +#define IO48_MMR_NIOS2_RESERVE2\t0xFFCFA118\n> +\n> +#define SEQ2CORE_MASK\t\t0xF\n> +#define CORE2SEQ_INT_REQ\t0xF\n> +#define SEQ2CORE_INT_RESP_BIT\t3\n> +\n> +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =\n> +\t\t(void *)SOCFPGA_SDR_ADDRESS;\n> +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =\n> +\t\t(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;\n> +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram\n> +\t\t*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =\n> +\t\t(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;\n> +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =\n> +\t\t(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;\n> +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =\n> +\t\t(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;\n> +\n> +/* The followring are the supported configurations */\n> +static u32 ddr_config[] = {\n> +\t/* Chip - Row - Bank - Column Style */\n> +\t/* All Types */\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 12),\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 13),\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 14),\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 15),\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 16),\n> +\tARRIA_DDR_CONFIG(0, 3, 10, 17),\n> +\t/* LPDDR x16 */\n> +\tARRIA_DDR_CONFIG(0, 3, 11, 14),\n> +\tARRIA_DDR_CONFIG(0, 3, 11, 15),\n> +\tARRIA_DDR_CONFIG(0, 3, 11, 16),\n> +\tARRIA_DDR_CONFIG(0, 3, 12, 15),\n> +\t/* DDR4 Only */\n> +\tARRIA_DDR_CONFIG(0, 4, 10, 14),\n> +\tARRIA_DDR_CONFIG(0, 4, 10, 15),\n> +\tARRIA_DDR_CONFIG(0, 4, 10, 16),\n> +\tARRIA_DDR_CONFIG(0, 4, 10, 17),\t/* 14 */\n> +\t/* Chip - Bank - Row - Column Style */\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 12),\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 13),\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 14),\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 15),\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 16),\n> +\tARRIA_DDR_CONFIG(1, 3, 10, 17),\n> +\tARRIA_DDR_CONFIG(1, 3, 11, 14),\n> +\tARRIA_DDR_CONFIG(1, 3, 11, 15),\n> +\tARRIA_DDR_CONFIG(1, 3, 11, 16),\n> +\tARRIA_DDR_CONFIG(1, 3, 12, 15),\n> +\t/* DDR4 Only */\n> +\tARRIA_DDR_CONFIG(1, 4, 10, 14),\n> +\tARRIA_DDR_CONFIG(1, 4, 10, 15),\n> +\tARRIA_DDR_CONFIG(1, 4, 10, 16),\n> +\tARRIA_DDR_CONFIG(1, 4, 10, 17),\n> +};\n> +\n> +static int match_ddr_conf(u32 ddr_conf)\n> +{\n> +\tint i;\n> +\n> +\tfor (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {\n> +\t\tif (ddr_conf == ddr_config[i])\n> +\t\t\treturn i;\n> +\t}\n> +\treturn 0;\n> +}\n> +\n> +/* Check whether SDRAM is successfully Calibrated */\n> +static int is_sdram_cal_success(void)\n> +{\n> +\treturn readl(&socfpga_ecc_hmc_base->ddrcalstat);\n> +}\n> +\n> +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)\n> +{\n> +\tu32 reg = readl(ereg);\n> +\n> +\treturn (reg & (1 << bit)) ? 1 : 0;\n\nUrgh, BIT() and just use it inline and drop this\n\n> +}\n> +\n> +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,\n> +\t\t\t u32 expected, u32 timeout_usec)\n> +{\n> +\tu32 tmr;\n> +\n> +\tfor (tmr = 0; tmr < timeout_usec; tmr += 100) {\n> +\t\tudelay(100);\n> +\t\tWATCHDOG_RESET();\n> +\t\tif (ddr_get_bit(ereg, bit) == expected)\n> +\t\t\treturn 0;\n> +\t}\n> +\n> +\treturn 1;\n> +}\n> +\n> +static void ddr_delay(u32 delay)\n> +{\n> +\tint tmr;\n> +\n> +\tfor (tmr = 0; tmr < delay; tmr++) {\n> +\t\tudelay(1000);\n> +\t\tWATCHDOG_RESET();\n\nSo this is mdelay(delay) ?\n\n> +\t}\n> +}\n> +\n> +static int emif_clear(void)\n> +{\n> +\tu32 s2c;\n> +\tu32 i = DDR_MAX_TRIES;\n> +\n> +\twritel(0, DDR_REG_CORE2SEQ);\n> +\tdo {\n> +\t\tddr_delay(50);\n> +\t\ts2c = readl(DDR_REG_SEQ2CORE);\n> +\t} while ((s2c & SEQ2CORE_MASK) && (--i > 0));\n\nwait_for_bit() or something ?\n\n> +\treturn !i;\n> +}\n> +\n> +static int emif_reset(void)\n> +{\n> +\tu32 c2s, s2c;\n> +\n> +\tc2s = readl(DDR_REG_CORE2SEQ);\n> +\ts2c = readl(DDR_REG_SEQ2CORE);\n> +\n> +\tdebug(\"c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\\n\",\n> +\t\tc2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),\n> +\t\treadl(IO48_MMR_NIOS2_RESERVE1),\n> +\t\treadl(IO48_MMR_NIOS2_RESERVE2),\n> +\t\treadl(IO48_MMR_DRAMSTS));\n> +\n> +\tif ((s2c & SEQ2CORE_MASK) && emif_clear()) {\n> +\t\tprintf(\"failed emif_clear()\\n\");\n> +\t\treturn -1;\n> +\t}\n> +\n> +\twritel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);\n> +\n> +\tif (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {\n> +\t\tprintf(\"emif_reset failed to see interrupt acknowledge\\n\");\n> +\t\treturn -2;\n\nUse proper errno.h codes\n\n> +\t} else {\n> +\t\tprintf(\"emif_reset interrupt acknowledged\\n\");\n> +\t}\n> +\n> +\tif (emif_clear()) {\n> +\t\tprintf(\"emif_clear() failed\\n\");\n> +\t\treturn -3;\n> +\t}\n> +\tdebug(\"emif_reset interrupt cleared\\n\");\n> +\n> +\tdebug(\"nr0=%08x nr1=%08x nr2=%08x\\n\",\n> +\t\treadl(IO48_MMR_NIOS2_RESERVE0),\n> +\t\treadl(IO48_MMR_NIOS2_RESERVE1),\n> +\t\treadl(IO48_MMR_NIOS2_RESERVE2));\n> +\n> +\treturn 0;\n> +}\n[...]\n\n> +struct firewall_entry {\n> +\tconst char *prop_name;\n> +\tconst u32 cfg_addr;\n> +\tconst u32 en_addr;\n> +\tconst u32 en_bit;\n> +};\n> +#define FW_MPU_FPGA_ADDRESS \\\n> +\t((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\\\n> +\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)\n> +const struct firewall_entry firewall_table[] = {\n> +\t{\n\nThis seems to be mostly copy-paste of the same stuff ... fix with macro.\n\n> +\t\t\"altr,mpu0\",\n> +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n> +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n> +\t\t\t mpuregion0addr),\n> +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n> +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n> +\t\t\t enable),\n> +\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK\n> +\t},\n> +\t{\n> +\t\t\"altr,mpu1\",\n> +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n> +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n> +\t\t\t mpuregion1addr),\n> +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n> +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n> +\t\t\t enable),\n> +\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK\n> +\t},\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:35 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:35 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"EI/ewoMjekHjtdMbKvU7LG7ZQYxMIEXQ/pS52z/EiCE=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>","Date":"Mon, 25 Sep 2017 11:19:58 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775242,"web_url":"http://patchwork.ozlabs.org/comment/1775242/","msgid":"<1506414031.27760.20.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T08:20:32","subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Add DDR driver suppport for Arria 10.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> > ---\r\n> >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +\r\n> >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-\r\n> >  drivers/ddr/altera/sdram_arria10.c                 | 735\r\n> > +++++++++++++++++++++\r\n> >  3 files changed, 839 insertions(+), 1 deletion(-)\r\n> >  create mode 100644 drivers/ddr/altera/sdram_arria10.c\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > b/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > index 4a9754e..b833fc2 100644\r\n> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > @@ -10,6 +10,8 @@\r\n> >  \r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >  #include \r\n> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#include \r\n> >  #endif\r\n> >  \r\n> >  #endif\r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > index 1d7b7c1..7af9431 100644\r\n> > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > @@ -1,5 +1,5 @@\r\n> >  /*\r\n> > - * Copyright (C) 2015-2017 Intel Corporation \r\n> > + * Copyright (C) 2017 Intel Corporation \r\n> >   *\r\n> >   * SPDX-License-Identifier:\tGPL-2.0\r\n> >   */\r\n> > @@ -8,6 +8,7 @@\r\n> >  #define _SOCFPGA_SDRAM_ARRIA10_H_\r\n> >  \r\n> >  #ifndef __ASSEMBLY__\r\n> > +int ddr_calibration_sequence(void);\r\n> >  \r\n> >  struct socfpga_ecc_hmc {\r\n> >  \tu32 ip_rev_id;\r\n> > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {\r\n> >  \tu32 niosreserve1;\r\n> >  \tu32 niosreserve2;\r\n> >  };\r\n> > +\r\n> > +union dramaddrw_reg {\r\n> > +\tstruct {\r\n> > +\t\tu32 cfg_col_addr_width:5;\r\n> > +\t\tu32 cfg_row_addr_width:5;\r\n> > +\t\tu32 cfg_bank_addr_width:4;\r\n> > +\t\tu32 cfg_bank_group_addr_width:2;\r\n> > +\t\tu32 cfg_cs_addr_width:3;\r\n> > +\t\tu32 reserved:13;\r\n> > +\t};\r\n> Use regular macros for bitfields, not this crap.\r\n> \r\nWhy regular macros is prefered? Above implementation improve\r\nreadability, simplify the implementation and saving memory.\r\n> > \r\n> > +\tu32 word;\r\n> > +};\r\n> > +\r\n> > +union ctrlcfg0_reg {\r\n> > +\tstruct {\r\n> > +\t\tu32 cfg_mem_type:4;\r\n> > +\t\tu32 cfg_dimm_type:3;\r\n> > +\t\tu32 cfg_ac_pos:2;\r\n> > +\t\tu32 cfg_ctrl_burst_len:5;\r\n> > +\t\tu32 reserved:18;  /* Other fields unused */\r\n> > +\t};\r\n> > +\tu32 word;\r\n> > +};\r\n> [...]\r\n> \r\n> > \r\n> > diff --git a/drivers/ddr/altera/sdram_arria10.c\r\n> > b/drivers/ddr/altera/sdram_arria10.c\r\n> > new file mode 100644\r\n> > index 0000000..f22a726\r\n> > --- /dev/null\r\n> > +++ b/drivers/ddr/altera/sdram_arria10.c\r\n> > @@ -0,0 +1,735 @@\r\n> > +/*\r\n> > + * Copyright (C) 2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> Why does an SDRAM init driver need access to ns16550 UART , MMC and\r\n> NAND ?\r\n> \r\nI will remove them.\r\n> > \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +\r\n> > +DECLARE_GLOBAL_DATA_PTR;\r\n> > +\r\n> > +static void sdram_mmr_init(void);\r\n> > +static unsigned long long sdram_size_calc(void);\r\n> > +\r\n> > +/* FAWBANK - Number of Bank of a given device involved in the FAW\r\n> > period. */\r\n> > +#define ARRIA10_SDR_ACTIVATE_FAWBANK\t(0x1)\r\n> > +\r\n> > +#define ARRIA_DDR_CONFIG(A, B, C, R)\t((A<<24)|(B<<16)|(C<<8\r\n> > )|R)\r\n> Missing parenthesis around (A), (B) etc. ...\r\n> \r\nOkay.\r\n> > \r\n> > +#define DDR_CONFIG_ELEMENTS\t(sizeof(ddr_config)/sizeof(u32)\r\n> > )\r\n> So this is ARRAY_SIZE() ?\r\n> \r\nYes. i will use ARRAY_SIZE().\r\n> > \r\n> > +#define DDR_REG_SEQ2CORE        0xFFD0507C\r\n> > +#define DDR_REG_CORE2SEQ        0xFFD05078\r\n> > +#define DDR_READ_LATENCY_DELAY\t40\r\n> > +#define DDR_SIZE_2GB_HEX\t0x80000000\r\n> > +#define DDR_MAX_TRIES\t\t0x00100000\r\n> > +\r\n> > +#define IO48_MMR_DRAMSTS\t0xFFCFA0EC\r\n> > +#define IO48_MMR_NIOS2_RESERVE0\t0xFFCFA110\r\n> > +#define IO48_MMR_NIOS2_RESERVE1\t0xFFCFA114\r\n> > +#define IO48_MMR_NIOS2_RESERVE2\t0xFFCFA118\r\n> > +\r\n> > +#define SEQ2CORE_MASK\t\t0xF\r\n> > +#define CORE2SEQ_INT_REQ\t0xF\r\n> > +#define SEQ2CORE_INT_RESP_BIT\t3\r\n> > +\r\n> > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =\r\n> > +\t\t(void *)SOCFPGA_SDR_ADDRESS;\r\n> > +static const struct socfpga_noc_ddr_scheduler\r\n> > *socfpga_noc_ddr_scheduler_base =\r\n> > +\t\t(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;\r\n> > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram\r\n> > +\t\t*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =\r\n> > +\t\t(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;\r\n> > +static const struct socfpga_noc_fw_ddr_l3\r\n> > *socfpga_noc_fw_ddr_l3_base =\r\n> > +\t\t(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;\r\n> > +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =\r\n> > +\t\t(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;\r\n> > +\r\n> > +/* The followring are the supported configurations */\r\n> > +static u32 ddr_config[] = {\r\n> > +\t/* Chip - Row - Bank - Column Style */\r\n> > +\t/* All Types */\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 12),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 13),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 14),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 15),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 16),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 10, 17),\r\n> > +\t/* LPDDR x16 */\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 11, 14),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 11, 15),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 11, 16),\r\n> > +\tARRIA_DDR_CONFIG(0, 3, 12, 15),\r\n> > +\t/* DDR4 Only */\r\n> > +\tARRIA_DDR_CONFIG(0, 4, 10, 14),\r\n> > +\tARRIA_DDR_CONFIG(0, 4, 10, 15),\r\n> > +\tARRIA_DDR_CONFIG(0, 4, 10, 16),\r\n> > +\tARRIA_DDR_CONFIG(0, 4, 10, 17),\t/* 14 */\r\n> > +\t/* Chip - Bank - Row - Column Style */\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 12),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 13),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 14),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 15),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 16),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 10, 17),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 11, 14),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 11, 15),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 11, 16),\r\n> > +\tARRIA_DDR_CONFIG(1, 3, 12, 15),\r\n> > +\t/* DDR4 Only */\r\n> > +\tARRIA_DDR_CONFIG(1, 4, 10, 14),\r\n> > +\tARRIA_DDR_CONFIG(1, 4, 10, 15),\r\n> > +\tARRIA_DDR_CONFIG(1, 4, 10, 16),\r\n> > +\tARRIA_DDR_CONFIG(1, 4, 10, 17),\r\n> > +};\r\n> > +\r\n> > +static int match_ddr_conf(u32 ddr_conf)\r\n> > +{\r\n> > +\tint i;\r\n> > +\r\n> > +\tfor (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {\r\n> > +\t\tif (ddr_conf == ddr_config[i])\r\n> > +\t\t\treturn i;\r\n> > +\t}\r\n> > +\treturn 0;\r\n> > +}\r\n> > +\r\n> > +/* Check whether SDRAM is successfully Calibrated */\r\n> > +static int is_sdram_cal_success(void)\r\n> > +{\r\n> > +\treturn readl(&socfpga_ecc_hmc_base->ddrcalstat);\r\n> > +}\r\n> > +\r\n> > +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)\r\n> > +{\r\n> > +\tu32 reg = readl(ereg);\r\n> > +\r\n> > +\treturn (reg & (1 << bit)) ? 1 : 0;\r\n> Urgh, BIT() and just use it inline and drop this\r\n> \r\nOkay.\r\n> > \r\n> > +}\r\n> > +\r\n> > +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,\r\n> > +\t\t\t   u32 expected, u32 timeout_usec)\r\n> > +{\r\n> > +\tu32 tmr;\r\n> > +\r\n> > +\tfor (tmr = 0; tmr < timeout_usec; tmr += 100) {\r\n> > +\t\tudelay(100);\r\n> > +\t\tWATCHDOG_RESET();\r\n> > +\t\tif (ddr_get_bit(ereg, bit) == expected)\r\n> > +\t\t\treturn 0;\r\n> > +\t}\r\n> > +\r\n> > +\treturn 1;\r\n> > +}\r\n> > +\r\n> > +static void ddr_delay(u32 delay)\r\n> > +{\r\n> > +\tint tmr;\r\n> > +\r\n> > +\tfor (tmr = 0; tmr < delay; tmr++) {\r\n> > +\t\tudelay(1000);\r\n> > +\t\tWATCHDOG_RESET();\r\n> So this is mdelay(delay) ?\r\n> \r\nYes, i can use mdelay.\r\n> > \r\n> > +\t}\r\n> > +}\r\n> > +\r\n> > +static int emif_clear(void)\r\n> > +{\r\n> > +\tu32 s2c;\r\n> > +\tu32 i = DDR_MAX_TRIES;\r\n> > +\r\n> > +\twritel(0, DDR_REG_CORE2SEQ);\r\n> > +\tdo {\r\n> > +\t\tddr_delay(50);\r\n> > +\t\ts2c = readl(DDR_REG_SEQ2CORE);\r\n> > +\t} while ((s2c & SEQ2CORE_MASK) && (--i > 0));\r\n> wait_for_bit() or something ?\r\n> \r\nOkay.\r\n> > \r\n> > +\treturn !i;\r\n> > +}\r\n> > +\r\n> > +static int emif_reset(void)\r\n> > +{\r\n> > +\tu32 c2s, s2c;\r\n> > +\r\n> > +\tc2s = readl(DDR_REG_CORE2SEQ);\r\n> > +\ts2c = readl(DDR_REG_SEQ2CORE);\r\n> > +\r\n> > +\tdebug(\"c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x\r\n> > dst=%08x\\n\",\r\n> > +\t\tc2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),\r\n> > +\t\treadl(IO48_MMR_NIOS2_RESERVE1),\r\n> > +\t\treadl(IO48_MMR_NIOS2_RESERVE2),\r\n> > +\t\treadl(IO48_MMR_DRAMSTS));\r\n> > +\r\n> > +\tif ((s2c & SEQ2CORE_MASK) && emif_clear()) {\r\n> > +\t\tprintf(\"failed emif_clear()\\n\");\r\n> > +\t\treturn -1;\r\n> > +\t}\r\n> > +\r\n> > +\twritel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);\r\n> > +\r\n> > +\tif (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT,\r\n> > 0, 1000000)) {\r\n> > +\t\tprintf(\"emif_reset failed to see interrupt\r\n> > acknowledge\\n\");\r\n> > +\t\treturn -2;\r\n> Use proper errno.h codes\r\n> \r\nOkay.\r\n> > \r\n> > +\t} else {\r\n> > +\t\tprintf(\"emif_reset interrupt acknowledged\\n\");\r\n> > +\t}\r\n> > +\r\n> > +\tif (emif_clear()) {\r\n> > +\t\tprintf(\"emif_clear() failed\\n\");\r\n> > +\t\treturn -3;\r\n> > +\t}\r\n> > +\tdebug(\"emif_reset interrupt cleared\\n\");\r\n> > +\r\n> > +\tdebug(\"nr0=%08x nr1=%08x nr2=%08x\\n\",\r\n> > +\t\treadl(IO48_MMR_NIOS2_RESERVE0),\r\n> > +\t\treadl(IO48_MMR_NIOS2_RESERVE1),\r\n> > +\t\treadl(IO48_MMR_NIOS2_RESERVE2));\r\n> > +\r\n> > +\treturn 0;\r\n> > +}\r\n> [...]\r\n> \r\n> > \r\n> > +struct firewall_entry {\r\n> > +\tconst char *prop_name;\r\n> > +\tconst u32 cfg_addr;\r\n> > +\tconst u32 en_addr;\r\n> > +\tconst u32 en_bit;\r\n> > +};\r\n> > +#define FW_MPU_FPGA_ADDRESS \\\r\n> > +\t((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\\\r\n> > +\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)\r\n> > +const struct firewall_entry firewall_table[] = {\r\n> > +\t{\r\n> This seems to be mostly copy-paste of the same stuff ... fix with\r\n> macro.\r\n> \r\nOkay.\r\n> > \r\n> > +\t\t\"altr,mpu0\",\r\n> > +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\r\n> > +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\r\n> > +\t\t\t mpuregion0addr),\r\n> > +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\r\n> > +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\r\n> > +\t\t\t enable),\r\n> > +\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK\r\n> > +\t},\r\n> > +\t{\r\n> > +\t\t\"altr,mpu1\",\r\n> > +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\r\n> > +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\r\n> > +\t\t\t mpuregion1addr),\r\n> > +\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\r\n> > +\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\r\n> > +\t\t\t enable),\r\n> > +\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK\r\n> > +\t},\r\n> [...]\r\n> \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 16:20:33 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,440,1500966000\"; d=\"scan'208\";\n\ta=\"1018474700\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10","Thread-Index":"AQHTNdoCtEGrJJW24kKee0CNuJZ5BqLEzRkAgAGBuYA=","Date":"Tue, 26 Sep 2017 08:20:32 +0000","Message-ID":"<1506414031.27760.20.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>\n\t<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>","In-Reply-To":"<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775375,"web_url":"http://patchwork.ozlabs.org/comment/1775375/","msgid":"<79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>","list_archive_url":null,"date":"2017-09-26T10:35:43","subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Add DDR driver suppport for Arria 10.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>>> ---\n>>>  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +\n>>>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-\n>>>  drivers/ddr/altera/sdram_arria10.c                 | 735\n>>> +++++++++++++++++++++\n>>>  3 files changed, 839 insertions(+), 1 deletion(-)\n>>>  create mode 100644 drivers/ddr/altera/sdram_arria10.c\n>>>\n>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h\n>>> b/arch/arm/mach-socfpga/include/mach/sdram.h\n>>> index 4a9754e..b833fc2 100644\n>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h\n>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h\n>>> @@ -10,6 +10,8 @@\n>>>  \n>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>  #include \n>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>> +#include \n>>>  #endif\n>>>  \n>>>  #endif\n>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n>>> b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n>>> index 1d7b7c1..7af9431 100644\n>>> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n>>> @@ -1,5 +1,5 @@\n>>>  /*\n>>> - * Copyright (C) 2015-2017 Intel Corporation \n>>> + * Copyright (C) 2017 Intel Corporation \n>>>   *\n>>>   * SPDX-License-Identifier:\tGPL-2.0\n>>>   */\n>>> @@ -8,6 +8,7 @@\n>>>  #define _SOCFPGA_SDRAM_ARRIA10_H_\n>>>  \n>>>  #ifndef __ASSEMBLY__\n>>> +int ddr_calibration_sequence(void);\n>>>  \n>>>  struct socfpga_ecc_hmc {\n>>>  \tu32 ip_rev_id;\n>>> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {\n>>>  \tu32 niosreserve1;\n>>>  \tu32 niosreserve2;\n>>>  };\n>>> +\n>>> +union dramaddrw_reg {\n>>> +\tstruct {\n>>> +\t\tu32 cfg_col_addr_width:5;\n>>> +\t\tu32 cfg_row_addr_width:5;\n>>> +\t\tu32 cfg_bank_addr_width:4;\n>>> +\t\tu32 cfg_bank_group_addr_width:2;\n>>> +\t\tu32 cfg_cs_addr_width:3;\n>>> +\t\tu32 reserved:13;\n>>> +\t};\n>> Use regular macros for bitfields, not this crap.\n>>\n> Why regular macros is prefered? Above implementation improve\n> readability, simplify the implementation and saving memory.\n\nBecause that's how U-Boot does it (and the above afair breaks on\ndifferent endianness).\n\n>>>\n>>> +\tu32 word;\n>>> +};\n>>> +\n>>> +union ctrlcfg0_reg {\n>>> +\tstruct {\n>>> +\t\tu32 cfg_mem_type:4;\n>>> +\t\tu32 cfg_dimm_type:3;\n>>> +\t\tu32 cfg_ac_pos:2;\n>>> +\t\tu32 cfg_ctrl_burst_len:5;\n>>> +\t\tu32 reserved:18;  /* Other fields unused */\n>>> +\t};\n>>> +\tu32 word;\n>>> +};\n>> [...]\n\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1dXw4m94z9tXP\n\tfor ;\n\tTue, 26 Sep 2017 21:10:40 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 7154FC21E32; Tue, 26 Sep 2017 11:08:56 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 72417C21F21;\n\tTue, 26 Sep 2017 11:08:00 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A4850C21EDE; Tue, 26 Sep 2017 11:07:41 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10])\n\tby lists.denx.de (Postfix) with ESMTPS id E1C7CC21F02\n\tfor ; Tue, 26 Sep 2017 11:07:37 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y1dTN0Dv9z1qtX4;\n\tTue, 26 Sep 2017 13:07:36 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y1dTM70hjz1r0wb;\n\tTue, 26 Sep 2017 13:07:35 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id tDPbk_9yb8NF; Tue, 26 Sep 2017 13:07:34 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:34 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"7usp+oUXGKm3sKPwgBIkmeR5nT4ro2qNTS91oNSaK1c=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>\n\t<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>\n\t<1506414031.27760.20.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>","Date":"Tue, 26 Sep 2017 12:35:43 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506414031.27760.20.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776032,"web_url":"http://patchwork.ozlabs.org/comment/1776032/","msgid":"<1506488114.3589.12.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T04:55:14","subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Add DDR driver suppport for Arria 10.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > > ---\r\n> > > >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +\r\n> > > >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-\r\n> > > >  drivers/ddr/altera/sdram_arria10.c                 | 735\r\n> > > > +++++++++++++++++++++\r\n> > > >  3 files changed, 839 insertions(+), 1 deletion(-)\r\n> > > >  create mode 100644 drivers/ddr/altera/sdram_arria10.c\r\n> > > > \r\n> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > > > index 4a9754e..b833fc2 100644\r\n> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h\r\n> > > > @@ -10,6 +10,8 @@\r\n> > > >  \r\n> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > >  #include \r\n> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > +#include \r\n> > > >  #endif\r\n> > > >  \r\n> > > >  #endif\r\n> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > > > index 1d7b7c1..7af9431 100644\r\n> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\r\n> > > > @@ -1,5 +1,5 @@\r\n> > > >  /*\r\n> > > > - * Copyright (C) 2015-2017 Intel Corporation \r\n> > > > + * Copyright (C) 2017 Intel Corporation \r\n> > > >   *\r\n> > > >   * SPDX-License-Identifier:\tGPL-2.0\r\n> > > >   */\r\n> > > > @@ -8,6 +8,7 @@\r\n> > > >  #define _SOCFPGA_SDRAM_ARRIA10_H_\r\n> > > >  \r\n> > > >  #ifndef __ASSEMBLY__\r\n> > > > +int ddr_calibration_sequence(void);\r\n> > > >  \r\n> > > >  struct socfpga_ecc_hmc {\r\n> > > >  \tu32 ip_rev_id;\r\n> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {\r\n> > > >  \tu32 niosreserve1;\r\n> > > >  \tu32 niosreserve2;\r\n> > > >  };\r\n> > > > +\r\n> > > > +union dramaddrw_reg {\r\n> > > > +\tstruct {\r\n> > > > +\t\tu32 cfg_col_addr_width:5;\r\n> > > > +\t\tu32 cfg_row_addr_width:5;\r\n> > > > +\t\tu32 cfg_bank_addr_width:4;\r\n> > > > +\t\tu32 cfg_bank_group_addr_width:2;\r\n> > > > +\t\tu32 cfg_cs_addr_width:3;\r\n> > > > +\t\tu32 reserved:13;\r\n> > > > +\t};\r\n> > > Use regular macros for bitfields, not this crap.\r\n> > > \r\n> > Why regular macros is prefered? Above implementation improve\r\n> > readability, simplify the implementation and saving memory.\r\n> Because that's how U-Boot does it (and the above afair breaks on\r\n> different endianness).\r\n> \r\nOkay.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > +\tu32 word;\r\n> > > > +};\r\n> > > > +\r\n> > > > +union ctrlcfg0_reg {\r\n> > > > +\tstruct {\r\n> > > > +\t\tu32 cfg_mem_type:4;\r\n> > > > +\t\tu32 cfg_dimm_type:3;\r\n> > > > +\t\tu32 cfg_ac_pos:2;\r\n> > > > +\t\tu32 cfg_ctrl_burst_len:5;\r\n> > > > +\t\tu32 reserved:18;  /* Other fields unused */\r\n> > > > +\t};\r\n> > > > +\tu32 word;\r\n> > > > +};\r\n> > > [...]\r\n> [...]\r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y259z43pDz9sBW\n\tfor ;\n\tWed, 27 Sep 2017 14:55:51 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 49B06C21DDF; Wed, 27 Sep 2017 04:55:49 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 55929C21D09;\n\tWed, 27 Sep 2017 04:55:47 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 7E675C21C40; Wed, 27 Sep 2017 04:55:41 +0000 (UTC)","from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby lists.denx.de (Postfix) with ESMTPS id 13D0FC21D99\n\tfor ; Wed, 27 Sep 2017 04:55:39 +0000 (UTC)","from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 21:55:38 -0700","from kmsmsx152.gar.corp.intel.com ([172.21.73.87])\n\tby fmsmga004.fm.intel.com with ESMTP; 26 Sep 2017 21:55:37 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX152.gar.corp.intel.com ([169.254.11.206]) with mapi id\n\t14.03.0319.002; Wed, 27 Sep 2017 12:55:15 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,443,1500966000\"; d=\"scan'208\";a=\"316659555\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10","Thread-Index":"AQHTNdoCtEGrJJW24kKee0CNuJZ5BqLEzRkAgAGBuYCAACXGgIABMzQA","Date":"Wed, 27 Sep 2017 04:55:14 +0000","Message-ID":"<1506488114.3589.12.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>\n\t<34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>\n\t<1506414031.27760.20.camel@intel.com>\n\t<79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>","In-Reply-To":"<79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<43FB6785426F014BA19A8F4886410E13@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]