[{"id":1774614,"web_url":"http://patchwork.ozlabs.org/comment/1774614/","msgid":"<5227f4bf-c598-4b9c-eae1-0e35ce89a5dc@denx.de>","list_archive_url":null,"date":"2017-09-25T09:21:08","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Add support to memory allocation in SPL for preparation to enable FAT\n> in SPL. Memory allocation is needed by FAT to work properly.\n> \n> Signed-off-by: Tien Fong Chee \n\nGen 5 does have malloc support in SPL, so what's the deal here ?\n\n> ---\n> include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\n> 1 file changed, 22 insertions(+), 1 deletion(-)\n> \n> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\n> index 7549ee8..9b6719e 100644\n> --- a/include/configs/socfpga_common.h\n> +++ b/include/configs/socfpga_common.h\n> @@ -280,17 +280,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);\n> /*\n> * SPL\n> *\n> - * SRAM Memory layout:\n> + * SRAM Memory layout for gen 5:\n> *\n> * 0xFFFF_0000 ...... Start of SRAM\n> * 0xFFFF_xxxx ...... Top of stack (grows down)\n> * 0xFFFF_yyyy ...... Malloc area\n> * 0xFFFF_zzzz ...... Global Data\n> * 0xFFFF_FF00 ...... End of SRAM\n> + *\n> + * SRAM Memory layout for Arria 10:\n> + * 0xFFE0_0000 ...... Start of SRAM (bottom)\n> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\n> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\n> + * 0xFFEz_zzzz ...... Global Data\n> + * 0xFFE3_FFFF ...... End of SRAM (top)\n> */\n> #define CONFIG_SPL_FRAMEWORK\n> #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RAM_ADDR\n> #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM_SIZE\n> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +/* SPL memory allocation configuration, it is required by FAT feature */\n> +#ifndef CONFIG_SYS_SPL_MALLOC_START\n> +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\n> +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RAM_SIZE - \\\n> +\t\t\t\t\t GENERATED_GBL_DATA_SIZE - \\\n> +\t\t\t\t\t CONFIG_SYS_SPL_MALLOC_SIZE + \\\n> +\t\t\t\t\t CONFIG_SYS_INIT_RAM_ADDR)\n> +#endif\n> +#endif\n> \n> /* SPL SDMMC boot support */\n> #ifdef CONFIG_SPL_MMC_SUPPORT\n> @@ -320,7 +337,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);\n> /*\n> * Stack setup\n> */\n> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADDR\n> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC_START - 1)\n> +#endif\n> \n> /* Extra Environment */\n> #ifndef CONFIG_SPL_BUILD\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:39 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:38 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"/GBjOGRCL0qbqhdv9YuTNn5hdvHLKSY/ZtAxz7RAG+E=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-16-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<5227f4bf-c598-4b9c-eae1-0e35ce89a5dc@denx.de>","Date":"Mon, 25 Sep 2017 11:21:08 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-16-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775163,"web_url":"http://patchwork.ozlabs.org/comment/1775163/","msgid":"<1506402366.27760.13.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T05:06:06","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Add support to memory allocation in SPL for preparation to enable\r\n> > FAT\r\n> > in SPL. Memory allocation is needed by FAT to work properly.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> Gen 5 does have malloc support in SPL, so what's the deal here ?\r\n> \r\nFor FAT to work properly in Arria 10 SPL, SPL malloc need to be\r\nenabled, and the min of SPL malloc size is 0x2000. FAT needed in Arria\r\n10 SPL, because u-boot.img is stored in FAT partition.\r\n> > \r\n> > ---\r\n> >  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\r\n> >  1 file changed, 22 insertions(+), 1 deletion(-)\r\n> > \r\n> > diff --git a/include/configs/socfpga_common.h\r\n> > b/include/configs/socfpga_common.h\r\n> > index 7549ee8..9b6719e 100644\r\n> > --- a/include/configs/socfpga_common.h\r\n> > +++ b/include/configs/socfpga_common.h\r\n> > @@ -280,17 +280,34 @@ unsigned int\r\n> > cm_get_qspi_controller_clk_hz(void);\r\n> >  /*\r\n> >   * SPL\r\n> >   *\r\n> > - * SRAM Memory layout:\r\n> > + * SRAM Memory layout for gen 5:\r\n> >   *\r\n> >   * 0xFFFF_0000 ...... Start of SRAM\r\n> >   * 0xFFFF_xxxx ...... Top of stack (grows down)\r\n> >   * 0xFFFF_yyyy ...... Malloc area\r\n> >   * 0xFFFF_zzzz ...... Global Data\r\n> >   * 0xFFFF_FF00 ...... End of SRAM\r\n> > + *\r\n> > + * SRAM Memory layout for Arria 10:\r\n> > + * 0xFFE0_0000 ...... Start of SRAM (bottom)\r\n> > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\r\n> > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\r\n> > + * 0xFFEz_zzzz ...... Global Data\r\n> > + * 0xFFE3_FFFF ...... End of SRAM (top)\r\n> >   */\r\n> >  #define CONFIG_SPL_FRAMEWORK\r\n> >  #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RAM_AD\r\n> > DR\r\n> >  #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM_SIZ\r\n> > E\r\n> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +/* SPL memory allocation configuration, it is required by FAT\r\n> > feature */\r\n> > +#ifndef CONFIG_SYS_SPL_MALLOC_START\r\n> > +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\r\n> > +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RAM_SI\r\n> > ZE - \\\r\n> > +\t\t\t\t\t GENERATED_GBL_DATA_SIZE -\r\n> > \\\r\n> > +\t\t\t\t\t CONFIG_SYS_SPL_MALLOC_SIZ\r\n> > E + \\\r\n> > +\t\t\t\t\t CONFIG_SYS_INIT_RAM_ADDR)\r\n> > +#endif\r\n> > +#endif\r\n> >  \r\n> >  /* SPL SDMMC boot support */\r\n> >  #ifdef CONFIG_SPL_MMC_SUPPORT\r\n> > @@ -320,7 +337,11 @@ unsigned int\r\n> > cm_get_qspi_controller_clk_hz(void);\r\n> >  /*\r\n> >   * Stack setup\r\n> >   */\r\n> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >  #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADDR\r\n> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC_STA\r\n> > RT - 1)\r\n> > +#endif\r\n> >  \r\n> >  /* Extra Environment */\r\n> >  #ifndef CONFIG_SPL_BUILD\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 13:06:06 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,439,1500966000\"; d=\"scan'208\";a=\"903851954\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","Thread-Index":"AQHTNdoEzN5iTDIeUkW1zfW5wtX0FaLEzW0AgAFLEwA=","Date":"Tue, 26 Sep 2017 05:06:06 +0000","Message-ID":"<1506402366.27760.13.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-16-git-send-email-tien.fong.chee@intel.com>\n\t<5227f4bf-c598-4b9c-eae1-0e35ce89a5dc@denx.de>","In-Reply-To":"<5227f4bf-c598-4b9c-eae1-0e35ce89a5dc@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775372,"web_url":"http://patchwork.ozlabs.org/comment/1775372/","msgid":"<4802cf18-3966-b8fc-2f15-17fb2c8892e4@denx.de>","list_archive_url":null,"date":"2017-09-26T10:37:09","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Add support to memory allocation in SPL for preparation to enable\n>>> FAT\n>>> in SPL. Memory allocation is needed by FAT to work properly.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>> Gen 5 does have malloc support in SPL, so what's the deal here ?\n>>\n> For FAT to work properly in Arria 10 SPL, SPL malloc need to be\n> enabled,\n\nIt is already enabled on Gen 5\n\n> and the min of SPL malloc size is 0x2000.\n\nWhere did you find about this minimum ? That can be configured ...\n\n> FAT needed in Arria\n> 10 SPL, because u-boot.img is stored in FAT partition.\n\nIt can also be stored on ext partition (which is preferred, patent-wise)\n\n>>>\n>>> ---\n>>>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\n>>>  1 file changed, 22 insertions(+), 1 deletion(-)\n>>>\n>>> diff --git a/include/configs/socfpga_common.h\n>>> b/include/configs/socfpga_common.h\n>>> index 7549ee8..9b6719e 100644\n>>> --- a/include/configs/socfpga_common.h\n>>> +++ b/include/configs/socfpga_common.h\n>>> @@ -280,17 +280,34 @@ unsigned int\n>>> cm_get_qspi_controller_clk_hz(void);\n>>>  /*\n>>>   * SPL\n>>>   *\n>>> - * SRAM Memory layout:\n>>> + * SRAM Memory layout for gen 5:\n>>>   *\n>>>   * 0xFFFF_0000 ...... Start of SRAM\n>>>   * 0xFFFF_xxxx ...... Top of stack (grows down)\n>>>   * 0xFFFF_yyyy ...... Malloc area\n>>>   * 0xFFFF_zzzz ...... Global Data\n>>>   * 0xFFFF_FF00 ...... End of SRAM\n>>> + *\n>>> + * SRAM Memory layout for Arria 10:\n>>> + * 0xFFE0_0000 ...... Start of SRAM (bottom)\n>>> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\n>>> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\n>>> + * 0xFFEz_zzzz ...... Global Data\n>>> + * 0xFFE3_FFFF ...... End of SRAM (top)\n>>>   */\n>>>  #define CONFIG_SPL_FRAMEWORK\n>>>  #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RAM_AD\n>>> DR\n>>>  #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM_SIZ\n>>> E\n>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>> +/* SPL memory allocation configuration, it is required by FAT\n>>> feature */\n>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START\n>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\n>>> +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RAM_SI\n>>> ZE - \\\n>>> +\t\t\t\t\t GENERATED_GBL_DATA_SIZE -\n>>> \\\n>>> +\t\t\t\t\t CONFIG_SYS_SPL_MALLOC_SIZ\n>>> E + \\\n>>> +\t\t\t\t\t CONFIG_SYS_INIT_RAM_ADDR)\n>>> +#endif\n>>> +#endif\n>>>  \n>>>  /* SPL SDMMC boot support */\n>>>  #ifdef CONFIG_SPL_MMC_SUPPORT\n>>> @@ -320,7 +337,11 @@ unsigned int\n>>> cm_get_qspi_controller_clk_hz(void);\n>>>  /*\n>>>   * Stack setup\n>>>   */\n>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>  #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADDR\n>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>> +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC_STA\n>>> RT - 1)\n>>> +#endif\n>>>  \n>>>  /* Extra Environment */\n>>>  #ifndef CONFIG_SPL_BUILD\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506402366.27760.13.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776038,"web_url":"http://patchwork.ozlabs.org/comment/1776038/","msgid":"<1506491001.3589.19.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T05:43:22","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Add support to memory allocation in SPL for preparation to\r\n> > > > enable\r\n> > > > FAT\r\n> > > > in SPL. Memory allocation is needed by FAT to work properly.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > Gen 5 does have malloc support in SPL, so what's the deal here ?\r\n> > > \r\n> > For FAT to work properly in Arria 10 SPL, SPL malloc need to be\r\n> > enabled,\r\n> It is already enabled on Gen 5\r\n> \r\nI think i have confused you, this patch is for getting the malloc area\r\nmapping to Arria 10 SRAM memory correctly. I will improve the commit\r\nmessage.\r\n> > \r\n> > and the min of SPL malloc size is 0x2000.\r\n> Where did you find about this minimum ? That can be configured ...\r\n> \r\nI having issue to boot u-boot successful(Hung or reset), after debuging\r\nthrough debugger, just found that 0x2000 is min required.\r\n> > \r\n> > FAT needed in Arria\r\n> > 10 SPL, because u-boot.img is stored in FAT partition.\r\n> It can also be stored on ext partition (which is preferred, patent-\r\n> wise)\r\n> \r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > ---\r\n> > > >  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\r\n> > > >  1 file changed, 22 insertions(+), 1 deletion(-)\r\n> > > > \r\n> > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > b/include/configs/socfpga_common.h\r\n> > > > index 7549ee8..9b6719e 100644\r\n> > > > --- a/include/configs/socfpga_common.h\r\n> > > > +++ b/include/configs/socfpga_common.h\r\n> > > > @@ -280,17 +280,34 @@ unsigned int\r\n> > > > cm_get_qspi_controller_clk_hz(void);\r\n> > > >  /*\r\n> > > >   * SPL\r\n> > > >   *\r\n> > > > - * SRAM Memory layout:\r\n> > > > + * SRAM Memory layout for gen 5:\r\n> > > >   *\r\n> > > >   * 0xFFFF_0000 ...... Start of SRAM\r\n> > > >   * 0xFFFF_xxxx ...... Top of stack (grows down)\r\n> > > >   * 0xFFFF_yyyy ...... Malloc area\r\n> > > >   * 0xFFFF_zzzz ...... Global Data\r\n> > > >   * 0xFFFF_FF00 ...... End of SRAM\r\n> > > > + *\r\n> > > > + * SRAM Memory layout for Arria 10:\r\n> > > > + * 0xFFE0_0000 ...... Start of SRAM (bottom)\r\n> > > > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\r\n> > > > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\r\n> > > > + * 0xFFEz_zzzz ...... Global Data\r\n> > > > + * 0xFFE3_FFFF ...... End of SRAM (top)\r\n> > > >   */\r\n> > > >  #define CONFIG_SPL_FRAMEWORK\r\n> > > >  #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RA\r\n> > > > M_AD\r\n> > > > DR\r\n> > > >  #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM\r\n> > > > _SIZ\r\n> > > > E\r\n> > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > +/* SPL memory allocation configuration, it is required by FAT\r\n> > > > feature */\r\n> > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START\r\n> > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\r\n> > > > +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RA\r\n> > > > M_SI\r\n> > > > ZE - \\\r\n> > > > +\t\t\t\t\t GENERATED_GBL_DATA_SI\r\n> > > > ZE -\r\n> > > > \\\r\n> > > > +\t\t\t\t\t CONFIG_SYS_SPL_MALLOC\r\n> > > > _SIZ\r\n> > > > E + \\\r\n> > > > +\t\t\t\t\t CONFIG_SYS_INIT_RAM_A\r\n> > > > DDR)\r\n> > > > +#endif\r\n> > > > +#endif\r\n> > > >  \r\n> > > >  /* SPL SDMMC boot support */\r\n> > > >  #ifdef CONFIG_SPL_MMC_SUPPORT\r\n> > > > @@ -320,7 +337,11 @@ unsigned int\r\n> > > > cm_get_qspi_controller_clk_hz(void);\r\n> > > >  /*\r\n> > > >   * Stack setup\r\n> > > >   */\r\n> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > >  #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADD\r\n> > > > R\r\n> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC\r\n> > > > _STA\r\n> > > > RT - 1)\r\n> > > > +#endif\r\n> > > >  \r\n> > > >  /* Extra Environment */\r\n> > > >  #ifndef CONFIG_SPL_BUILD\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y26FF5WTmz9t2Q\n\tfor ;\n\tWed, 27 Sep 2017 15:43:44 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 80699C21DA3; Wed, 27 Sep 2017 05:43:33 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CF1E7C21C45;\n\tWed, 27 Sep 2017 05:43:30 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 6CADDC21C45; Wed, 27 Sep 2017 05:43:29 +0000 (UTC)","from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby lists.denx.de (Postfix) with ESMTPS id 5AB27C21C40\n\tfor ; Wed, 27 Sep 2017 05:43:28 +0000 (UTC)","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga105.jf.intel.com with ESMTP; 26 Sep 2017 22:43:24 -0700","from pgsmsx106.gar.corp.intel.com ([10.221.44.98])\n\tby orsmga002.jf.intel.com with ESMTP; 26 Sep 2017 22:43:23 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX106.gar.corp.intel.com ([169.254.9.199]) with mapi id\n\t14.03.0319.002; Wed, 27 Sep 2017 13:43:22 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,443,1500966000\"; d=\"scan'208\";a=\"139912261\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","Thread-Index":"AQHTNdoEzN5iTDIeUkW1zfW5wtX0FaLEzW0AgAFLEwCAAFx/gIABQD6A","Date":"Wed, 27 Sep 2017 05:43:22 +0000","Message-ID":"<1506491001.3589.19.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-16-git-send-email-tien.fong.chee@intel.com>\n\t<5227f4bf-c598-4b9c-eae1-0e35ce89a5dc@denx.de>\n\t<1506402366.27760.13.camel@intel.com>\n\t<4802cf18-3966-b8fc-2f15-17fb2c8892e4@denx.de>","In-Reply-To":"<4802cf18-3966-b8fc-2f15-17fb2c8892e4@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<1AAFDA709E5A354DA0C8EC446294C5D7@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776184,"web_url":"http://patchwork.ozlabs.org/comment/1776184/","msgid":"<21cde1e2-e824-af74-30a6-aacb1aa36e79@denx.de>","list_archive_url":null,"date":"2017-09-27T08:32:52","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/27/2017 07:43 AM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\n>> On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> Add support to memory allocation in SPL for preparation to\n>>>>> enable\n>>>>> FAT\n>>>>> in SPL. Memory allocation is needed by FAT to work properly.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>>>> Gen 5 does have malloc support in SPL, so what's the deal here ?\n>>>>\n>>> For FAT to work properly in Arria 10 SPL, SPL malloc need to be\n>>> enabled,\n>> It is already enabled on Gen 5\n>>\n> I think i have confused you, this patch is for getting the malloc area\n> mapping to Arria 10 SRAM memory correctly. I will improve the commit\n> message.\n>>>\n>>> and the min of SPL malloc size is 0x2000.\n>> Where did you find about this minimum ? That can be configured ...\n>>\n> I having issue to boot u-boot successful(Hung or reset), after debuging\n> through debugger, just found that 0x2000 is min required.\n\nYou can set the value much lower and depending on the requirements, it\nwill work, so the problem must be elsewhere ...\n\n>>>\n>>> FAT needed in Arria\n>>> 10 SPL, because u-boot.img is stored in FAT partition.\n>> It can also be stored on ext partition (which is preferred, patent-\n>> wise)\n>>\n>>>\n>>>>\n>>>>>\n>>>>>\n>>>>> ---\n>>>>>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\n>>>>>  1 file changed, 22 insertions(+), 1 deletion(-)\n>>>>>\n>>>>> diff --git a/include/configs/socfpga_common.h\n>>>>> b/include/configs/socfpga_common.h\n>>>>> index 7549ee8..9b6719e 100644\n>>>>> --- a/include/configs/socfpga_common.h\n>>>>> +++ b/include/configs/socfpga_common.h\n>>>>> @@ -280,17 +280,34 @@ unsigned int\n>>>>> cm_get_qspi_controller_clk_hz(void);\n>>>>>  /*\n>>>>>   * SPL\n>>>>>   *\n>>>>> - * SRAM Memory layout:\n>>>>> + * SRAM Memory layout for gen 5:\n>>>>>   *\n>>>>>   * 0xFFFF_0000 ...... Start of SRAM\n>>>>>   * 0xFFFF_xxxx ...... Top of stack (grows down)\n>>>>>   * 0xFFFF_yyyy ...... Malloc area\n>>>>>   * 0xFFFF_zzzz ...... Global Data\n>>>>>   * 0xFFFF_FF00 ...... End of SRAM\n>>>>> + *\n>>>>> + * SRAM Memory layout for Arria 10:\n>>>>> + * 0xFFE0_0000 ...... Start of SRAM (bottom)\n>>>>> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\n>>>>> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\n>>>>> + * 0xFFEz_zzzz ...... Global Data\n>>>>> + * 0xFFE3_FFFF ...... End of SRAM (top)\n>>>>>   */\n>>>>>  #define CONFIG_SPL_FRAMEWORK\n>>>>>  #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RA\n>>>>> M_AD\n>>>>> DR\n>>>>>  #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM\n>>>>> _SIZ\n>>>>> E\n>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>>>> +/* SPL memory allocation configuration, it is required by FAT\n>>>>> feature */\n>>>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START\n>>>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\n>>>>> +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RA\n>>>>> M_SI\n>>>>> ZE - \\\n>>>>> +\t\t\t\t\t GENERATED_GBL_DATA_SI\n>>>>> ZE -\n>>>>> \\\n>>>>> +\t\t\t\t\t CONFIG_SYS_SPL_MALLOC\n>>>>> _SIZ\n>>>>> E + \\\n>>>>> +\t\t\t\t\t CONFIG_SYS_INIT_RAM_A\n>>>>> DDR)\n>>>>> +#endif\n>>>>> +#endif\n>>>>>  \n>>>>>  /* SPL SDMMC boot support */\n>>>>>  #ifdef CONFIG_SPL_MMC_SUPPORT\n>>>>> @@ -320,7 +337,11 @@ unsigned int\n>>>>> cm_get_qspi_controller_clk_hz(void);\n>>>>>  /*\n>>>>>   * Stack setup\n>>>>>   */\n>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>>>  #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADD\n>>>>> R\n>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>>>> +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC\n>>>>> _STA\n>>>>> RT - 1)\n>>>>> +#endif\n>>>>>  \n>>>>>  /* Extra Environment */\n>>>>>  #ifndef CONFIG_SPL_BUILD\n>>>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506491001.3589.19.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776730,"web_url":"http://patchwork.ozlabs.org/comment/1776730/","msgid":"<1506566914.3589.40.camel@intel.com>","list_archive_url":null,"date":"2017-09-28T02:48:40","subject":"Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Rab, 2017-09-27 at 10:32 +0200, Marek Vasut wrote:\r\n> On 09/27/2017 07:43 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > Add support to memory allocation in SPL for preparation to\r\n> > > > > > enable\r\n> > > > > > FAT\r\n> > > > > > in SPL. Memory allocation is needed by FAT to work\r\n> > > > > > properly.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > > > Gen 5 does have malloc support in SPL, so what's the deal\r\n> > > > > here ?\r\n> > > > > \r\n> > > > For FAT to work properly in Arria 10 SPL, SPL malloc need to be\r\n> > > > enabled,\r\n> > > It is already enabled on Gen 5\r\n> > > \r\n> > I think i have confused you, this patch is for getting the malloc\r\n> > area\r\n> > mapping to Arria 10 SRAM memory correctly. I will improve the\r\n> > commit\r\n> > message.\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > and the min of SPL malloc size is 0x2000.\r\n> > > Where did you find about this minimum ? That can be configured\r\n> > > ...\r\n> > > \r\n> > I having issue to boot u-boot successful(Hung or reset), after\r\n> > debuging\r\n> > through debugger, just found that 0x2000 is min required.\r\n> You can set the value much lower and depending on the requirements,\r\n> it\r\n> will work, so the problem must be elsewhere ...\r\n> \r\nOkay, i will test it out.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > FAT needed in Arria\r\n> > > > 10 SPL, because u-boot.img is stored in FAT partition.\r\n> > > It can also be stored on ext partition (which is preferred,\r\n> > > patent-\r\n> > > wise)\r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > ---\r\n> > > > > >  include/configs/socfpga_common.h | 23\r\n> > > > > > ++++++++++++++++++++++-\r\n> > > > > >  1 file changed, 22 insertions(+), 1 deletion(-)\r\n> > > > > > \r\n> > > > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > > > b/include/configs/socfpga_common.h\r\n> > > > > > index 7549ee8..9b6719e 100644\r\n> > > > > > --- a/include/configs/socfpga_common.h\r\n> > > > > > +++ b/include/configs/socfpga_common.h\r\n> > > > > > @@ -280,17 +280,34 @@ unsigned int\r\n> > > > > > cm_get_qspi_controller_clk_hz(void);\r\n> > > > > >  /*\r\n> > > > > >   * SPL\r\n> > > > > >   *\r\n> > > > > > - * SRAM Memory layout:\r\n> > > > > > + * SRAM Memory layout for gen 5:\r\n> > > > > >   *\r\n> > > > > >   * 0xFFFF_0000 ...... Start of SRAM\r\n> > > > > >   * 0xFFFF_xxxx ...... Top of stack (grows down)\r\n> > > > > >   * 0xFFFF_yyyy ...... Malloc area\r\n> > > > > >   * 0xFFFF_zzzz ...... Global Data\r\n> > > > > >   * 0xFFFF_FF00 ...... End of SRAM\r\n> > > > > > + *\r\n> > > > > > + * SRAM Memory layout for Arria 10:\r\n> > > > > > + * 0xFFE0_0000 ...... Start of SRAM (bottom)\r\n> > > > > > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\r\n> > > > > > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)\r\n> > > > > > + * 0xFFEz_zzzz ...... Global Data\r\n> > > > > > + * 0xFFE3_FFFF ...... End of SRAM (top)\r\n> > > > > >   */\r\n> > > > > >  #define CONFIG_SPL_FRAMEWORK\r\n> > > > > >  #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INI\r\n> > > > > > T_RA\r\n> > > > > > M_AD\r\n> > > > > > DR\r\n> > > > > >  #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT\r\n> > > > > > _RAM\r\n> > > > > > _SIZ\r\n> > > > > > E\r\n> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > > > +/* SPL memory allocation configuration, it is required by\r\n> > > > > > FAT\r\n> > > > > > feature */\r\n> > > > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START\r\n> > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\r\n> > > > > > +#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INI\r\n> > > > > > T_RA\r\n> > > > > > M_SI\r\n> > > > > > ZE - \\\r\n> > > > > > +\t\t\t\t\t GENERATED_GBL_DAT\r\n> > > > > > A_SI\r\n> > > > > > ZE -\r\n> > > > > > \\\r\n> > > > > > +\t\t\t\t\t CONFIG_SYS_SPL_MA\r\n> > > > > > LLOC\r\n> > > > > > _SIZ\r\n> > > > > > E + \\\r\n> > > > > > +\t\t\t\t\t CONFIG_SYS_INIT_R\r\n> > > > > > AM_A\r\n> > > > > > DDR)\r\n> > > > > > +#endif\r\n> > > > > > +#endif\r\n> > > > > >  \r\n> > > > > >  /* SPL SDMMC boot support */\r\n> > > > > >  #ifdef CONFIG_SPL_MMC_SUPPORT\r\n> > > > > > @@ -320,7 +337,11 @@ unsigned int\r\n> > > > > > cm_get_qspi_controller_clk_hz(void);\r\n> > > > > >  /*\r\n> > > > > >   * Stack setup\r\n> > > > > >   */\r\n> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > > > >  #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP\r\n> > > > > > _ADD\r\n> > > > > > R\r\n> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > > > > +#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MA\r\n> > > > > > LLOC\r\n> > > > > > _STA\r\n> > > > > > RT - 1)\r\n> > > > > > +#endif\r\n> > > > > >  \r\n> > > > > >  /* Extra Environment */\r\n> > > > > >  #ifndef CONFIG_SPL_BUILD\r\n> > > > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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