[{"id":1774612,"web_url":"http://patchwork.ozlabs.org/comment/1774612/","msgid":"<2b0dec3a-6d53-f10f-55a5-4dbdd1659691@denx.de>","list_archive_url":null,"date":"2017-09-25T09:20:24","subject":"Re: [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR\n\tArria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> This patch is for enabling the DDR support on Arria 10.\n> \n> Signed-off-by: Tien Fong Chee \n> ---\n> drivers/ddr/altera/Makefile | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile\n> index ac4ab85..02f8b7c 100644\n> --- a/drivers/ddr/altera/Makefile\n> +++ b/drivers/ddr/altera/Makefile\n> @@ -10,4 +10,5 @@\n> \n> ifdef CONFIG_ALTERA_SDRAM\n> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o\n> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o\n> endif\n> \nThis should be part of the patch which added the sdram_arria10.c","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10GG1pvVz9tXG\n\tfor ;\n\tMon, 25 Sep 2017 20:10:46 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E4F6EC22154; Mon, 25 Sep 2017 10:04:44 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 45C80C220E5;\n\tMon, 25 Sep 2017 09:59:03 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 5D185C221B5; Mon, 25 Sep 2017 09:58:42 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10])\n\tby lists.denx.de (Postfix) with ESMTPS id BA58BC220DA\n\tfor ; Mon, 25 Sep 2017 09:58:38 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y100G3tnZz1qtPZ;\n\tMon, 25 Sep 2017 11:58:38 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y100G3Y08z1qqkh;\n\tMon, 25 Sep 2017 11:58:38 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id 9SUVMwrXUqOm; Mon, 25 Sep 2017 11:58:37 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:37 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"9l7IJSHj+YhG1Oa3tCzCwdHs2Y0FNtcAzWnJ9C5pqB8=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-15-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<2b0dec3a-6d53-f10f-55a5-4dbdd1659691@denx.de>","Date":"Mon, 25 Sep 2017 11:20:24 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-15-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775162,"web_url":"http://patchwork.ozlabs.org/comment/1775162/","msgid":"<1506402409.27760.14.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T05:06:49","subject":"Re: [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR\n\tArria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:20 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > This patch is for enabling the DDR support on Arria 10.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> > ---\r\n> >  drivers/ddr/altera/Makefile | 1 +\r\n> >  1 file changed, 1 insertion(+)\r\n> > \r\n> > diff --git a/drivers/ddr/altera/Makefile\r\n> > b/drivers/ddr/altera/Makefile\r\n> > index ac4ab85..02f8b7c 100644\r\n> > --- a/drivers/ddr/altera/Makefile\r\n> > +++ b/drivers/ddr/altera/Makefile\r\n> > @@ -10,4 +10,5 @@\r\n> >  \r\n> >  ifdef CONFIG_ALTERA_SDRAM\r\n> >  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o\r\n> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o\r\n> >  endif\r\n> > \r\n> This should be part of the patch which added the sdram_arria10.c\r\n> \r\nOkay.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1TTs0J0Rz9t49\n\tfor ;\n\tTue, 26 Sep 2017 15:07:27 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 7D756C21F95; Tue, 26 Sep 2017 05:07:20 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6BCDFC21D5B;\n\tTue, 26 Sep 2017 05:07:18 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 34650C21D5B; Tue, 26 Sep 2017 05:07:17 +0000 (UTC)","from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby lists.denx.de (Postfix) with ESMTPS id A8967C21CA5\n\tfor ; Tue, 26 Sep 2017 05:07:15 +0000 (UTC)","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga105.jf.intel.com with ESMTP; 25 Sep 2017 22:07:12 -0700","from pgsmsx106.gar.corp.intel.com ([10.221.44.98])\n\tby orsmga002.jf.intel.com with ESMTP; 25 Sep 2017 22:07:11 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX106.gar.corp.intel.com ([169.254.9.199]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 13:06:50 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,439,1500966000\"; d=\"scan'208\";a=\"139432727\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 14/19] arm: socfpga: Enable build for DDR Arria 10","Thread-Index":"AQHTNdoEhu1fYYDXH0K8IXDd6AsWmqLEzTgAgAFLe4A=","Date":"Tue, 26 Sep 2017 05:06:49 +0000","Message-ID":"<1506402409.27760.14.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-15-git-send-email-tien.fong.chee@intel.com>\n\t<2b0dec3a-6d53-f10f-55a5-4dbdd1659691@denx.de>","In-Reply-To":"<2b0dec3a-6d53-f10f-55a5-4dbdd1659691@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR\n\tArria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]