[{"id":1774617,"web_url":"http://patchwork.ozlabs.org/comment/1774617/","msgid":"<3186f594-ba7c-a36f-3baf-b4e524499cf6@denx.de>","list_archive_url":null,"date":"2017-09-25T09:24:25","subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.\n\nThis patch seems to be doing more than just one thing ...\n\n> Signed-off-by: Tien Fong Chee \n> ---\n> arch/arm/mach-socfpga/spl.c | 55 +++++++++++++++++++++++++++++++++++++\n> common/spl/spl_mmc.c | 2 +-\n> configs/socfpga_arria10_defconfig | 57 ++++++++++++++++++++++++++++++++++-----\n> include/spl.h | 2 ++\n> 4 files changed, 108 insertions(+), 8 deletions(-)\n> \n> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c\n> index aba116d..9b381bb 100644\n> --- a/arch/arm/mach-socfpga/spl.c\n> +++ b/arch/arm/mach-socfpga/spl.c\n> @@ -15,6 +15,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -22,6 +23,10 @@\n> #include \n> #include \n> #include \n> +#include \n> +#include \n> +#include \n> +#include \n> #include \n> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> #include \n> @@ -29,6 +34,9 @@\n> \n> DECLARE_GLOBAL_DATA_PTR;\n> \n> +#define BSIZE\t4096\n> +#define PERIPH_RBF\t0\n> +\n> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> static struct pl310_regs *const pl310 =\n> \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n> @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)\n> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> void spl_board_init(void)\n> {\n> +\tint rval = 0;\n> +\tint len = 0;\n> +\tu32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);\n> +\tstruct spl_boot_device bootdev;\n> +\tfpga_fs_info fpga_fsinfo;\n> +\n> \t/* configuring the clock based on handoff */\n> \tcm_basic_init(gd->fdt_blob);\n> \tWATCHDOG_RESET();\n> @@ -214,6 +228,47 @@ void spl_board_init(void)\n> \n> \t/* Add device descriptor to FPGA device table */\n> \tsocfpga_fpga_add();\n> +\n> +\tbootdev.boot_device = spl_boot_device();\n> +\n> +\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\n> +\t\tstruct mmc *mmc = NULL;\n> +\t\tint err = 0;\n> +\n> +\t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\n> +\n> +\t\terr = mmc_init(mmc);\n> +\n> +\t\tif (err) {\n> +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\n> +\t\t\tprintf(\"spl: mmc init failed with error: %d\\n\", err);\n> +#endif\n> +\t\t}\n> +\n> +\t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,\n> +\t\t\t\t\t\t\t\t &len);\n> +\n> +\t\tfpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,\n> +\t\t\t\t\t\t\t\t &len,\n> +\t\t\t\t\t\t\t\tPERIPH_RBF);\n> +\n> +\t\tfpga_fsinfo.interface = \"mmc\";\n> +\n> +\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\n> +\t} else {\n> +\t\tprintf(\"Invalid boot device!\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\t/* Program peripheral RBF */\n> +\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))\n> +\t\trval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);\n> +\n> +\tif (rval > 0) {\n> +\t\tconfig_pins(gd->fdt_blob, \"shared\");\n> +\n> +\t\tddr_calibration_sequence();\n> +\t}\n> }\n> \n> void board_init_f(ulong dummy)\n> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c\n> index b2cccc6..159443f 100644\n> --- a/common/spl/spl_mmc.c\n> +++ b/common/spl/spl_mmc.c\n> @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)\n> \treturn -ENODEV;\n> }\n> \n> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n> {\n> #if CONFIG_IS_ENABLED(DM_MMC)\n> \tstruct udevice *dev;\n> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig\n> index 4c73d73..2ff9801 100644\n> --- a/configs/socfpga_arria10_defconfig\n> +++ b/configs/socfpga_arria10_defconfig\n> @@ -2,33 +2,76 @@ CONFIG_ARM=y\n> CONFIG_ARCH_SOCFPGA=y\n> CONFIG_SYS_MALLOC_F_LEN=0x2000\n> CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y\n> +CONFIG_SPL_STACK_R_ADDR=0x00800000\n> CONFIG_IDENT_STRING=\"socfpga_arria10\"\n> CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\n> -CONFIG_USE_BOOTARGS=y\n> -CONFIG_BOOTARGS=\"console=ttyS0,115200\"\n> CONFIG_DEFAULT_FDT_FILE=\"socfpga_arria10_socdk_sdmmc.dtb\"\n> +CONFIG_FIT=y\n> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y\n> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y\n> +CONFIG_SPL_ENV_SUPPORT=y\n> +CONFIG_VERSION_VARIABLE=y\n> CONFIG_SPL=y\n> +CONFIG_HUSH_PARSER=y\n> CONFIG_SPL_FPGA_SUPPORT=y\n> +CONFIG_SPL_FAT_SUPPORT=y\n> +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768\n> CONFIG_CMD_BOOTZ=y\n> # CONFIG_CMD_IMLS is not set\n> CONFIG_CMD_ASKENV=y\n> CONFIG_CMD_GREPENV=y\n> # CONFIG_CMD_FLASH is not set\n> -CONFIG_CMD_GPIO=y\n> +CONFIG_SPL_LIBDISK_SUPPORT=y\n> +CONFIG_CMD_PART=y\n> CONFIG_CMD_MMC=y\n> +CONFIG_CMD_SF=y\n> +CONFIG_CMD_SPI=y\n> +CONFIG_CMD_I2C=y\n> +CONFIG_SYS_I2C_DW=y\n> +CONFIG_CMD_USB=y\n> +CONFIG_CMD_DFU=y\n> +CONFIG_CMD_USB_MASS_STORAGE=y\n> +CONFIG_CMD_GPIO=y\n> +CONFIG_CMD_MII=y\n> CONFIG_CMD_DHCP=y\n> CONFIG_CMD_PING=y\n> CONFIG_CMD_CACHE=y\n> -CONFIG_CMD_EXT4=y\n> -CONFIG_CMD_EXT4_WRITE=y\n> CONFIG_DOS_PARTITION=y\n> -# CONFIG_SPL_DOS_PARTITION is not set\n> -CONFIG_ENV_IS_IN_MMC=y\n> +CONFIG_SPL_DOS_PARTITION=y\n> +CONFIG_SPL_FS_GENERIC=y\n> +CONFIG_CMD_FAT=y\n> +CONFIG_CMD_FS_GENERIC=y\n> CONFIG_SPL_DM=y\n> CONFIG_SPL_DM_SEQ_ALIAS=y\n> +CONFIG_DFU_MMC=y\n> CONFIG_FPGA_SOCFPGA=y\n> CONFIG_DM_GPIO=y\n> CONFIG_DWAPB_GPIO=y\n> CONFIG_DM_MMC=y\n> +CONFIG_MMC_DW=y\n> +CONFIG_SPI_FLASH=y\n> +CONFIG_SPI_FLASH_BAR=y\n> +CONFIG_SPI_FLASH_SPANSION=y\n> +CONFIG_SPI_FLASH_STMICRO=y\n> +CONFIG_DM_ETH=y\n> +CONFIG_ETH_DESIGNWARE=y\n> CONFIG_SYS_NS16550=y\n> CONFIG_USE_TINY_PRINTF=y\n> +CONFIG_CMD_FPGA_LOADFS=y\n> +CONFIG_CADENCE_QSPI=y\n> +CONFIG_DESIGNWARE_SPI=y\n> +CONFIG_USB=y\n> +CONFIG_DM_USB=y\n> +CONFIG_USB_STORAGE=y\n> +CONFIG_USB_GADGET=y\n> +CONFIG_USB_GADGET_DWC2_OTG=y\n> +CONFIG_USB_GADGET_DOWNLOAD=y\n> +CONFIG_G_DNL_MANUFACTURER=\"altera\"\n> +CONFIG_G_DNL_VENDOR_NUM=0x0525\n> +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\n> +CONFIG_USE_TINY_PRINTF=y\n> +CONFIG_SPL_MMC_SUPPORT=y\n> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\n> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800\n> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y\n> diff --git a/include/spl.h b/include/spl.h\n> index ce4cf0a..e24433d 100644\n> --- a/include/spl.h\n> +++ b/include/spl.h\n> @@ -10,6 +10,7 @@\n> /* Platform-specific defines */\n> #include \n> #include \n> +#include \n> \n> /* Value in r0 indicates we booted from U-Boot */\n> #define UBOOT_NOT_LOADED_FROM_SPL\t0x13578642\n> @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,\n> void preloader_console_init(void);\n> u32 spl_boot_device(void);\n> u32 spl_boot_mode(const u32 boot_device);\n> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);\n> \n> /**\n> * spl_set_header_raw_uboot() - Set up a standard SPL image structure\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10Gv2mbwz9tXG\n\tfor ;\n\tMon, 25 Sep 2017 20:11:19 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 2F227C22145; Mon, 25 Sep 2017 10:06:17 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A1399C22192;\n\tMon, 25 Sep 2017 10:00:18 +0000 (UTC)","by lists.denx.de (Postfix, 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,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775145,"web_url":"http://patchwork.ozlabs.org/comment/1775145/","msgid":"<1506400308.27760.3.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T04:31:48","subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.\r\n> This patch seems to be doing more than just one thing ...\r\n> \r\nI can split into two patches:\r\n1) Enable DDR up by configuring FPGA so SPL able loading U-boot to DDR\r\n2) Setting up configs so SPL can boot U-boot from FAT.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> > ---\r\n> >  arch/arm/mach-socfpga/spl.c       | 55\r\n> > +++++++++++++++++++++++++++++++++++++\r\n> >  common/spl/spl_mmc.c              |  2 +-\r\n> >  configs/socfpga_arria10_defconfig | 57\r\n> > ++++++++++++++++++++++++++++++++++-----\r\n> >  include/spl.h                     |  2 ++\r\n> >  4 files changed, 108 insertions(+), 8 deletions(-)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-\r\n> > socfpga/spl.c\r\n> > index aba116d..9b381bb 100644\r\n> > --- a/arch/arm/mach-socfpga/spl.c\r\n> > +++ b/arch/arm/mach-socfpga/spl.c\r\n> > @@ -15,6 +15,7 @@\r\n> >  #include \r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> >  #include \r\n> >  #include \r\n> >  #include \r\n> > @@ -22,6 +23,10 @@\r\n> >  #include \r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> >  #include \r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> >  #include \r\n> > @@ -29,6 +34,9 @@\r\n> >  \r\n> >  DECLARE_GLOBAL_DATA_PTR;\r\n> >  \r\n> > +#define BSIZE\t4096\r\n> > +#define PERIPH_RBF\t0\r\n> > +\r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >  static struct pl310_regs *const pl310 =\r\n> >  \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\r\n> > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)\r\n> >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> >  void spl_board_init(void)\r\n> >  {\r\n> > +\tint rval = 0;\r\n> > +\tint len = 0;\r\n> > +\tu32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);\r\n> > +\tstruct spl_boot_device bootdev;\r\n> > +\tfpga_fs_info fpga_fsinfo;\r\n> > +\r\n> >  \t/* configuring the clock based on handoff */\r\n> >  \tcm_basic_init(gd->fdt_blob);\r\n> >  \tWATCHDOG_RESET();\r\n> > @@ -214,6 +228,47 @@ void spl_board_init(void)\r\n> >  \r\n> >  \t/* Add device descriptor to FPGA device table */\r\n> >  \tsocfpga_fpga_add();\r\n> > +\r\n> > +\tbootdev.boot_device = spl_boot_device();\r\n> > +\r\n> > +\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\r\n> > +\t\tstruct mmc *mmc = NULL;\r\n> > +\t\tint err = 0;\r\n> > +\r\n> > +\t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\r\n> > +\r\n> > +\t\terr = mmc_init(mmc);\r\n> > +\r\n> > +\t\tif (err) {\r\n> > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\r\n> > +\t\t\tprintf(\"spl: mmc init failed with error:\r\n> > %d\\n\", err);\r\n> > +#endif\r\n> > +\t\t}\r\n> > +\r\n> > +\t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-\r\n> > >fdt_blob,\r\n> > +\t\t\t\t\t\t\t\t &\r\n> > len);\r\n> > +\r\n> > +\t\tfpga_fsinfo.filename = (char\r\n> > *)get_cff_filename(gd->fdt_blob,\r\n> > +\t\t\t\t\t\t\t\t &\r\n> > len,\r\n> > +\t\t\t\t\t\t\t\tPE\r\n> > RIPH_RBF);\r\n> > +\r\n> > +\t\tfpga_fsinfo.interface = \"mmc\";\r\n> > +\r\n> > +\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\r\n> > +\t} else {\r\n> > +\t\tprintf(\"Invalid boot device!\\n\");\r\n> > +\t\treturn;\r\n> > +\t}\r\n> > +\r\n> > +\t/* Program peripheral RBF */\r\n> > +\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len >\r\n> > 0))\r\n> > +\t\trval = fpga_fsload(0, buffer, BSIZE,\r\n> > &fpga_fsinfo);\r\n> > +\r\n> > +\tif (rval > 0) {\r\n> > +\t\tconfig_pins(gd->fdt_blob, \"shared\");\r\n> > +\r\n> > +\t\tddr_calibration_sequence();\r\n> > +\t}\r\n> >  }\r\n> >  \r\n> >  void board_init_f(ulong dummy)\r\n> > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c\r\n> > index b2cccc6..159443f 100644\r\n> > --- a/common/spl/spl_mmc.c\r\n> > +++ b/common/spl/spl_mmc.c\r\n> > @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32\r\n> > boot_device)\r\n> >  \treturn -ENODEV;\r\n> >  }\r\n> >  \r\n> > -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\r\n> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\r\n> >  {\r\n> >  #if CONFIG_IS_ENABLED(DM_MMC)\r\n> >  \tstruct udevice *dev;\r\n> > diff --git a/configs/socfpga_arria10_defconfig\r\n> > b/configs/socfpga_arria10_defconfig\r\n> > index 4c73d73..2ff9801 100644\r\n> > --- a/configs/socfpga_arria10_defconfig\r\n> > +++ b/configs/socfpga_arria10_defconfig\r\n> > @@ -2,33 +2,76 @@ CONFIG_ARM=y\r\n> >  CONFIG_ARCH_SOCFPGA=y\r\n> >  CONFIG_SYS_MALLOC_F_LEN=0x2000\r\n> >  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y\r\n> > +CONFIG_SPL_STACK_R_ADDR=0x00800000\r\n> >  CONFIG_IDENT_STRING=\"socfpga_arria10\"\r\n> >  CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\r\n> > -CONFIG_USE_BOOTARGS=y\r\n> > -CONFIG_BOOTARGS=\"console=ttyS0,115200\"\r\n> >  CONFIG_DEFAULT_FDT_FILE=\"socfpga_arria10_socdk_sdmmc.dtb\"\r\n> > +CONFIG_FIT=y\r\n> > +CONFIG_SYS_CONSOLE_IS_IN_ENV=y\r\n> > +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y\r\n> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y\r\n> > +CONFIG_SPL_ENV_SUPPORT=y\r\n> > +CONFIG_VERSION_VARIABLE=y\r\n> >  CONFIG_SPL=y\r\n> > +CONFIG_HUSH_PARSER=y\r\n> >  CONFIG_SPL_FPGA_SUPPORT=y\r\n> > +CONFIG_SPL_FAT_SUPPORT=y\r\n> > +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768\r\n> >  CONFIG_CMD_BOOTZ=y\r\n> >  # CONFIG_CMD_IMLS is not set\r\n> >  CONFIG_CMD_ASKENV=y\r\n> >  CONFIG_CMD_GREPENV=y\r\n> >  # CONFIG_CMD_FLASH is not set\r\n> > -CONFIG_CMD_GPIO=y\r\n> > +CONFIG_SPL_LIBDISK_SUPPORT=y\r\n> > +CONFIG_CMD_PART=y\r\n> >  CONFIG_CMD_MMC=y\r\n> > +CONFIG_CMD_SF=y\r\n> > +CONFIG_CMD_SPI=y\r\n> > +CONFIG_CMD_I2C=y\r\n> > +CONFIG_SYS_I2C_DW=y\r\n> > +CONFIG_CMD_USB=y\r\n> > +CONFIG_CMD_DFU=y\r\n> > +CONFIG_CMD_USB_MASS_STORAGE=y\r\n> > +CONFIG_CMD_GPIO=y\r\n> > +CONFIG_CMD_MII=y\r\n> >  CONFIG_CMD_DHCP=y\r\n> >  CONFIG_CMD_PING=y\r\n> >  CONFIG_CMD_CACHE=y\r\n> > -CONFIG_CMD_EXT4=y\r\n> > -CONFIG_CMD_EXT4_WRITE=y\r\n> >  CONFIG_DOS_PARTITION=y\r\n> > -# CONFIG_SPL_DOS_PARTITION is not set\r\n> > -CONFIG_ENV_IS_IN_MMC=y\r\n> > +CONFIG_SPL_DOS_PARTITION=y\r\n> > +CONFIG_SPL_FS_GENERIC=y\r\n> > +CONFIG_CMD_FAT=y\r\n> > +CONFIG_CMD_FS_GENERIC=y\r\n> >  CONFIG_SPL_DM=y\r\n> >  CONFIG_SPL_DM_SEQ_ALIAS=y\r\n> > +CONFIG_DFU_MMC=y\r\n> >  CONFIG_FPGA_SOCFPGA=y\r\n> >  CONFIG_DM_GPIO=y\r\n> >  CONFIG_DWAPB_GPIO=y\r\n> >  CONFIG_DM_MMC=y\r\n> > +CONFIG_MMC_DW=y\r\n> > +CONFIG_SPI_FLASH=y\r\n> > +CONFIG_SPI_FLASH_BAR=y\r\n> > +CONFIG_SPI_FLASH_SPANSION=y\r\n> > +CONFIG_SPI_FLASH_STMICRO=y\r\n> > +CONFIG_DM_ETH=y\r\n> > +CONFIG_ETH_DESIGNWARE=y\r\n> >  CONFIG_SYS_NS16550=y\r\n> >  CONFIG_USE_TINY_PRINTF=y\r\n> > +CONFIG_CMD_FPGA_LOADFS=y\r\n> > +CONFIG_CADENCE_QSPI=y\r\n> > +CONFIG_DESIGNWARE_SPI=y\r\n> > +CONFIG_USB=y\r\n> > +CONFIG_DM_USB=y\r\n> > +CONFIG_USB_STORAGE=y\r\n> > +CONFIG_USB_GADGET=y\r\n> > +CONFIG_USB_GADGET_DWC2_OTG=y\r\n> > +CONFIG_USB_GADGET_DOWNLOAD=y\r\n> > +CONFIG_G_DNL_MANUFACTURER=\"altera\"\r\n> > +CONFIG_G_DNL_VENDOR_NUM=0x0525\r\n> > +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\r\n> > +CONFIG_USE_TINY_PRINTF=y\r\n> > +CONFIG_SPL_MMC_SUPPORT=y\r\n> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\r\n> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800\r\n> > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y\r\n> > diff --git a/include/spl.h b/include/spl.h\r\n> > index ce4cf0a..e24433d 100644\r\n> > --- a/include/spl.h\r\n> > +++ b/include/spl.h\r\n> > @@ -10,6 +10,7 @@\r\n> >  /* Platform-specific defines */\r\n> >  #include \r\n> >  #include \r\n> > +#include \r\n> >  \r\n> >  /* Value in r0 indicates we booted from U-Boot */\r\n> >  #define UBOOT_NOT_LOADED_FROM_SPL\t0x13578642\r\n> > @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info\r\n> > *spl_image,\r\n> >  void preloader_console_init(void);\r\n> >  u32 spl_boot_device(void);\r\n> >  u32 spl_boot_mode(const u32 boot_device);\r\n> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);\r\n> >  \r\n> >  /**\r\n> >   * spl_set_header_raw_uboot() - Set up a standard SPL image\r\n> > structure\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1Sj309ktz9t1t\n\tfor ;\n\tTue, 26 Sep 2017 14:32:05 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 008B6C21F40; Tue, 26 Sep 2017 04:32:00 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 1DBD7C21D5B;\n\tTue, 26 Sep 2017 04:31:57 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A1050C21D5B; Tue, 26 Sep 2017 04:31:55 +0000 (UTC)","from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby lists.denx.de (Postfix) with ESMTPS id 802A3C21CA5\n\tfor ; Tue, 26 Sep 2017 04:31:54 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga104.jf.intel.com with ESMTP; 25 Sep 2017 21:31:52 -0700","from kmsmsx154.gar.corp.intel.com ([172.21.73.14])\n\tby fmsmga002.fm.intel.com with ESMTP; 25 Sep 2017 21:31:50 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX154.gar.corp.intel.com ([169.254.12.132]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 12:31:49 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,439,1500966000\"; d=\"scan'208\";\n\ta=\"1223718458\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to\n\tDDR and booting U-boot","Thread-Index":"AQHTNdoOc0wR75IC/EqskDfckQHF56LEzleAgAFAlAA=","Date":"Tue, 26 Sep 2017 04:31:48 +0000","Message-ID":"<1506400308.27760.3.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>\n\t<3186f594-ba7c-a36f-3baf-b4e524499cf6@denx.de>","In-Reply-To":"<3186f594-ba7c-a36f-3baf-b4e524499cf6@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<6928566E85A9474983ED75F78AF9E05F@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775378,"web_url":"http://patchwork.ozlabs.org/comment/1775378/","msgid":"","list_archive_url":null,"date":"2017-09-26T10:38:36","subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.\n>> This patch seems to be doing more than just one thing ...\n>>\n> I can split into two patches:\n> 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to DDR\n> 2) Setting up configs so SPL can boot U-boot from FAT.\n\nSplit it so that one patch does one thing.\n\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>>> ---\n>>>  arch/arm/mach-socfpga/spl.c       | 55\n>>> +++++++++++++++++++++++++++++++++++++\n>>>  common/spl/spl_mmc.c              |  2 +-\n>>>  configs/socfpga_arria10_defconfig | 57\n>>> ++++++++++++++++++++++++++++++++++-----\n>>>  include/spl.h                     |  2 ++\n>>>  4 files changed, 108 insertions(+), 8 deletions(-)\n>>>\n>>> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-\n>>> socfpga/spl.c\n>>> index aba116d..9b381bb 100644\n>>> --- a/arch/arm/mach-socfpga/spl.c\n>>> +++ b/arch/arm/mach-socfpga/spl.c\n>>> @@ -15,6 +15,7 @@\n>>>  #include \n>>>  #include \n>>>  #include \n>>> +#include \n>>>  #include \n>>>  #include \n>>>  #include \n>>> @@ -22,6 +23,10 @@\n>>>  #include \n>>>  #include \n>>>  #include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>>  #include \n>>>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>>  #include \n>>> @@ -29,6 +34,9 @@\n>>>  \n>>>  DECLARE_GLOBAL_DATA_PTR;\n>>>  \n>>> +#define BSIZE\t4096\n>>> +#define PERIPH_RBF\t0\n>>> +\n>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n>>>  static struct pl310_regs *const pl310 =\n>>>  \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n>>> @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)\n>>>  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n>>>  void spl_board_init(void)\n>>>  {\n>>> +\tint rval = 0;\n>>> +\tint len = 0;\n>>> +\tu32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);\n>>> +\tstruct spl_boot_device bootdev;\n>>> +\tfpga_fs_info fpga_fsinfo;\n>>> +\n>>>  \t/* configuring the clock based on handoff */\n>>>  \tcm_basic_init(gd->fdt_blob);\n>>>  \tWATCHDOG_RESET();\n>>> @@ -214,6 +228,47 @@ void spl_board_init(void)\n>>>  \n>>>  \t/* Add device descriptor to FPGA device table */\n>>>  \tsocfpga_fpga_add();\n>>> +\n>>> +\tbootdev.boot_device = spl_boot_device();\n>>> +\n>>> +\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\n>>> +\t\tstruct mmc *mmc = NULL;\n>>> +\t\tint err = 0;\n>>> +\n>>> +\t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\n>>> +\n>>> +\t\terr = mmc_init(mmc);\n>>> +\n>>> +\t\tif (err) {\n>>> +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\n>>> +\t\t\tprintf(\"spl: mmc init failed with error:\n>>> %d\\n\", err);\n>>> +#endif\n>>> +\t\t}\n>>> +\n>>> +\t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-\n>>>> fdt_blob,\n>>> +\t\t\t\t\t\t\t\t &\n>>> len);\n>>> +\n>>> +\t\tfpga_fsinfo.filename = (char\n>>> *)get_cff_filename(gd->fdt_blob,\n>>> +\t\t\t\t\t\t\t\t &\n>>> len,\n>>> +\t\t\t\t\t\t\t\tPE\n>>> RIPH_RBF);\n>>> +\n>>> +\t\tfpga_fsinfo.interface = \"mmc\";\n>>> +\n>>> +\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\n>>> +\t} else {\n>>> +\t\tprintf(\"Invalid boot device!\\n\");\n>>> +\t\treturn;\n>>> +\t}\n>>> +\n>>> +\t/* Program peripheral RBF */\n>>> +\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len >\n>>> 0))\n>>> +\t\trval = fpga_fsload(0, buffer, BSIZE,\n>>> &fpga_fsinfo);\n>>> +\n>>> +\tif (rval > 0) {\n>>> +\t\tconfig_pins(gd->fdt_blob, \"shared\");\n>>> +\n>>> +\t\tddr_calibration_sequence();\n>>> +\t}\n>>>  }\n>>>  \n>>>  void board_init_f(ulong dummy)\n>>> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c\n>>> index b2cccc6..159443f 100644\n>>> --- a/common/spl/spl_mmc.c\n>>> +++ b/common/spl/spl_mmc.c\n>>> @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32\n>>> boot_device)\n>>>  \treturn -ENODEV;\n>>>  }\n>>>  \n>>> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n>>> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n>>>  {\n>>>  #if CONFIG_IS_ENABLED(DM_MMC)\n>>>  \tstruct udevice *dev;\n>>> diff --git a/configs/socfpga_arria10_defconfig\n>>> b/configs/socfpga_arria10_defconfig\n>>> index 4c73d73..2ff9801 100644\n>>> --- a/configs/socfpga_arria10_defconfig\n>>> +++ b/configs/socfpga_arria10_defconfig\n>>> @@ -2,33 +2,76 @@ CONFIG_ARM=y\n>>>  CONFIG_ARCH_SOCFPGA=y\n>>>  CONFIG_SYS_MALLOC_F_LEN=0x2000\n>>>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y\n>>> +CONFIG_SPL_STACK_R_ADDR=0x00800000\n>>>  CONFIG_IDENT_STRING=\"socfpga_arria10\"\n>>>  CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\n>>> -CONFIG_USE_BOOTARGS=y\n>>> -CONFIG_BOOTARGS=\"console=ttyS0,115200\"\n>>>  CONFIG_DEFAULT_FDT_FILE=\"socfpga_arria10_socdk_sdmmc.dtb\"\n>>> +CONFIG_FIT=y\n>>> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n>>> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y\n>>> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y\n>>> +CONFIG_SPL_ENV_SUPPORT=y\n>>> +CONFIG_VERSION_VARIABLE=y\n>>>  CONFIG_SPL=y\n>>> +CONFIG_HUSH_PARSER=y\n>>>  CONFIG_SPL_FPGA_SUPPORT=y\n>>> +CONFIG_SPL_FAT_SUPPORT=y\n>>> +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768\n>>>  CONFIG_CMD_BOOTZ=y\n>>>  # CONFIG_CMD_IMLS is not set\n>>>  CONFIG_CMD_ASKENV=y\n>>>  CONFIG_CMD_GREPENV=y\n>>>  # CONFIG_CMD_FLASH is not set\n>>> -CONFIG_CMD_GPIO=y\n>>> +CONFIG_SPL_LIBDISK_SUPPORT=y\n>>> +CONFIG_CMD_PART=y\n>>>  CONFIG_CMD_MMC=y\n>>> +CONFIG_CMD_SF=y\n>>> +CONFIG_CMD_SPI=y\n>>> +CONFIG_CMD_I2C=y\n>>> +CONFIG_SYS_I2C_DW=y\n>>> +CONFIG_CMD_USB=y\n>>> +CONFIG_CMD_DFU=y\n>>> +CONFIG_CMD_USB_MASS_STORAGE=y\n>>> +CONFIG_CMD_GPIO=y\n>>> +CONFIG_CMD_MII=y\n>>>  CONFIG_CMD_DHCP=y\n>>>  CONFIG_CMD_PING=y\n>>>  CONFIG_CMD_CACHE=y\n>>> -CONFIG_CMD_EXT4=y\n>>> -CONFIG_CMD_EXT4_WRITE=y\n>>>  CONFIG_DOS_PARTITION=y\n>>> -# CONFIG_SPL_DOS_PARTITION is not set\n>>> -CONFIG_ENV_IS_IN_MMC=y\n>>> +CONFIG_SPL_DOS_PARTITION=y\n>>> +CONFIG_SPL_FS_GENERIC=y\n>>> +CONFIG_CMD_FAT=y\n>>> +CONFIG_CMD_FS_GENERIC=y\n>>>  CONFIG_SPL_DM=y\n>>>  CONFIG_SPL_DM_SEQ_ALIAS=y\n>>> +CONFIG_DFU_MMC=y\n>>>  CONFIG_FPGA_SOCFPGA=y\n>>>  CONFIG_DM_GPIO=y\n>>>  CONFIG_DWAPB_GPIO=y\n>>>  CONFIG_DM_MMC=y\n>>> +CONFIG_MMC_DW=y\n>>> +CONFIG_SPI_FLASH=y\n>>> +CONFIG_SPI_FLASH_BAR=y\n>>> +CONFIG_SPI_FLASH_SPANSION=y\n>>> +CONFIG_SPI_FLASH_STMICRO=y\n>>> +CONFIG_DM_ETH=y\n>>> +CONFIG_ETH_DESIGNWARE=y\n>>>  CONFIG_SYS_NS16550=y\n>>>  CONFIG_USE_TINY_PRINTF=y\n>>> +CONFIG_CMD_FPGA_LOADFS=y\n>>> +CONFIG_CADENCE_QSPI=y\n>>> +CONFIG_DESIGNWARE_SPI=y\n>>> +CONFIG_USB=y\n>>> +CONFIG_DM_USB=y\n>>> +CONFIG_USB_STORAGE=y\n>>> +CONFIG_USB_GADGET=y\n>>> +CONFIG_USB_GADGET_DWC2_OTG=y\n>>> +CONFIG_USB_GADGET_DOWNLOAD=y\n>>> +CONFIG_G_DNL_MANUFACTURER=\"altera\"\n>>> +CONFIG_G_DNL_VENDOR_NUM=0x0525\n>>> +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\n>>> +CONFIG_USE_TINY_PRINTF=y\n>>> +CONFIG_SPL_MMC_SUPPORT=y\n>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\n>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800\n>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y\n>>> diff --git a/include/spl.h b/include/spl.h\n>>> index ce4cf0a..e24433d 100644\n>>> --- a/include/spl.h\n>>> +++ b/include/spl.h\n>>> @@ -10,6 +10,7 @@\n>>>  /* Platform-specific defines */\n>>>  #include \n>>>  #include \n>>> +#include \n>>>  \n>>>  /* Value in r0 indicates we booted from U-Boot */\n>>>  #define UBOOT_NOT_LOADED_FROM_SPL\t0x13578642\n>>> @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info\n>>> *spl_image,\n>>>  void preloader_console_init(void);\n>>>  u32 spl_boot_device(void);\n>>>  u32 spl_boot_mode(const u32 boot_device);\n>>> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);\n>>>  \n>>>  /**\n>>>   * spl_set_header_raw_uboot() - Set up a standard SPL image\n>>> structure\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 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(dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id gj7lwtrF1Emh; Tue, 26 Sep 2017 13:07:40 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:40 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"edwop+gqXBsRqtCrpK9jopn+ztkhP97gLTnrRUm8UJA=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>\n\t<3186f594-ba7c-a36f-3baf-b4e524499cf6@denx.de>\n\t<1506400308.27760.3.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Tue, 26 Sep 2017 12:38:36 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506400308.27760.3.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776002,"web_url":"http://patchwork.ozlabs.org/comment/1776002/","msgid":"<1506482055.3589.6.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T03:14:17","subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:38 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.\r\n> > > This patch seems to be doing more than just one thing ...\r\n> > > \r\n> > I can split into two patches:\r\n> > 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to\r\n> > DDR\r\n> > 2) Setting up configs so SPL can boot U-boot from FAT.\r\n> Split it so that one patch does one thing.\r\n> \r\nOkay.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > > ---\r\n> > > >  arch/arm/mach-socfpga/spl.c       | 55\r\n> > > > +++++++++++++++++++++++++++++++++++++\r\n> > > >  common/spl/spl_mmc.c              |  2 +-\r\n> > > >  configs/socfpga_arria10_defconfig | 57\r\n> > > > ++++++++++++++++++++++++++++++++++-----\r\n> > > >  include/spl.h                     |  2 ++\r\n> > > >  4 files changed, 108 insertions(+), 8 deletions(-)\r\n> > > > \r\n> > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-\r\n> > > > socfpga/spl.c\r\n> > > > index aba116d..9b381bb 100644\r\n> > > > --- a/arch/arm/mach-socfpga/spl.c\r\n> > > > +++ b/arch/arm/mach-socfpga/spl.c\r\n> > > > @@ -15,6 +15,7 @@\r\n> > > >  #include \r\n> > > >  #include \r\n> > > >  #include \r\n> > > > +#include \r\n> > > >  #include \r\n> > > >  #include \r\n> > > >  #include \r\n> > > > @@ -22,6 +23,10 @@\r\n> > > >  #include \r\n> > > >  #include \r\n> > > >  #include \r\n> > > > +#include \r\n> > > > +#include \r\n> > > > +#include \r\n> > > > +#include \r\n> > > >  #include \r\n> > > >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > >  #include \r\n> > > > @@ -29,6 +34,9 @@\r\n> > > >  \r\n> > > >  DECLARE_GLOBAL_DATA_PTR;\r\n> > > >  \r\n> > > > +#define BSIZE\t4096\r\n> > > > +#define PERIPH_RBF\t0\r\n> > > > +\r\n> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> > > >  static struct pl310_regs *const pl310 =\r\n> > > >  \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\r\n> > > > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)\r\n> > > >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > > >  void spl_board_init(void)\r\n> > > >  {\r\n> > > > +\tint rval = 0;\r\n> > > > +\tint len = 0;\r\n> > > > +\tu32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);\r\n> > > > +\tstruct spl_boot_device bootdev;\r\n> > > > +\tfpga_fs_info fpga_fsinfo;\r\n> > > > +\r\n> > > >  \t/* configuring the clock based on handoff */\r\n> > > >  \tcm_basic_init(gd->fdt_blob);\r\n> > > >  \tWATCHDOG_RESET();\r\n> > > > @@ -214,6 +228,47 @@ void spl_board_init(void)\r\n> > > >  \r\n> > > >  \t/* Add device descriptor to FPGA device table */\r\n> > > >  \tsocfpga_fpga_add();\r\n> > > > +\r\n> > > > +\tbootdev.boot_device = spl_boot_device();\r\n> > > > +\r\n> > > > +\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\r\n> > > > +\t\tstruct mmc *mmc = NULL;\r\n> > > > +\t\tint err = 0;\r\n> > > > +\r\n> > > > +\t\tspl_mmc_find_device(&mmc,\r\n> > > > bootdev.boot_device);\r\n> > > > +\r\n> > > > +\t\terr = mmc_init(mmc);\r\n> > > > +\r\n> > > > +\t\tif (err) {\r\n> > > > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\r\n> > > > +\t\t\tprintf(\"spl: mmc init failed with\r\n> > > > error:\r\n> > > > %d\\n\", err);\r\n> > > > +#endif\r\n> > > > +\t\t}\r\n> > > > +\r\n> > > > +\t\tfpga_fsinfo.dev_part = (char\r\n> > > > *)get_cff_devpart(gd-\r\n> > > > > \r\n> > > > > fdt_blob,\r\n> > > > +\t\t\t\t\t\t\t\t\r\n> > > >  &\r\n> > > > len);\r\n> > > > +\r\n> > > > +\t\tfpga_fsinfo.filename = (char\r\n> > > > *)get_cff_filename(gd->fdt_blob,\r\n> > > > +\t\t\t\t\t\t\t\t\r\n> > > >  &\r\n> > > > len,\r\n> > > > +\t\t\t\t\t\t\t\t\r\n> > > > PE\r\n> > > > RIPH_RBF);\r\n> > > > +\r\n> > > > +\t\tfpga_fsinfo.interface = \"mmc\";\r\n> > > > +\r\n> > > > +\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\r\n> > > > +\t} else {\r\n> > > > +\t\tprintf(\"Invalid boot device!\\n\");\r\n> > > > +\t\treturn;\r\n> > > > +\t}\r\n> > > > +\r\n> > > > +\t/* Program peripheral RBF */\r\n> > > > +\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part &&\r\n> > > > (len >\r\n> > > > 0))\r\n> > > > +\t\trval = fpga_fsload(0, buffer, BSIZE,\r\n> > > > &fpga_fsinfo);\r\n> > > > +\r\n> > > > +\tif (rval > 0) {\r\n> > > > +\t\tconfig_pins(gd->fdt_blob, \"shared\");\r\n> > > > +\r\n> > > > +\t\tddr_calibration_sequence();\r\n> > > > +\t}\r\n> > > >  }\r\n> > > >  \r\n> > > >  void board_init_f(ulong dummy)\r\n> > > > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c\r\n> > > > index b2cccc6..159443f 100644\r\n> > > > --- a/common/spl/spl_mmc.c\r\n> > > > +++ b/common/spl/spl_mmc.c\r\n> > > > @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32\r\n> > > > boot_device)\r\n> > > >  \treturn -ENODEV;\r\n> > > >  }\r\n> > > >  \r\n> > > > -static int spl_mmc_find_device(struct mmc **mmcp, u32\r\n> > > > boot_device)\r\n> > > > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\r\n> > > >  {\r\n> > > >  #if CONFIG_IS_ENABLED(DM_MMC)\r\n> > > >  \tstruct udevice *dev;\r\n> > > > diff --git a/configs/socfpga_arria10_defconfig\r\n> > > > b/configs/socfpga_arria10_defconfig\r\n> > > > index 4c73d73..2ff9801 100644\r\n> > > > --- a/configs/socfpga_arria10_defconfig\r\n> > > > +++ b/configs/socfpga_arria10_defconfig\r\n> > > > @@ -2,33 +2,76 @@ CONFIG_ARM=y\r\n> > > >  CONFIG_ARCH_SOCFPGA=y\r\n> > > >  CONFIG_SYS_MALLOC_F_LEN=0x2000\r\n> > > >  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y\r\n> > > > +CONFIG_SPL_STACK_R_ADDR=0x00800000\r\n> > > >  CONFIG_IDENT_STRING=\"socfpga_arria10\"\r\n> > > >  CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\r\n> > > > -CONFIG_USE_BOOTARGS=y\r\n> > > > -CONFIG_BOOTARGS=\"console=ttyS0,115200\"\r\n> > > >  CONFIG_DEFAULT_FDT_FILE=\"socfpga_arria10_socdk_sdmmc.dtb\"\r\n> > > > +CONFIG_FIT=y\r\n> > > > +CONFIG_SYS_CONSOLE_IS_IN_ENV=y\r\n> > > > +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y\r\n> > > > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y\r\n> > > > +CONFIG_SPL_ENV_SUPPORT=y\r\n> > > > +CONFIG_VERSION_VARIABLE=y\r\n> > > >  CONFIG_SPL=y\r\n> > > > +CONFIG_HUSH_PARSER=y\r\n> > > >  CONFIG_SPL_FPGA_SUPPORT=y\r\n> > > > +CONFIG_SPL_FAT_SUPPORT=y\r\n> > > > +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768\r\n> > > >  CONFIG_CMD_BOOTZ=y\r\n> > > >  # CONFIG_CMD_IMLS is not set\r\n> > > >  CONFIG_CMD_ASKENV=y\r\n> > > >  CONFIG_CMD_GREPENV=y\r\n> > > >  # CONFIG_CMD_FLASH is not set\r\n> > > > -CONFIG_CMD_GPIO=y\r\n> > > > +CONFIG_SPL_LIBDISK_SUPPORT=y\r\n> > > > +CONFIG_CMD_PART=y\r\n> > > >  CONFIG_CMD_MMC=y\r\n> > > > +CONFIG_CMD_SF=y\r\n> > > > +CONFIG_CMD_SPI=y\r\n> > > > +CONFIG_CMD_I2C=y\r\n> > > > +CONFIG_SYS_I2C_DW=y\r\n> > > > +CONFIG_CMD_USB=y\r\n> > > > +CONFIG_CMD_DFU=y\r\n> > > > +CONFIG_CMD_USB_MASS_STORAGE=y\r\n> > > > +CONFIG_CMD_GPIO=y\r\n> > > > +CONFIG_CMD_MII=y\r\n> > > >  CONFIG_CMD_DHCP=y\r\n> > > >  CONFIG_CMD_PING=y\r\n> > > >  CONFIG_CMD_CACHE=y\r\n> > > > -CONFIG_CMD_EXT4=y\r\n> > > > -CONFIG_CMD_EXT4_WRITE=y\r\n> > > >  CONFIG_DOS_PARTITION=y\r\n> > > > -# CONFIG_SPL_DOS_PARTITION is not set\r\n> > > > -CONFIG_ENV_IS_IN_MMC=y\r\n> > > > +CONFIG_SPL_DOS_PARTITION=y\r\n> > > > +CONFIG_SPL_FS_GENERIC=y\r\n> > > > +CONFIG_CMD_FAT=y\r\n> > > > +CONFIG_CMD_FS_GENERIC=y\r\n> > > >  CONFIG_SPL_DM=y\r\n> > > >  CONFIG_SPL_DM_SEQ_ALIAS=y\r\n> > > > +CONFIG_DFU_MMC=y\r\n> > > >  CONFIG_FPGA_SOCFPGA=y\r\n> > > >  CONFIG_DM_GPIO=y\r\n> > > >  CONFIG_DWAPB_GPIO=y\r\n> > > >  CONFIG_DM_MMC=y\r\n> > > > +CONFIG_MMC_DW=y\r\n> > > > +CONFIG_SPI_FLASH=y\r\n> > > > +CONFIG_SPI_FLASH_BAR=y\r\n> > > > +CONFIG_SPI_FLASH_SPANSION=y\r\n> > > > +CONFIG_SPI_FLASH_STMICRO=y\r\n> > > > +CONFIG_DM_ETH=y\r\n> > > > +CONFIG_ETH_DESIGNWARE=y\r\n> > > >  CONFIG_SYS_NS16550=y\r\n> > > >  CONFIG_USE_TINY_PRINTF=y\r\n> > > > +CONFIG_CMD_FPGA_LOADFS=y\r\n> > > > +CONFIG_CADENCE_QSPI=y\r\n> > > > +CONFIG_DESIGNWARE_SPI=y\r\n> > > > +CONFIG_USB=y\r\n> > > > +CONFIG_DM_USB=y\r\n> > > > +CONFIG_USB_STORAGE=y\r\n> > > > +CONFIG_USB_GADGET=y\r\n> > > > +CONFIG_USB_GADGET_DWC2_OTG=y\r\n> > > > +CONFIG_USB_GADGET_DOWNLOAD=y\r\n> > > > +CONFIG_G_DNL_MANUFACTURER=\"altera\"\r\n> > > > +CONFIG_G_DNL_VENDOR_NUM=0x0525\r\n> > > > +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\r\n> > > > +CONFIG_USE_TINY_PRINTF=y\r\n> > > > +CONFIG_SPL_MMC_SUPPORT=y\r\n> > > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\r\n> > > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800\r\n> > > > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y\r\n> > > > diff --git a/include/spl.h b/include/spl.h\r\n> > > > index ce4cf0a..e24433d 100644\r\n> > > > --- a/include/spl.h\r\n> > > > +++ b/include/spl.h\r\n> > > > @@ -10,6 +10,7 @@\r\n> > > >  /* Platform-specific defines */\r\n> > > >  #include \r\n> > > >  #include \r\n> > > > +#include \r\n> > > >  \r\n> > > >  /* Value in r0 indicates we booted from U-Boot */\r\n> > > >  #define UBOOT_NOT_LOADED_FROM_SPL\t0x13578642\r\n> > > > @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info\r\n> > > > *spl_image,\r\n> > > >  void preloader_console_init(void);\r\n> > > >  u32 spl_boot_device(void);\r\n> > > >  u32 spl_boot_mode(const u32 boot_device);\r\n> > > > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);\r\n> > > >  \r\n> > > >  /**\r\n> > > >   * spl_set_header_raw_uboot() - Set up a standard SPL image\r\n> > > > structure\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y22x46n2Sz9sP1\n\tfor ;\n\tWed, 27 Sep 2017 13:14:32 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 883CEC21D19; Wed, 27 Sep 2017 03:14:30 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5A92FC21C45;\n\tWed, 27 Sep 2017 03:14:26 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 3110AC21C45; Wed, 27 Sep 2017 03:14:24 +0000 (UTC)","from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby lists.denx.de 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\"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to\n\tDDR and booting U-boot","Thread-Index":"AQHTNdoOc0wR75IC/EqskDfckQHF56LEzleAgAFAlACAAGZ7AIABFi+A","Date":"Wed, 27 Sep 2017 03:14:17 +0000","Message-ID":"<1506482055.3589.6.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>\n\t<3186f594-ba7c-a36f-3baf-b4e524499cf6@denx.de>\n\t<1506400308.27760.3.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<6C48BECADFAF3C40863D237F696BD103@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading\n\tU-boot to DDR and booting U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]