[{"id":1774603,"web_url":"http://patchwork.ozlabs.org/comment/1774603/","msgid":"","list_archive_url":null,"date":"2017-09-25T09:15:43","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Add function for both multiple DRAM bank and single DRAM bank size\n> initialization. This common functionality could be used by every single\n> SOCFPGA board.\n> \n> Signed-off-by: Tien Fong Chee \n\nI'd like TB on Gen5.\n\n> ---\n> arch/arm/mach-socfpga/board.c | 7 +++++++\n> include/configs/socfpga_common.h | 1 +\n> 2 files changed, 8 insertions(+)\n> \n> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c\n> index a41d089..965f9dc 100644\n> --- a/arch/arm/mach-socfpga/board.c\n> +++ b/arch/arm/mach-socfpga/board.c\n> @@ -29,6 +29,13 @@ int board_init(void)\n> \treturn 0;\n> }\n> \n> +int dram_init_banksize(void)\n> +{\n> +\tfdtdec_setup_memory_banksize();\n> +\n> +\treturn 0;\n> +}\n> +\n> #ifdef CONFIG_USB_GADGET\n> struct dwc2_plat_otg_data socfpga_otg_data = {\n> \t.usb_gusbcfg\t= 0x1417,\n> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\n> index eadce2d..7549ee8 100644\n> --- a/include/configs/socfpga_common.h\n> +++ b/include/configs/socfpga_common.h\n> @@ -47,6 +47,7 @@\n> \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n> \n> #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n> +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\n> #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\n> #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\n> #else\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:33 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:33 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"cHTXa4wK0VTHH7VQ6eK6Im6SHe5T3pDIT7HtGjI590Y=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Mon, 25 Sep 2017 11:15:43 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775243,"web_url":"http://patchwork.ozlabs.org/comment/1775243/","msgid":"<1506414054.27760.21.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T08:20:54","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Add function for both multiple DRAM bank and single DRAM bank size\r\n> > initialization. This common functionality could be used by every\r\n> > single\r\n> > SOCFPGA board.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> I'd like TB on Gen5.\r\n> \r\nWhat is TB?\r\n> > \r\n> > ---\r\n> >  arch/arm/mach-socfpga/board.c    | 7 +++++++\r\n> >  include/configs/socfpga_common.h | 1 +\r\n> >  2 files changed, 8 insertions(+)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > socfpga/board.c\r\n> > index a41d089..965f9dc 100644\r\n> > --- a/arch/arm/mach-socfpga/board.c\r\n> > +++ b/arch/arm/mach-socfpga/board.c\r\n> > @@ -29,6 +29,13 @@ int board_init(void)\r\n> >  \treturn 0;\r\n> >  }\r\n> >  \r\n> > +int dram_init_banksize(void)\r\n> > +{\r\n> > +\tfdtdec_setup_memory_banksize();\r\n> > +\r\n> > +\treturn 0;\r\n> > +}\r\n> > +\r\n> >  #ifdef CONFIG_USB_GADGET\r\n> >  struct dwc2_plat_otg_data socfpga_otg_data = {\r\n> >  \t.usb_gusbcfg\t= 0x1417,\r\n> > diff --git a/include/configs/socfpga_common.h\r\n> > b/include/configs/socfpga_common.h\r\n> > index eadce2d..7549ee8 100644\r\n> > --- a/include/configs/socfpga_common.h\r\n> > +++ b/include/configs/socfpga_common.h\r\n> > @@ -47,6 +47,7 @@\r\n> >  \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\r\n> >  \r\n> >  #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\r\n> > +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\r\n> >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\r\n> >  #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\r\n> >  #else\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 16:20:55 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,440,1500966000\"; d=\"scan'208\";\n\ta=\"1199072193\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","Thread-Index":"AQHTNdoC07UG1iEF2UOcYNwCBTO8i6LEy+mAgAGDBAA=","Date":"Tue, 26 Sep 2017 08:20:54 +0000","Message-ID":"<1506414054.27760.21.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775376,"web_url":"http://patchwork.ozlabs.org/comment/1775376/","msgid":"<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>","list_archive_url":null,"date":"2017-09-26T10:33:19","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Add function for both multiple DRAM bank and single DRAM bank size\n>>> initialization. This common functionality could be used by every\n>>> single\n>>> SOCFPGA board.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>> I'd like TB on Gen5.\n>>\n> What is TB?\n\nTested-by\n\n>>>\n>>> ---\n>>>  arch/arm/mach-socfpga/board.c    | 7 +++++++\n>>>  include/configs/socfpga_common.h | 1 +\n>>>  2 files changed, 8 insertions(+)\n>>>\n>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\n>>> socfpga/board.c\n>>> index a41d089..965f9dc 100644\n>>> --- a/arch/arm/mach-socfpga/board.c\n>>> +++ b/arch/arm/mach-socfpga/board.c\n>>> @@ -29,6 +29,13 @@ int board_init(void)\n>>>  \treturn 0;\n>>>  }\n>>>  \n>>> +int dram_init_banksize(void)\n>>> +{\n>>> +\tfdtdec_setup_memory_banksize();\n>>> +\n>>> +\treturn 0;\n>>> +}\n>>> +\n>>>  #ifdef CONFIG_USB_GADGET\n>>>  struct dwc2_plat_otg_data socfpga_otg_data = {\n>>>  \t.usb_gusbcfg\t= 0x1417,\n>>> diff --git a/include/configs/socfpga_common.h\n>>> b/include/configs/socfpga_common.h\n>>> index eadce2d..7549ee8 100644\n>>> --- a/include/configs/socfpga_common.h\n>>> +++ b/include/configs/socfpga_common.h\n>>> @@ -47,6 +47,7 @@\n>>>  \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n>>>  \n>>>  #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n>>> +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\n>>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\n>>>  #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\n>>>  #else\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 13:07:33 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:33 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"DBpBSIoiazg5H46JHtyZTrjGBE/GDuvZFmEmVU7s4mY=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506414054.27760.21.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>","Date":"Tue, 26 Sep 2017 12:33:19 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506414054.27760.21.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778229,"web_url":"http://patchwork.ozlabs.org/comment/1778229/","msgid":"<1506938492.2178.1.camel@intel.com>","list_archive_url":null,"date":"2017-10-02T10:01:33","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Add function for both multiple DRAM bank and single DRAM bank\r\n> > > > size\r\n> > > > initialization. This common functionality could be used by\r\n> > > > every\r\n> > > > single\r\n> > > > SOCFPGA board.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > I'd like TB on Gen5.\r\n> > > \r\n> > What is TB?\r\n> Tested-by\r\n> Tested-by: Tien Fong Chee \r\n\r\nYou want me resend the patch with Tested-by?\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > ---\r\n> > > >  arch/arm/mach-socfpga/board.c    | 7 +++++++\r\n> > > >  include/configs/socfpga_common.h | 1 +\r\n> > > >  2 files changed, 8 insertions(+)\r\n> > > > \r\n> > > > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > > > socfpga/board.c\r\n> > > > index a41d089..965f9dc 100644\r\n> > > > --- a/arch/arm/mach-socfpga/board.c\r\n> > > > +++ b/arch/arm/mach-socfpga/board.c\r\n> > > > @@ -29,6 +29,13 @@ int board_init(void)\r\n> > > >  \treturn 0;\r\n> > > >  }\r\n> > > >  \r\n> > > > +int dram_init_banksize(void)\r\n> > > > +{\r\n> > > > +\tfdtdec_setup_memory_banksize();\r\n> > > > +\r\n> > > > +\treturn 0;\r\n> > > > +}\r\n> > > > +\r\n> > > >  #ifdef CONFIG_USB_GADGET\r\n> > > >  struct dwc2_plat_otg_data socfpga_otg_data = {\r\n> > > >  \t.usb_gusbcfg\t= 0x1417,\r\n> > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > b/include/configs/socfpga_common.h\r\n> > > > index eadce2d..7549ee8 100644\r\n> > > > --- a/include/configs/socfpga_common.h\r\n> > > > +++ b/include/configs/socfpga_common.h\r\n> > > > @@ -47,6 +47,7 @@\r\n> > > >  \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\r\n> > > >  \r\n> > > >  #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\r\n> > > > +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\r\n> > > >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\r\n> > > >  #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\r\n> > > >  #else\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5Hkp4rFPz9t4X\n\tfor ;\n\tMon, 2 Oct 2017 21:01:53 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid A6739C21C29; Mon, 2 Oct 2017 10:01:44 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4A1C1C21C41;\n\tMon, 2 Oct 2017 10:01:42 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid BCE9DC21C41; Mon, 2 Oct 2017 10:01:40 +0000 (UTC)","from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby lists.denx.de (Postfix) with ESMTPS id D8D0AC21C29\n\tfor ; Mon, 2 Oct 2017 10:01:39 +0000 (UTC)","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Oct 2017 03:01:36 -0700","from kmsmsx154.gar.corp.intel.com ([172.21.73.14])\n\tby orsmga002.jf.intel.com with ESMTP; 02 Oct 2017 03:01:35 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX154.gar.corp.intel.com ([169.254.12.132]) with mapi id\n\t14.03.0319.002; Mon, 2 Oct 2017 18:01:33 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,468,1500966000\"; d=\"scan'208\";a=\"141671723\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","Thread-Index":"AQHTNdoC07UG1iEF2UOcYNwCBTO8i6LEy+mAgAGDBACAACT/gIAJZRwA","Date":"Mon, 2 Oct 2017 10:01:33 +0000","Message-ID":"<1506938492.2178.1.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506414054.27760.21.camel@intel.com>\n\t<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>","In-Reply-To":"<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.168]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778230,"web_url":"http://patchwork.ozlabs.org/comment/1778230/","msgid":"","list_archive_url":null,"date":"2017-10-02T10:04:10","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:\n>> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> Add function for both multiple DRAM bank and single DRAM bank\n>>>>> size\n>>>>> initialization. This common functionality could be used by\n>>>>> every\n>>>>> single\n>>>>> SOCFPGA board.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>>>> I'd like TB on Gen5.\n>>>>\n>>> What is TB?\n>> Tested-by\n>> Tested-by: Tien Fong Chee \n> \n> You want me resend the patch with Tested-by?\n\nUh no, that's not how TB works. You should get TB on your patches from\nsomeone else , not yourself .\n\n>>>\n>>>>\n>>>>>\n>>>>>\n>>>>> ---\n>>>>>  arch/arm/mach-socfpga/board.c    | 7 +++++++\n>>>>>  include/configs/socfpga_common.h | 1 +\n>>>>>  2 files changed, 8 insertions(+)\n>>>>>\n>>>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\n>>>>> socfpga/board.c\n>>>>> index a41d089..965f9dc 100644\n>>>>> --- a/arch/arm/mach-socfpga/board.c\n>>>>> +++ b/arch/arm/mach-socfpga/board.c\n>>>>> @@ -29,6 +29,13 @@ int board_init(void)\n>>>>>  \treturn 0;\n>>>>>  }\n>>>>>  \n>>>>> +int dram_init_banksize(void)\n>>>>> +{\n>>>>> +\tfdtdec_setup_memory_banksize();\n>>>>> +\n>>>>> +\treturn 0;\n>>>>> +}\n>>>>> +\n>>>>>  #ifdef CONFIG_USB_GADGET\n>>>>>  struct dwc2_plat_otg_data socfpga_otg_data = {\n>>>>>  \t.usb_gusbcfg\t= 0x1417,\n>>>>> diff --git a/include/configs/socfpga_common.h\n>>>>> b/include/configs/socfpga_common.h\n>>>>> index eadce2d..7549ee8 100644\n>>>>> --- a/include/configs/socfpga_common.h\n>>>>> +++ b/include/configs/socfpga_common.h\n>>>>> @@ -47,6 +47,7 @@\n>>>>>  \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n>>>>>  \n>>>>>  #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n>>>>> +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\n>>>>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\n>>>>>  #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\n>>>>>  #else\n>>>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 2 Oct 2017 12:04:11 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 2 Oct 2017 12:04:11 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"kSpOo/uDWHX1i6TUuNE8cempCVC7UxNk/P64a8rCl28=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506414054.27760.21.camel@intel.com>\n\t<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>\n\t<1506938492.2178.1.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Mon, 2 Oct 2017 12:04:10 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506938492.2178.1.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778233,"web_url":"http://patchwork.ozlabs.org/comment/1778233/","msgid":"<1506938810.2178.4.camel@intel.com>","list_archive_url":null,"date":"2017-10-02T10:06:51","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-10-02 at 12:04 +0200, Marek Vasut wrote:\r\n> On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > Add function for both multiple DRAM bank and single DRAM\r\n> > > > > > bank\r\n> > > > > > size\r\n> > > > > > initialization. This common functionality could be used by\r\n> > > > > > every\r\n> > > > > > single\r\n> > > > > > SOCFPGA board.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > > > I'd like TB on Gen5.\r\n> > > > > \r\n> > > > What is TB?\r\n> > > Tested-by\r\n> > > Tested-by: Tien Fong Chee \r\n> > You want me resend the patch with Tested-by?\r\n> Uh no, that's not how TB works. You should get TB on your patches\r\n> from\r\n> someone else , not yourself .\r\n> \r\noo...okay, i will ask ley foon help to verify.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > ---\r\n> > > > > >  arch/arm/mach-socfpga/board.c    | 7 +++++++\r\n> > > > > >  include/configs/socfpga_common.h | 1 +\r\n> > > > > >  2 files changed, 8 insertions(+)\r\n> > > > > > \r\n> > > > > > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-\r\n> > > > > > socfpga/board.c\r\n> > > > > > index a41d089..965f9dc 100644\r\n> > > > > > --- a/arch/arm/mach-socfpga/board.c\r\n> > > > > > +++ b/arch/arm/mach-socfpga/board.c\r\n> > > > > > @@ -29,6 +29,13 @@ int board_init(void)\r\n> > > > > >  \treturn 0;\r\n> > > > > >  }\r\n> > > > > >  \r\n> > > > > > +int dram_init_banksize(void)\r\n> > > > > > +{\r\n> > > > > > +\tfdtdec_setup_memory_banksize();\r\n> > > > > > +\r\n> > > > > > +\treturn 0;\r\n> > > > > > +}\r\n> > > > > > +\r\n> > > > > >  #ifdef CONFIG_USB_GADGET\r\n> > > > > >  struct dwc2_plat_otg_data socfpga_otg_data = {\r\n> > > > > >  \t.usb_gusbcfg\t= 0x1417,\r\n> > > > > > diff --git a/include/configs/socfpga_common.h\r\n> > > > > > b/include/configs/socfpga_common.h\r\n> > > > > > index eadce2d..7549ee8 100644\r\n> > > > > > --- a/include/configs/socfpga_common.h\r\n> > > > > > +++ b/include/configs/socfpga_common.h\r\n> > > > > > @@ -47,6 +47,7 @@\r\n> > > > > >  \t(CONFIG_SYS_INIT_RAM_ADDR +\r\n> > > > > > CONFIG_SYS_INIT_SP_OFFSET)\r\n> > > > > >  \r\n> > > > > >  #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\r\n> > > > > > +#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_\r\n> > > > > > SIZE\r\n> > > > > >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\r\n> > > > > >  #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\r\n> > > > > >  #else\r\n> > > > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5Hrw2ZhPz9t4X\n\tfor ;\n\tMon, 2 Oct 2017 21:07:12 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 1BD0CC21E16; Mon, 2 Oct 2017 10:07:01 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 7F42AC21CB3;\n\tMon, 2 Oct 2017 10:06:59 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 2AFD4C21CB3; Mon, 2 Oct 2017 10:06:57 +0000 (UTC)","from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby lists.denx.de (Postfix) with ESMTPS id 26BE7C21C29\n\tfor ; Mon, 2 Oct 2017 10:06:55 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Oct 2017 03:06:54 -0700","from pgsmsx103.gar.corp.intel.com ([10.221.44.82])\n\tby fmsmga002.fm.intel.com with ESMTP; 02 Oct 2017 03:06:53 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX103.gar.corp.intel.com ([169.254.2.203]) with mapi id\n\t14.03.0319.002; Mon, 2 Oct 2017 18:06:52 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,468,1500966000\"; d=\"scan'208\";\n\ta=\"1225981936\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","Thread-Index":"AQHTNdoC07UG1iEF2UOcYNwCBTO8i6LEy+mAgAGDBACAACT/gIAJZRwAgAAAvACAAAC/AA==","Date":"Mon, 2 Oct 2017 10:06:51 +0000","Message-ID":"<1506938810.2178.4.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506414054.27760.21.camel@intel.com>\n\t<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>\n\t<1506938492.2178.1.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.168]","Content-ID":"<32502138CED9754DBBD754FE7563ACBC@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1778714,"web_url":"http://patchwork.ozlabs.org/comment/1778714/","msgid":"","list_archive_url":null,"date":"2017-10-03T03:30:46","subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","submitter":{"id":64658,"url":"http://patchwork.ozlabs.org/api/people/64658/","name":"Ley Foon Tan","email":"lftan.linux@gmail.com"},"content":"On Mon, Oct 2, 2017 at 6:06 PM, Chee, Tien Fong\n wrote:\n> On Isn, 2017-10-02 at 12:04 +0200, Marek Vasut wrote:\n>> On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:\n>> >\n>> > On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:\n>> > >\n>> > > On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:\n>> > > >\n>> > > >\n>> > > > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:\n>> > > > >\n>> > > > >\n>> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>> > > > > >\n>> > > > > >\n>> > > > > >\n>> > > > > > From: Tien Fong Chee \n>> > > > > >\n>> > > > > > Add function for both multiple DRAM bank and single DRAM\n>> > > > > > bank\n>> > > > > > size\n>> > > > > > initialization. This common functionality could be used by\n>> > > > > > every\n>> > > > > > single\n>> > > > > > SOCFPGA board.\n>> > > > > >\n>> > > > > > Signed-off-by: Tien Fong Chee \n>> > > > > I'd like TB on Gen5.\n>> > > > >\n>> > > > What is TB?\n>> > > Tested-by\n>> > > Tested-by: Tien Fong Chee \n>> > You want me resend the patch with Tested-by?\n>> Uh no, that's not how TB works. You should get TB on your patches\n>> from\n>> someone else , not yourself .\n>>\n> oo...okay, i will ask ley foon help to verify.\n>> >\nTested-by: Ley Foon Tan ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"b4pFMJOr\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5l1H6mjQz9t39\n\tfor ;\n\tTue, 3 Oct 2017 14:30:59 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 9DB9CC21F40; Tue, 3 Oct 2017 03:30:55 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3F9E3C21C46;\n\tTue, 3 Oct 2017 03:30:51 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 6973BC21C46; Tue, 3 Oct 2017 03:30:49 +0000 (UTC)","from mail-it0-f46.google.com (mail-it0-f46.google.com\n\t[209.85.214.46])\n\tby lists.denx.de (Postfix) with ESMTPS id 83FA7C21C40\n\tfor ; Tue, 3 Oct 2017 03:30:48 +0000 (UTC)","by mail-it0-f46.google.com with SMTP id 85so9768894ith.2\n\tfor ; Mon, 02 Oct 2017 20:30:48 -0700 (PDT)","by 10.107.10.135 with HTTP; Mon, 2 Oct 2017 20:30:46 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=qjUBhS1e8+JQjr7ELJGM3wLOq8Ol7vnJoLc1x7PL2nA=;\n\tb=b4pFMJOr4RxxRGsiTWrohI3WBP5h08gXSfpz8Ryh3RaeuQyYGE53XA3eg1JSFTYYCM\n\tU54f3u6Yolub0mXOaEcuAwCD5kb+RhazVicIlY8tLKgfZSQnOWcdqTVb2m9TnJ9Uz3Ne\n\tDVCxdiUTXhnqfCGvonDq6ynn3rx94LCDMpFc5wFn+RthqQ5uvQBNbjND9BOX2IDKekX6\n\t4n92eCmzJu0nCs8rdm7Git33l4KtWhykSv7Uz1E528PqekDI7lXfaYU7vfEvSaVIDC8L\n\tymp+Ifd7KyM/KeMg++KtjTiAwBoPnTFE19mQe3gBfcjh8u4r2WByStC0wRj0njEs9afd\n\twGWA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=qjUBhS1e8+JQjr7ELJGM3wLOq8Ol7vnJoLc1x7PL2nA=;\n\tb=tLJseze8IJvmdYKr71Z/pBATXEMtbjCn4cZFOgPj55JaXKE5sSrbBKX8rUp7x2fCTW\n\tOMEJMHPfZXzSsU203mv4T0Bm1tDU6FFLRJWgTD/CHhjaBWA9eCKgv4ZC5/9WH6oq5VvY\n\tMHjDWRTf0WRr2hRc62cD0nFwxSTJ/elXyt7VDiJYg19rUdvvBXWatTtUGajuNUlqF7+j\n\teRZui0xwjlkDJlCwhAV7GD61+i2Zr9jMZbANdUPT3y+/z3kPtTbcQv2pE2J+lGlqZ7zk\n\tMT2J4kNcxFyCVqppT3Nd5qb2ajoC7qMoBSJwwp+lIPk0AlYjFAp629/DTmSUq592WmZL\n\tsDjg==","X-Gm-Message-State":"AMCzsaVQNtyGSFizKqYCHHf541JCUOgSgNTwcCi9HSp71MoQxbeiRH6A\n\tKKYH88tJTXwvyNr1jWnBgrVF0bObrelKDoaaP6U=","X-Google-Smtp-Source":"AOwi7QATJUYNAIA4CytzO5ewhNDfFpAbFXzXowI2h7buXtB8+OZhR/nqy2oKmXskVEoiDjEBic2rTdU0PclQ8gZ4ePU=","X-Received":"by 10.36.117.150 with SMTP id y144mr23159344itc.60.1507001447123;\n\tMon, 02 Oct 2017 20:30:47 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506938810.2178.4.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>\n\t\n\t<1506414054.27760.21.camel@intel.com>\n\t<85db4eba-8f9b-8a82-471c-3f7ed4a85836@denx.de>\n\t<1506938492.2178.1.camel@intel.com>\n\t\n\t<1506938810.2178.4.camel@intel.com>","From":"Ley Foon Tan ","Date":"Tue, 3 Oct 2017 11:30:46 +0800","Message-ID":"","To":"\"Chee, Tien Fong\" ","Cc":"\"marex@denx.de\" ,\n\t\"u-boot@lists.denx.de\" , \"See,\n\tChin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]