[{"id":1774594,"web_url":"http://patchwork.ozlabs.org/comment/1774594/","msgid":"<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>","list_archive_url":null,"date":"2017-09-25T09:00:26","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> This patch adds description on properties about location of FPGA RBFs are\n> stored, type and functionality of RBF used to configure FPGA.\n> \n> Signed-off-by: Tien Fong Chee \n\nWhy does this patch have different tags than 1/19 ? Please keep things\nconsistent ...\n\n> ---\n> doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++\n> 1 file changed, 11 insertions(+)\n> \n> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> index 2fd8e7a..7abb746 100644\n> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> @@ -7,6 +7,14 @@ Required properties:\n> - The second index is for writing FPGA configuration data.\n> - resets : Phandle and reset specifier for the device's reset.\n> - clocks : Clocks used by the device.\n> +- bitstream_periph : FPGA peripheral raw binary file which is used to\n> + initialize FPGA IOs, PLL, IO48 and DDR.\n> +- bitstream_core : FPGA core raw binary file contains FPGA design which is used\n> + to program FPGA CRAM and ERAM.\n> +- bitstream_devpart : Partition of flash device where bitstream files are\n> +\t\t stored.\n> + - dev is flash device number, part is flash\n> + device partition.\n> \n> Example:\n> \n> @@ -16,4 +24,7 @@ Example:\n> \t\t 0xffcfe400 0x20>;\n> \t\tclocks = <&l4_mp_clk>;\n> \t\tresets = <&rst FPGAMGR_RESET>;\n> +\t\tbitstream_periph = \"ghrd_10as066n2.periph.rbf.mkimage\";\n> +\t\tbitstream_core = \"ghrd_10as066n2.core.rbf.mkimage\";\n> +\t\tbitstream_devpart = \"0:1\";\n> \t};\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:20 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:19 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"SiSprD4DJE4lXt4blcjNXvMYOJlrk3rtb1Ny4VXI/aA=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>","Date":"Mon, 25 Sep 2017 11:00:26 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1774595,"web_url":"http://patchwork.ozlabs.org/comment/1774595/","msgid":"<3d05adc6-6b1f-c80c-4e76-e645d90b3753@denx.de>","list_archive_url":null,"date":"2017-09-25T09:01:03","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> This patch adds description on properties about location of FPGA RBFs are\n> stored, type and functionality of RBF used to configure FPGA.\n> \n> Signed-off-by: Tien Fong Chee \n> ---\n> doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++\n> 1 file changed, 11 insertions(+)\n> \n> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> index 2fd8e7a..7abb746 100644\n> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> @@ -7,6 +7,14 @@ Required properties:\n> - The second index is for writing FPGA configuration data.\n> - resets : Phandle and reset specifier for the device's reset.\n> - clocks : Clocks used by the device.\n> +- bitstream_periph : FPGA peripheral raw binary file which is used to\n> + initialize FPGA IOs, PLL, IO48 and DDR.\n> +- bitstream_core : FPGA core raw binary file contains FPGA design which is used\n> + to program FPGA CRAM and ERAM.\n> +- bitstream_devpart : Partition of flash device where bitstream files are\n> +\t\t stored.\n> + - dev is flash device number, part is flash\n> + device partition.\n> \n> Example:\n> \n> @@ -16,4 +24,7 @@ Example:\n> \t\t 0xffcfe400 0x20>;\n> \t\tclocks = <&l4_mp_clk>;\n> \t\tresets = <&rst FPGAMGR_RESET>;\n> +\t\tbitstream_periph = \"ghrd_10as066n2.periph.rbf.mkimage\";\n> +\t\tbitstream_core = \"ghrd_10as066n2.core.rbf.mkimage\";\n> +\t\tbitstream_devpart = \"0:1\";\n\nThese should probably be altr,something-something ... they are\ndefinitely not generic bindings\n\n> \t};\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:21 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:21 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"urFks+s134QpBFKXUvicNb/IgXMtCFRWAb4nkh+C8zM=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"<3d05adc6-6b1f-c80c-4e76-e645d90b3753@denx.de>","Date":"Mon, 25 Sep 2017 11:01:03 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775260,"web_url":"http://patchwork.ozlabs.org/comment/1775260/","msgid":"<1506414763.27760.27.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T08:32:43","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:01 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > This patch adds description on properties about location of FPGA\r\n> > RBFs are\r\n> > stored, type and functionality of RBF used to configure FPGA.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> > ---\r\n> >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11\r\n> > +++++++++++\r\n> >  1 file changed, 11 insertions(+)\r\n> > \r\n> > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > mgr.txt\r\n> > index 2fd8e7a..7abb746 100644\r\n> > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\r\n> > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\r\n> > @@ -7,6 +7,14 @@ Required properties:\r\n> >                 - The second index is for writing FPGA\r\n> > configuration data.\r\n> >  - resets     : Phandle and reset specifier for the device's reset.\r\n> >  - clocks     : Clocks used by the device.\r\n> > +- bitstream_periph : FPGA peripheral raw binary file which is used\r\n> > to\r\n> > +                     initialize FPGA IOs, PLL, IO48 and DDR.\r\n> > +- bitstream_core : FPGA core raw binary file contains FPGA design\r\n> > which is used\r\n> > +                   to program FPGA CRAM and ERAM.\r\n> > +- bitstream_devpart : Partition of flash device where bitstream\r\n> > files are\r\n> > +\t\t       stored.\r\n> > +                       - dev is flash device number,\r\n> > part is flash\r\n> > +                                     device partition.\r\n> >  \r\n> >  Example:\r\n> >  \r\n> > @@ -16,4 +24,7 @@ Example:\r\n> >  \t\t       0xffcfe400 0x20>;\r\n> >  \t\tclocks = <&l4_mp_clk>;\r\n> >  \t\tresets = <&rst FPGAMGR_RESET>;\r\n> > +\t\tbitstream_periph =\r\n> > \"ghrd_10as066n2.periph.rbf.mkimage\";\r\n> > +\t\tbitstream_core =\r\n> > \"ghrd_10as066n2.core.rbf.mkimage\";\r\n> > +\t\tbitstream_devpart = \"0:1\";\r\n> These should probably be altr,something-something ... they are\r\n> definitely not generic bindings\r\n> \r\nOkay.\r\n> > \r\n> >  \t};\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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26 Sep 2017 01:32:46 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX102.gar.corp.intel.com ([169.254.6.144]) with mapi id\n\t14.03.0319.002; Tue, 26 Sep 2017 16:32:44 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,440,1500966000\"; d=\"scan'208\";a=\"316254862\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF\n\tproperties at Arria 10 FPGA manager","Thread-Index":"AQHTNdn6x2ydMdw3EEGwwEww2rldmaLEx9CAgAGKaoA=","Date":"Tue, 26 Sep 2017 08:32:43 +0000","Message-ID":"<1506414763.27760.27.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<3d05adc6-6b1f-c80c-4e76-e645d90b3753@denx.de>","In-Reply-To":"<3d05adc6-6b1f-c80c-4e76-e645d90b3753@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<3B03EA38A3C8F24B93F46FC52414703C@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775280,"web_url":"http://patchwork.ozlabs.org/comment/1775280/","msgid":"<1506416078.27760.30.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T08:54:38","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > This patch adds description on properties about location of FPGA\r\n> > RBFs are\r\n> > stored, type and functionality of RBF used to configure FPGA.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> Why does this patch have different tags than 1/19 ? Please keep\r\n> things\r\n> consistent ...\r\n> \r\nNot get you. What's you means for tags?\r\n> > \r\n> > ---\r\n> >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11\r\n> > +++++++++++\r\n> >  1 file changed, 11 insertions(+)\r\n> > \r\n> > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > mgr.txt\r\n> > index 2fd8e7a..7abb746 100644\r\n> > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\r\n> > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\r\n> > @@ -7,6 +7,14 @@ Required properties:\r\n> >                 - The second index is for writing FPGA\r\n> > configuration data.\r\n> >  - resets     : Phandle and reset specifier for the device's reset.\r\n> >  - clocks     : Clocks used by the device.\r\n> > +- bitstream_periph : FPGA peripheral raw binary file which is used\r\n> > to\r\n> > +                     initialize FPGA IOs, PLL, IO48 and DDR.\r\n> > +- bitstream_core : FPGA core raw binary file contains FPGA design\r\n> > which is used\r\n> > +                   to program FPGA CRAM and ERAM.\r\n> > +- bitstream_devpart : Partition of flash device where bitstream\r\n> > files are\r\n> > +\t\t       stored.\r\n> > +                       - dev is flash device number,\r\n> > part is flash\r\n> > +                                     device partition.\r\n> >  \r\n> >  Example:\r\n> >  \r\n> > @@ -16,4 +24,7 @@ Example:\r\n> >  \t\t       0xffcfe400 0x20>;\r\n> >  \t\tclocks = <&l4_mp_clk>;\r\n> >  \t\tresets = <&rst FPGAMGR_RESET>;\r\n> > +\t\tbitstream_periph =\r\n> > \"ghrd_10as066n2.periph.rbf.mkimage\";\r\n> > +\t\tbitstream_core =\r\n> > \"ghrd_10as066n2.core.rbf.mkimage\";\r\n> > +\t\tbitstream_devpart = \"0:1\";\r\n> >  \t};\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1ZXG5Jkgz9t6C\n\tfor ;\n\tTue, 26 Sep 2017 18:54:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid B320FC21ECE; Tue, 26 Sep 2017 08:54:50 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 825BAC21D5F;\n\tTue, 26 Sep 2017 08:54:47 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D1B31C21D5F; Tue, 26 Sep 2017 08:54:45 +0000 (UTC)","from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby lists.denx.de (Postfix) with ESMTPS id 34142C21C93\n\tfor ; Tue, 26 Sep 2017 08:54:44 +0000 (UTC)","from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga104.jf.intel.com with ESMTP; 26 Sep 2017 01:54:41 -0700","from kmsmsx154.gar.corp.intel.com ([172.21.73.14])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Sep 2017 01:54:39 -0700","from kmsmsx156.gar.corp.intel.com (172.21.138.133) by\n\tKMSMSX154.gar.corp.intel.com (172.21.73.14) with Microsoft SMTP\n\tServer (TLS) id 14.3.319.2; Tue, 26 Sep 2017 16:54:38 +0800","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tKMSMSX156.gar.corp.intel.com ([172.21.138.133]) with mapi id\n\t14.03.0248.002; Tue, 26 Sep 2017 16:54:38 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,440,1500966000\"; d=\"scan'208\";\n\ta=\"1018484157\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF\n\tproperties at Arria 10 FPGA manager","Thread-Index":"AQHTNdn6x2ydMdw3EEGwwEww2rldmaLEx6QAgAGQtgA=","Date":"Tue, 26 Sep 2017 08:54:38 +0000","Message-ID":"<1506416078.27760.30.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>","In-Reply-To":"<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<275E947F238C2A40B1079D6D21EB2AEB@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775370,"web_url":"http://patchwork.ozlabs.org/comment/1775370/","msgid":"<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>","list_archive_url":null,"date":"2017-09-26T10:30:27","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> This patch adds description on properties about location of FPGA\n>>> RBFs are\n>>> stored, type and functionality of RBF used to configure FPGA.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>> Why does this patch have different tags than 1/19 ? Please keep\n>> things\n>> consistent ...\n>>\n> Not get you. What's you means for tags?\n\nARM: socfpga: , not the random doc: dtbinding: .\nHeck, the first and second patch change the same file, yet have\ndifferent tags, why ?\n\n>>> ---\n>>>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11\n>>> +++++++++++\n>>>  1 file changed, 11 insertions(+)\n>>>\n>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\n>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\n>>> mgr.txt\n>>> index 2fd8e7a..7abb746 100644\n>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n>>> @@ -7,6 +7,14 @@ Required properties:\n>>>                 - The second index is for writing FPGA\n>>> configuration data.\n>>>  - resets     : Phandle and reset specifier for the device's reset.\n>>>  - clocks     : Clocks used by the device.\n>>> +- bitstream_periph : FPGA peripheral raw binary file which is used\n>>> to\n>>> +                     initialize FPGA IOs, PLL, IO48 and DDR.\n>>> +- bitstream_core : FPGA core raw binary file contains FPGA design\n>>> which is used\n>>> +                   to program FPGA CRAM and ERAM.\n>>> +- bitstream_devpart : Partition of flash device where bitstream\n>>> files are\n>>> +\t\t       stored.\n>>> +                       - dev is flash device number,\n>>> part is flash\n>>> +                                     device partition.\n>>>  \n>>>  Example:\n>>>  \n>>> @@ -16,4 +24,7 @@ Example:\n>>>  \t\t       0xffcfe400 0x20>;\n>>>  \t\tclocks = <&l4_mp_clk>;\n>>>  \t\tresets = <&rst FPGAMGR_RESET>;\n>>> +\t\tbitstream_periph =\n>>> \"ghrd_10as066n2.periph.rbf.mkimage\";\n>>> +\t\tbitstream_core =\n>>> \"ghrd_10as066n2.core.rbf.mkimage\";\n>>> +\t\tbitstream_devpart = \"0:1\";\n>>>  \t};\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 13:07:21 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:21 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"wrjH76ehuF6ikI6na0Dvr3fRB6pK5ESEOg8xb/7ZZ+A=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>\n\t<1506416078.27760.30.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>","Date":"Tue, 26 Sep 2017 12:30:27 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506416078.27760.30.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776000,"web_url":"http://patchwork.ozlabs.org/comment/1776000/","msgid":"<1506481952.3589.5.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T03:12:45","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > This patch adds description on properties about location of\r\n> > > > FPGA\r\n> > > > RBFs are\r\n> > > > stored, type and functionality of RBF used to configure FPGA.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > Why does this patch have different tags than 1/19 ? Please keep\r\n> > > things\r\n> > > consistent ...\r\n> > > \r\n> > Not get you. What's you means for tags?\r\n> ARM: socfpga: , not the random doc: dtbinding: .\r\n> Heck, the first and second patch change the same file, yet have\r\n> different tags, why ?\r\n> \r\nI ported patch 01 from Linux, so i keep everything intact. For patch\r\n02, i put doc:dtbinding because i think that is more descriptive to the\r\nfile i changed.\r\nI can change to ARM:socfpga .\r\n> > \r\n> > > \r\n> > > > \r\n> > > > ---\r\n> > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\r\n> > > > | 11\r\n> > > > +++++++++++\r\n> > > >  1 file changed, 11 insertions(+)\r\n> > > > \r\n> > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-\r\n> > > > fpga-\r\n> > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-\r\n> > > > fpga-\r\n> > > > mgr.txt\r\n> > > > index 2fd8e7a..7abb746 100644\r\n> > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > > > mgr.txt\r\n> > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > > > mgr.txt\r\n> > > > @@ -7,6 +7,14 @@ Required properties:\r\n> > > >                 - The second index is for writing FPGA\r\n> > > > configuration data.\r\n> > > >  - resets     : Phandle and reset specifier for the device's\r\n> > > > reset.\r\n> > > >  - clocks     : Clocks used by the device.\r\n> > > > +- bitstream_periph : FPGA peripheral raw binary file which is\r\n> > > > used\r\n> > > > to\r\n> > > > +                     initialize FPGA IOs, PLL, IO48 and DDR.\r\n> > > > +- bitstream_core : FPGA core raw binary file contains FPGA\r\n> > > > design\r\n> > > > which is used\r\n> > > > +                   to program FPGA CRAM and ERAM.\r\n> > > > +- bitstream_devpart : Partition of flash device where\r\n> > > > bitstream\r\n> > > > files are\r\n> > > > +\t\t       stored.\r\n> > > > +                       - dev is flash device\r\n> > > > number,\r\n> > > > part is flash\r\n> > > > +                                     device partition.\r\n> > > >  \r\n> > > >  Example:\r\n> > > >  \r\n> > > > @@ -16,4 +24,7 @@ Example:\r\n> > > >  \t\t       0xffcfe400 0x20>;\r\n> > > >  \t\tclocks = <&l4_mp_clk>;\r\n> > > >  \t\tresets = <&rst FPGAMGR_RESET>;\r\n> > > > +\t\tbitstream_periph =\r\n> > > > \"ghrd_10as066n2.periph.rbf.mkimage\";\r\n> > > > +\t\tbitstream_core =\r\n> > > > \"ghrd_10as066n2.core.rbf.mkimage\";\r\n> > > > +\t\tbitstream_devpart = \"0:1\";\r\n> > > >  \t};\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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26 Sep 2017 20:12:49 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX108.gar.corp.intel.com ([169.254.8.194]) with mapi id\n\t14.03.0319.002; Wed, 27 Sep 2017 11:12:47 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,442,1500966000\"; d=\"scan'208\";\n\ta=\"1176173273\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF\n\tproperties at Arria 10 FPGA manager","Thread-Index":"AQHTNdn6x2ydMdw3EEGwwEww2rldmaLEx6QAgAGQtgCAABrFgIABF/sA","Date":"Wed, 27 Sep 2017 03:12:45 +0000","Message-ID":"<1506481952.3589.5.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>\n\t<1506416078.27760.30.camel@intel.com>\n\t<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>","In-Reply-To":"<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<1063C031E1FF114E9E5E7E73BF7CE7A1@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776174,"web_url":"http://patchwork.ozlabs.org/comment/1776174/","msgid":"","list_archive_url":null,"date":"2017-09-27T08:29:03","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/27/2017 05:12 AM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:\n>> On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> This patch adds description on properties about location of\n>>>>> FPGA\n>>>>> RBFs are\n>>>>> stored, type and functionality of RBF used to configure FPGA.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>>>> Why does this patch have different tags than 1/19 ? Please keep\n>>>> things\n>>>> consistent ...\n>>>>\n>>> Not get you. What's you means for tags?\n>> ARM: socfpga: , not the random doc: dtbinding: .\n>> Heck, the first and second patch change the same file, yet have\n>> different tags, why ?\n>>\n> I ported patch 01 from Linux, so i keep everything intact. For patch\n> 02, i put doc:dtbinding because i think that is more descriptive to the\n> file i changed.\n> I can change to ARM:socfpga .\n\nThe tags are standardized ... inventing new random ones only messes\nthings up.\n\n>>>\n>>>>\n>>>>>\n>>>>> ---\n>>>>>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n>>>>> | 11\n>>>>> +++++++++++\n>>>>>  1 file changed, 11 insertions(+)\n>>>>>\n>>>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-\n>>>>> fpga-\n>>>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-\n>>>>> fpga-\n>>>>> mgr.txt\n>>>>> index 2fd8e7a..7abb746 100644\n>>>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\n>>>>> mgr.txt\n>>>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\n>>>>> mgr.txt\n>>>>> @@ -7,6 +7,14 @@ Required properties:\n>>>>>                 - The second index is for writing FPGA\n>>>>> configuration data.\n>>>>>  - resets     : Phandle and reset specifier for the device's\n>>>>> reset.\n>>>>>  - clocks     : Clocks used by the device.\n>>>>> +- bitstream_periph : FPGA peripheral raw binary file which is\n>>>>> used\n>>>>> to\n>>>>> +                     initialize FPGA IOs, PLL, IO48 and DDR.\n>>>>> +- bitstream_core : FPGA core raw binary file contains FPGA\n>>>>> design\n>>>>> which is used\n>>>>> +                   to program FPGA CRAM and ERAM.\n>>>>> +- bitstream_devpart : Partition of flash device where\n>>>>> bitstream\n>>>>> files are\n>>>>> +\t\t       stored.\n>>>>> +                       - dev is flash device\n>>>>> number,\n>>>>> part is flash\n>>>>> +                                     device partition.\n>>>>>  \n>>>>>  Example:\n>>>>>  \n>>>>> @@ -16,4 +24,7 @@ Example:\n>>>>>  \t\t       0xffcfe400 0x20>;\n>>>>>  \t\tclocks = <&l4_mp_clk>;\n>>>>>  \t\tresets = <&rst FPGAMGR_RESET>;\n>>>>> +\t\tbitstream_periph =\n>>>>> \"ghrd_10as066n2.periph.rbf.mkimage\";\n>>>>> +\t\tbitstream_core =\n>>>>> \"ghrd_10as066n2.core.rbf.mkimage\";\n>>>>> +\t\tbitstream_devpart = \"0:1\";\n>>>>>  \t};\n>>>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2C162mQqz9tXn\n\tfor ;\n\tWed, 27 Sep 2017 19:18:34 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0C31BC21E7F; Wed, 27 Sep 2017 09:18:32 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9A47FC21DA5;\n\tWed, 27 Sep 2017 08:59:38 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 1FB90C21DE7; Wed, 27 Sep 2017 08:59:36 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10])\n\tby lists.denx.de (Postfix) with ESMTPS id A9570C21CB1\n\tfor ; Wed, 27 Sep 2017 08:58:16 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3y2BYf5vrkz1qqkS;\n\tWed, 27 Sep 2017 10:58:14 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3y2BYf51XGz1qrmT;\n\tWed, 27 Sep 2017 10:58:14 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id XRAm2znloLWS; Wed, 27 Sep 2017 10:58:13 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tWed, 27 Sep 2017 10:58:13 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"5PBbXNs1TFUxofnEKC6JzseeIOl4NcVBj1DZVtIvzTM=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>\n\t<1506416078.27760.30.camel@intel.com>\n\t<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>\n\t<1506481952.3589.5.camel@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Wed, 27 Sep 2017 10:29:03 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506481952.3589.5.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776729,"web_url":"http://patchwork.ozlabs.org/comment/1776729/","msgid":"<1506566953.3589.41.camel@intel.com>","list_archive_url":null,"date":"2017-09-28T02:49:20","subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Rab, 2017-09-27 at 10:29 +0200, Marek Vasut wrote:\r\n> On 09/27/2017 05:12 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > This patch adds description on properties about location of\r\n> > > > > > FPGA\r\n> > > > > > RBFs are\r\n> > > > > > stored, type and functionality of RBF used to configure\r\n> > > > > > FPGA.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > > > Why does this patch have different tags than 1/19 ? Please\r\n> > > > > keep\r\n> > > > > things\r\n> > > > > consistent ...\r\n> > > > > \r\n> > > > Not get you. What's you means for tags?\r\n> > > ARM: socfpga: , not the random doc: dtbinding: .\r\n> > > Heck, the first and second patch change the same file, yet have\r\n> > > different tags, why ?\r\n> > > \r\n> > I ported patch 01 from Linux, so i keep everything intact. For\r\n> > patch\r\n> > 02, i put doc:dtbinding because i think that is more descriptive to\r\n> > the\r\n> > file i changed.\r\n> > I can change to ARM:socfpga .\r\n> The tags are standardized ... inventing new random ones only messes\r\n> things up.\r\n> \r\nOkay.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > ---\r\n> > > > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-\r\n> > > > > > mgr.txt\r\n> > > > > > > \r\n> > > > > > > 11\r\n> > > > > > +++++++++++\r\n> > > > > >  1 file changed, 11 insertions(+)\r\n> > > > > > \r\n> > > > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-\r\n> > > > > > a10-\r\n> > > > > > fpga-\r\n> > > > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-\r\n> > > > > > fpga-\r\n> > > > > > mgr.txt\r\n> > > > > > index 2fd8e7a..7abb746 100644\r\n> > > > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-\r\n> > > > > > fpga-\r\n> > > > > > mgr.txt\r\n> > > > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-\r\n> > > > > > fpga-\r\n> > > > > > mgr.txt\r\n> > > > > > @@ -7,6 +7,14 @@ Required properties:\r\n> > > > > >                 - The second index is for writing FPGA\r\n> > > > > > configuration data.\r\n> > > > > >  - resets     : Phandle and reset specifier for the\r\n> > > > > > device's\r\n> > > > > > reset.\r\n> > > > > >  - clocks     : Clocks used by the device.\r\n> > > > > > +- bitstream_periph : FPGA peripheral raw binary file which\r\n> > > > > > is\r\n> > > > > > used\r\n> > > > > > to\r\n> > > > > > +                     initialize FPGA IOs, PLL, IO48 and\r\n> > > > > > DDR.\r\n> > > > > > +- bitstream_core : FPGA core raw binary file contains FPGA\r\n> > > > > > design\r\n> > > > > > which is used\r\n> > > > > > +                   to program FPGA CRAM and ERAM.\r\n> > > > > > +- bitstream_devpart : Partition of flash device where\r\n> > > > > > bitstream\r\n> > > > > > files are\r\n> > > > > > +\t\t       stored.\r\n> > > > > > +                       - dev is flash device\r\n> > > > > > number,\r\n> > > > > > part is flash\r\n> > > > > > +                                     device partition.\r\n> > > > > >  \r\n> > > > > >  Example:\r\n> > > > > >  \r\n> > > > > > @@ -16,4 +24,7 @@ Example:\r\n> > > > > >  \t\t       0xffcfe400 0x20>;\r\n> > > > > >  \t\tclocks = <&l4_mp_clk>;\r\n> > > > > >  \t\tresets = <&rst FPGAMGR_RESET>;\r\n> > > > > > +\t\tbitstream_periph =\r\n> > > > > > \"ghrd_10as066n2.periph.rbf.mkimage\";\r\n> > > > > > +\t\tbitstream_core =\r\n> > > > > > \"ghrd_10as066n2.core.rbf.mkimage\";\r\n> > > > > > +\t\tbitstream_devpart = \"0:1\";\r\n> > > > > >  \t};\r\n> > > > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Thu, 28 Sep 2017 10:49:20 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,448,1500966000\"; d=\"scan'208\";a=\"317077115\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF\n\tproperties at Arria 10 FPGA manager","Thread-Index":"AQHTNdn6x2ydMdw3EEGwwEww2rldmaLEx6QAgAGQtgCAABrFgIABF/sAgABYb4CAATNigA==","Date":"Thu, 28 Sep 2017 02:49:20 +0000","Message-ID":"<1506566953.3589.41.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>\n\t<1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>\n\t<1506416078.27760.30.camel@intel.com>\n\t<4a1fe075-246c-36c7-c01b-5e0f0ba8432a@denx.de>\n\t<1506481952.3589.5.camel@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA\n\tRBF properties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; 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