[{"id":1774154,"web_url":"http://patchwork.ozlabs.org/comment/1774154/","msgid":"<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>","list_archive_url":null,"date":"2017-09-24T12:01:03","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 12:59 PM, Vignesh R wrote:\n> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n> switch on QSPI power domain on TI 66AK2G SoC during probe.\n> \n> Signed-off-by: Vignesh R \n\nAre you planning to add some more fine-grained PM control later?\n\n> ---\n> drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++\n> 1 file changed, 11 insertions(+)\n> \n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index d9629e8f4798..2c8e6226d267 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -31,6 +31,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)\n> \t\treturn -ENXIO;\n> \t}\n> \n> +\tpm_runtime_enable(&pdev->dev);\n> +\tret = pm_runtime_get_sync(&pdev->dev);\n> +\tif (ret < 0) {\n> +\t\tpm_runtime_put_noidle(&pdev->dev);\n> +\t\treturn ret;\n> +\t}\n> +\n> \tret = clk_prepare_enable(cqspi->clk);\n> \tif (ret) {\n> \t\tdev_err(dev, \"Cannot enable QSPI clock.\\n\");\n> @@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)\n> \n> \tclk_disable_unprepare(cqspi->clk);\n> \n> +\tpm_runtime_put_sync(&pdev->dev);\n> +\tpm_runtime_disable(&pdev->dev);\n> +\n> \treturn 0;\n> }\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170924105924.23923-6-vigneshr@ti.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_051218_670488_39A88A4C ","X-CRM114-Status":"GOOD ( 15.03 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:242 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774178,"web_url":"http://patchwork.ozlabs.org/comment/1774178/","msgid":"<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","list_archive_url":null,"date":"2017-09-24T13:08:23","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 5:31 PM, Marek Vasut wrote:\n> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>\n>> Signed-off-by: Vignesh R \n> \n> Are you planning to add some more fine-grained PM control later?\n\nYes, I will need to add fine-grained PM control at some point. But, for\nnow SoC does not really support low power mode or runtime power saving\noption.\nThe fact that driver still uses clk_prepare_*() calls to enable/disable\nclocks instead of pm_*() calls makes it a bit tricky though.\n\nJust figured out I forgot to add cleanup code in error handling path of\nprobe(). Will fix that and send a v4.\n\n> \n>> ---\n>> drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++\n>> 1 file changed, 11 insertions(+)\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index d9629e8f4798..2c8e6226d267 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -31,6 +31,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> #include \n>> #include \n>> #include \n>> @@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \t\treturn -ENXIO;\n>> \t}\n>> \n>> +\tpm_runtime_enable(&pdev->dev);\n>> +\tret = pm_runtime_get_sync(&pdev->dev);\n>> +\tif (ret < 0) {\n>> +\t\tpm_runtime_put_noidle(&pdev->dev);\n>> +\t\treturn ret;\n>> +\t}\n>> +\n>> \tret = clk_prepare_enable(cqspi->clk);\n>> \tif (ret) {\n>> \t\tdev_err(dev, \"Cannot enable QSPI clock.\\n\");\n>> @@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)\n>> \n>> \tclk_disable_unprepare(cqspi->clk);\n>> \n>> +\tpm_runtime_put_sync(&pdev->dev);\n>> +\tpm_runtime_disable(&pdev->dev);\n>> +\n>> \treturn 0;\n>> }\n>> \n>>\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>","Content-Language":"en-US","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_061021_419390_0A0DF451 ","X-CRM114-Status":"GOOD ( 10.63 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.16 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774182,"web_url":"http://patchwork.ozlabs.org/comment/1774182/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:12:37","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 03:08 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>\n>>> Signed-off-by: Vignesh R \n>>\n>> Are you planning to add some more fine-grained PM control later?\n> \n> Yes, I will need to add fine-grained PM control at some point. But, for\n> now SoC does not really support low power mode or runtime power saving\n> option.\n> The fact that driver still uses clk_prepare_*() calls to enable/disable\n> clocks instead of pm_*() calls makes it a bit tricky though.\n> \n> Just figured out I forgot to add cleanup code in error handling path of\n> probe(). Will fix that and send a v4.\n\nOK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\neither, so it's fine for now.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"ZUO/1AJI\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"fz6ka5JW\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0SMm6fZxz9sPs\n\tfor ;\n\tSun, 24 Sep 2017 23:13:40 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw6iw-00075S-VC; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_061301_646090_BE2C10D2 ","X-CRM114-Status":"GOOD ( 13.02 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:243 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774188,"web_url":"http://patchwork.ozlabs.org/comment/1774188/","msgid":"<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>","list_archive_url":null,"date":"2017-09-24T13:27:30","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 6:42 PM, Marek Vasut wrote:\n> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>\n>>>> Signed-off-by: Vignesh R \n>>>\n>>> Are you planning to add some more fine-grained PM control later?\n>>\n>> Yes, I will need to add fine-grained PM control at some point. But, for\n>> now SoC does not really support low power mode or runtime power saving\n>> option.\n>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>\n>> Just figured out I forgot to add cleanup code in error handling path of\n>> probe(). Will fix that and send a v4.\n> \n> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n> either, so it's fine for now.\n> \n\nOk thanks! Do you know if pm_runtime_get_sync() can enable clocks for\nQSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\nif its possible to get rid of clk_*() calls in favor of pm_*() calls.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"ea5/PyDH\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"wCnYb//M\";\n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0SjL36sGz9sRV\n\tfor ;\n\tSun, 24 Sep 2017 23:28:54 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw6xT-00015w-2B; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774198,"web_url":"http://patchwork.ozlabs.org/comment/1774198/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:51:55","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 03:27 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>\n>>>\n>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>\n>>>>> Signed-off-by: Vignesh R \n>>>>\n>>>> Are you planning to add some more fine-grained PM control later?\n>>>\n>>> Yes, I will need to add fine-grained PM control at some point. But, for\n>>> now SoC does not really support low power mode or runtime power saving\n>>> option.\n>>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>\n>>> Just figured out I forgot to add cleanup code in error handling path of\n>>> probe(). Will fix that and send a v4.\n>>\n>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>> either, so it's fine for now.\n>>\n> \n> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n\nNot of the top of my head, sorry. +CC Matthew, he should know.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Acq/H/M+\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pqU7tp/g\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0TFB5gQJz9sNV\n\tfor ;\n\tSun, 24 Sep 2017 23:53:02 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw7L2-0007tc-6o; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_065218_946625_18A0B9FE ","X-CRM114-Status":"GOOD ( 13.05 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c09:0:0:0:242 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tmatthew.gerlach@linux.intel.com,\n\tBrian Norris , \n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1775006,"web_url":"http://patchwork.ozlabs.org/comment/1775006/","msgid":"","list_archive_url":null,"date":"2017-09-25T22:41:40","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"content":"On Sun, 24 Sep 2017, Marek Vasut wrote:\n\n> On 09/24/2017 03:27 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>>\n>>>>\n>>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>>\n>>>>>> Signed-off-by: Vignesh R \n>>>>>\n>>>>> Are you planning to add some more fine-grained PM control later?\n>>>>\n>>>> Yes, I will need to add fine-grained PM control at some point. But, for\n>>>> now SoC does not really support low power mode or runtime power saving\n>>>> option.\n>>>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>>\n>>>> Just figured out I forgot to add cleanup code in error handling path of\n>>>> probe(). Will fix that and send a v4.\n>>>\n>>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>>> either, so it's fine for now.\n>>>\n>>\n>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>\n> Not of the top of my head, sorry. +CC Matthew, he should know.\n\nI am not an expert at the clock framework nor the power management, but I\ndid ask around a bit. No one I asked was planning to change the clk_*()\ncalls to pm_*() call, but the feedback was that it would be a good idea.\n\nMatthew Gerlach\n\n\n>\n> -- \n> Best regards,\n> Marek Vasut\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"DIAJpwv2\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1Jxb1lFmz9sRV\n\tfor ;\n\tTue, 26 Sep 2017 08:42:26 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwc4t-0007bo-VM; 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d=\"scan'208\";a=\"153240557\"","Date":"Mon, 25 Sep 2017 15:41:40 -0700 (PDT)","From":"matthew.gerlach@linux.intel.com","X-X-Sender":"mgerlach@mgerlach-VirtualBox","To":"Marek Vasut ","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","In-Reply-To":"","Message-ID":"","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_154210_192151_37372B3C ","X-CRM114-Status":"GOOD ( 13.04 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [134.134.136.65 listed in list.dnswl.org]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tVignesh R , devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Rob Herring ,\n\tlinux-mtd@lists.infradead.org,\n\tCyrille Pitchen , \n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1775058,"web_url":"http://patchwork.ozlabs.org/comment/1775058/","msgid":"","list_archive_url":null,"date":"2017-09-25T23:49:46","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/26/2017 12:41 AM, matthew.gerlach@linux.intel.com wrote:\n> \n> \n> On Sun, 24 Sep 2017, Marek Vasut wrote:\n> \n>> On 09/24/2017 03:27 PM, Vignesh R wrote:\n>>>\n>>>\n>>> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>>>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>>>\n>>>>>\n>>>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>>>\n>>>>>>> Signed-off-by: Vignesh R \n>>>>>>\n>>>>>> Are you planning to add some more fine-grained PM control later?\n>>>>>\n>>>>> Yes, I will need to add fine-grained PM control at some point. But,\n>>>>> for\n>>>>> now SoC does not really support low power mode or runtime power saving\n>>>>> option.\n>>>>> The fact that driver still uses clk_prepare_*() calls to\n>>>>> enable/disable\n>>>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>>>\n>>>>> Just figured out I forgot to add cleanup code in error handling\n>>>>> path of\n>>>>> probe(). Will fix that and send a v4.\n>>>>\n>>>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>>>> either, so it's fine for now.\n>>>>\n>>>\n>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>\n>> Not of the top of my head, sorry. +CC Matthew, he should know.\n> \n> I am not an expert at the clock framework nor the power management, but I\n> did ask around a bit.  No one I asked was planning to change the clk_*()\n> calls to pm_*() call, but the feedback was that it would be a good idea.\n\nThe question is, if we do the replacement, will it break on socfpga ?\nA quick test might be useful.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"HZ/hOf3R\"; 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\n\tMon, 25 Sep 2017 16:49:48 -0700 (PDT)","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"matthew.gerlach@linux.intel.com","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t\n\t","From":"Marek Vasut ","Message-ID":"","Date":"Tue, 26 Sep 2017 01:49:46 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_165010_909654_BA0E0A58 ","X-CRM114-Status":"GOOD ( 15.42 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c09:0:0:0:244 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tVignesh R , devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Rob Herring ,\n\tlinux-mtd@lists.infradead.org,\n\tCyrille Pitchen , \n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1776241,"web_url":"http://patchwork.ozlabs.org/comment/1776241/","msgid":"<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>","list_archive_url":null,"date":"2017-09-27T10:48:49","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"Hi Matthew,\n\nOn Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote:\n[...]\n>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>>\n>>> Not of the top of my head, sorry. +CC Matthew, he should know.\n>>\n>> I am not an expert at the clock framework nor the power management, but I\n>> did ask around a bit.  No one I asked was planning to change the clk_*()\n>> calls to pm_*() call, but the feedback was that it would be a good idea.\n> \n> The question is, if we do the replacement, will it break on socfpga ?\n> A quick test might be useful.\n> \n\nyes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls\nlike below patch would be helpful:\n\n\ndiff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\nindex 53c7d8e0327a..7ad3e176cc88 100644\n--- a/drivers/mtd/spi-nor/cadence-quadspi.c\n+++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n@@ -34,6 +34,7 @@\n #include \n #include \n #include \n+#include \n \n #define CQSPI_NAME \"cadence-qspi\"\n #define CQSPI_MAX_CHIPSELECT 16\n@@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev)\n return -ENXIO;\n }\n \n- ret = clk_prepare_enable(cqspi->clk);\n- if (ret) {\n- dev_err(dev, \"Cannot enable QSPI clock.\\n\");\n- return ret;\n- }\n+ pm_runtime_enable(dev);\n+ pm_runtime_get_sync(dev);\n \n cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-Spam-Note":"CRM114 invocation failed","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on merlin.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.27.77 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMarek Vasut , Rob Herring ,\n\tlinux-mtd@lists.infradead.org,\n\tCyrille Pitchen , \n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1777086,"web_url":"http://patchwork.ozlabs.org/comment/1777086/","msgid":"","list_archive_url":null,"date":"2017-09-28T15:01:36","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"content":"Hi Vignesh,\n\nI tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi \nkernel, and it did not go well. Commands to the flash chip timedout \nresulting in the probe function failing. I ran into other problems, not \nrelated to cadence-quadspi, that prevented me from testing against 4.9 and \n4.12 kernels, but I suspect similar behavior.\n\nMatthew Gerlach\n\nOn Wed, 27 Sep 2017, Vignesh R wrote:\n\n> Hi Matthew,\n>\n> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote:\n> [...]\n>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>>>\n>>>> Not of the top of my head, sorry. +CC Matthew, he should know.\n>>>\n>>> I am not an expert at the clock framework nor the power management, but I\n>>> did ask around a bit.  No one I asked was planning to change the clk_*()\n>>> calls to pm_*() call, but the feedback was that it would be a good idea.\n>>\n>> The question is, if we do the replacement, will it break on socfpga ?\n>> A quick test might be useful.\n>>\n>\n> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls\n> like below patch would be helpful:\n>\n>\n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index 53c7d8e0327a..7ad3e176cc88 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -34,6 +34,7 @@\n> #include \n> #include \n> #include \n> +#include \n>\n> #define CQSPI_NAME \"cadence-qspi\"\n> #define CQSPI_MAX_CHIPSELECT 16\n> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev)\n> return -ENXIO;\n> }\n>\n> - ret = clk_prepare_enable(cqspi->clk);\n> - if (ret) {\n> - dev_err(dev, \"Cannot enable QSPI clock.\\n\");\n> - return ret;\n> - }\n> + pm_runtime_enable(dev);\n> + pm_runtime_get_sync(dev);\n>\n> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>\n>\n>\n>\n>\n> -- \n> Regards\n> Vignesh\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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d=\"scan'208\";a=\"156599517\"","Date":"Thu, 28 Sep 2017 08:01:36 -0700 (PDT)","From":"matthew.gerlach@linux.intel.com","X-X-Sender":"mgerlach@mgerlach-VirtualBox","To":"Vignesh R ","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","In-Reply-To":"<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>","Message-ID":"","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t\n\t\n\t\n\t<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"multipart/mixed; BOUNDARY=\"8323329-1557128041-1506610898=:2488\"","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_080201_396552_49A2E8EC ","X-CRM114-Status":"GOOD ( 17.23 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.31 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMarek Vasut , Rob Herring ,\n\tlinux-mtd@lists.infradead.org,\n\tCyrille Pitchen , \n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1778289,"web_url":"http://patchwork.ozlabs.org/comment/1778289/","msgid":"<5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com>","list_archive_url":null,"date":"2017-10-02T12:28:55","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"Hi,\n\nOn 9/28/2017 8:31 PM, matthew.gerlach@linux.intel.com wrote:\n> \n> Hi Vignesh,\n> \n> I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi \n> kernel, and it did not go well. Commands to the flash chip timedout \n> resulting in the probe function failing. I ran into other problems, not \n> related to cadence-quadspi, that prevented me from testing against 4.9 and \n> 4.12 kernels, but I suspect similar behavior.\n> \n\nOk, thanks! I will keep the clk_*() calls for now.\n\nRegards\nVignesh\n> Matthew Gerlach\n> \n> On Wed, 27 Sep 2017, Vignesh R wrote:\n> \n>> Hi Matthew,\n>>\n>> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote:\n>> [...]\n>>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>>>>\n>>>>> Not of the top of my head, sorry. +CC Matthew, he should know.\n>>>>\n>>>> I am not an expert at the clock framework nor the power management, but I\n>>>> did ask around a bit.  No one I asked was planning to change the clk_*()\n>>>> calls to pm_*() call, but the feedback was that it would be a good idea.\n>>>\n>>> The question is, if we do the replacement, will it break on socfpga ?\n>>> A quick test might be useful.\n>>>\n>>\n>> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls\n>> like below patch would be helpful:\n>>\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index 53c7d8e0327a..7ad3e176cc88 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -34,6 +34,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>>\n>> #define CQSPI_NAME \"cadence-qspi\"\n>> #define CQSPI_MAX_CHIPSELECT 16\n>> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev)\n>> return -ENXIO;\n>> }\n>>\n>> - ret = clk_prepare_enable(cqspi->clk);\n>> - if (ret) {\n>> - dev_err(dev, \"Cannot enable QSPI clock.\\n\");\n>> - return ret;\n>> - }\n>> + pm_runtime_enable(dev);\n>> + pm_runtime_get_sync(dev);\n>>\n>> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>\n>>\n>>\n>>\n>>\n>> -- \n>> Regards\n>> Vignesh\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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