[{"id":1774155,"web_url":"http://patchwork.ozlabs.org/comment/1774155/","msgid":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","list_archive_url":null,"date":"2017-09-24T11:59:45","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 12:59 PM, Vignesh R wrote:\n> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n> Controller programming sequence, a delay equal to couple of QSPI master\n> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n> to handle this and set this flag for TI 66AK2G SoC.\n> \n> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n> \n> Signed-off-by: Vignesh R \n\nIs this TI specific or is this controller property ? I wouldn't be\nsurprised of the later ...\n\n> ---\n> \n> v3:\n> Fix build warnings reported by kbuild test bot.\n> \n> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n> 1 file changed, 26 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index 53c7d8e0327a..5cd5d6f7303f 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -38,6 +38,9 @@\n> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n> #define CQSPI_MAX_CHIPSELECT\t\t16\n> \n> +/* Quirks */\n> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n> +\n> struct cqspi_st;\n> \n> struct cqspi_flash_pdata {\n> @@ -76,6 +79,7 @@ struct cqspi_st {\n> \tu32\t\t\tfifo_depth;\n> \tu32\t\t\tfifo_width;\n> \tu32\t\t\ttrigger_address;\n> +\tu32\t\t\twr_delay;\n> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n> };\n> \n> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n> \treinit_completion(&cqspi->transfer_complete);\n> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n> \t reg_base + CQSPI_REG_INDIRECTWR);\n> +\t/*\n> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n> +\t * Controller programming sequence, couple of cycles of\n> +\t * QSPI_REF_CLK delay is required for the above bit to\n> +\t * be internally synchronized by the QSPI module. Provide 5\n> +\t * cycles of delay.\n> +\t */\n> +\tif (cqspi->wr_delay)\n> +\t\tndelay(cqspi->wr_delay);\n> \n> \twhile (remaining > 0) {\n> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n> \tstruct cqspi_st *cqspi;\n> \tstruct resource *res;\n> \tstruct resource *res_ahb;\n> +\tunsigned long data;\n> \tint ret;\n> \tint irq;\n> \n> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n> \t}\n> \n> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n> +\tdata = (unsigned long)of_device_get_match_data(dev);\n> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n> \n> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n> \t\t\t pdev->name, cqspi);\n> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n> #endif\n> \n> static const struct of_device_id cqspi_dt_ids[] = {\n> -\t{.compatible = \"cdns,qspi-nor\",},\n> +\t{\n> +\t\t.compatible = \"cdns,qspi-nor\",\n> +\t\t.data = (void *)0,\n> +\t},\n> +\t{\n> +\t\t.compatible = \"ti,k2g-qspi\",\n> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n> +\t},\n> \t{ /* end of table */ }\n> };\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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\n\tSun, 24 Sep 2017 05:11:53 -0700 (PDT)","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Vignesh R , Cyrille Pitchen ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>","From":"Marek Vasut ","Message-ID":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","Date":"Sun, 24 Sep 2017 13:59:45 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170924105924.23923-3-vigneshr@ti.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_051216_715150_60AD11BD ","X-CRM114-Status":"GOOD ( 19.23 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c09:0:0:0:243 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774158,"web_url":"http://patchwork.ozlabs.org/comment/1774158/","msgid":"<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","list_archive_url":null,"date":"2017-09-24T12:33:51","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 5:29 PM, Marek Vasut wrote:\n> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>> Controller programming sequence, a delay equal to couple of QSPI master\n>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>> to handle this and set this flag for TI 66AK2G SoC.\n>>\n>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>\n>> Signed-off-by: Vignesh R \n> \n> Is this TI specific or is this controller property ? I wouldn't be\n> surprised of the later ...\n\nI am not sure, there is no generic public documentation by cadence for\nthis IP. TI TRM clearly states this delay is required and I have\nverified it practically that this delay is indeed needed.\nBut current user of this IP, socfpga does not seem to mention anything\nabout it. So, I guess its TI specific quirk.\n\n> \n>> ---\n>>\n>> v3:\n>> Fix build warnings reported by kbuild test bot.\n>>\n>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -38,6 +38,9 @@\n>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>> \n>> +/* Quirks */\n>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>> +\n>> struct cqspi_st;\n>> \n>> struct cqspi_flash_pdata {\n>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>> \tu32\t\t\tfifo_depth;\n>> \tu32\t\t\tfifo_width;\n>> \tu32\t\t\ttrigger_address;\n>> +\tu32\t\t\twr_delay;\n>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>> };\n>> \n>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>> \treinit_completion(&cqspi->transfer_complete);\n>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>> +\t/*\n>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>> +\t * Controller programming sequence, couple of cycles of\n>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>> +\t * be internally synchronized by the QSPI module. Provide 5\n>> +\t * cycles of delay.\n>> +\t */\n>> +\tif (cqspi->wr_delay)\n>> +\t\tndelay(cqspi->wr_delay);\n>> \n>> \twhile (remaining > 0) {\n>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \tstruct cqspi_st *cqspi;\n>> \tstruct resource *res;\n>> \tstruct resource *res_ahb;\n>> +\tunsigned long data;\n>> \tint ret;\n>> \tint irq;\n>> \n>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \t}\n>> \n>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>> \n>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>> \t\t\t pdev->name, cqspi);\n>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>> #endif\n>> \n>> static const struct of_device_id cqspi_dt_ids[] = {\n>> -\t{.compatible = \"cdns,qspi-nor\",},\n>> +\t{\n>> +\t\t.compatible = \"cdns,qspi-nor\",\n>> +\t\t.data = (void *)0,\n>> +\t},\n>> +\t{\n>> +\t\t.compatible = \"ti,k2g-qspi\",\n>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>> +\t},\n>> \t{ /* end of table */ }\n>> };\n>> \n>>\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","Content-Language":"en-US","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_053548_664101_D8CE196C ","X-CRM114-Status":"GOOD ( 13.58 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.16 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1774185,"web_url":"http://patchwork.ozlabs.org/comment/1774185/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:13:56","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 02:33 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 5:29 PM, Marek Vasut wrote:\n>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>>> Controller programming sequence, a delay equal to couple of QSPI master\n>>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>>> to handle this and set this flag for TI 66AK2G SoC.\n>>>\n>>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>>\n>>> Signed-off-by: Vignesh R \n>>\n>> Is this TI specific or is this controller property ? I wouldn't be\n>> surprised of the later ...\n> \n> I am not sure, there is no generic public documentation by cadence for\n> this IP. TI TRM clearly states this delay is required and I have\n> verified it practically that this delay is indeed needed.\n> But current user of this IP, socfpga does not seem to mention anything\n> about it. So, I guess its TI specific quirk.\n\nOK, let's go with that then. I didn't observe any stability issues with\nSoCFPGA, but I didn't run the flash at 100s of MHz either. At what kind\nof frequencies does the quirk become relevant ?\n\n>>\n>>> ---\n>>>\n>>> v3:\n>>> Fix build warnings reported by kbuild test bot.\n>>>\n>>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>>\n>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> @@ -38,6 +38,9 @@\n>>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>>> \n>>> +/* Quirks */\n>>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>>> +\n>>> struct cqspi_st;\n>>> \n>>> struct cqspi_flash_pdata {\n>>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>>> \tu32\t\t\tfifo_depth;\n>>> \tu32\t\t\tfifo_width;\n>>> \tu32\t\t\ttrigger_address;\n>>> +\tu32\t\t\twr_delay;\n>>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>>> };\n>>> \n>>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>>> \treinit_completion(&cqspi->transfer_complete);\n>>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>>> +\t/*\n>>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>>> +\t * Controller programming sequence, couple of cycles of\n>>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>>> +\t * be internally synchronized by the QSPI module. Provide 5\n>>> +\t * cycles of delay.\n>>> +\t */\n>>> +\tif (cqspi->wr_delay)\n>>> +\t\tndelay(cqspi->wr_delay);\n>>> \n>>> \twhile (remaining > 0) {\n>>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>>> \tstruct cqspi_st *cqspi;\n>>> \tstruct resource *res;\n>>> \tstruct resource *res_ahb;\n>>> +\tunsigned long data;\n>>> \tint ret;\n>>> \tint irq;\n>>> \n>>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>>> \t}\n>>> \n>>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>>> \n>>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>>> \t\t\t pdev->name, cqspi);\n>>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>>> #endif\n>>> \n>>> static const struct of_device_id cqspi_dt_ids[] = {\n>>> -\t{.compatible = \"cdns,qspi-nor\",},\n>>> +\t{\n>>> +\t\t.compatible = \"cdns,qspi-nor\",\n>>> +\t\t.data = (void *)0,\n>>> +\t},\n>>> +\t{\n>>> +\t\t.compatible = \"ti,k2g-qspi\",\n>>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>>> +\t},\n>>> \t{ /* end of table */ }\n>>> };\n>>> \n>>>\n>>\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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\n\tSun, 24 Sep 2017 06:13:57 -0700 (PDT)","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Vignesh R , Cyrille Pitchen ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>\n\t<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>\n\t<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","From":"Marek Vasut ","Message-ID":"","Date":"Sun, 24 Sep 2017 15:13:56 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_061420_677765_F192154E ","X-CRM114-Status":"GOOD ( 18.85 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c09:0:0:0:244 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (marek.vasut[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring , linux-mtd@lists.infradead.org,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1778301,"web_url":"http://patchwork.ozlabs.org/comment/1778301/","msgid":"<07137a92-244b-e009-54ae-71f733860f28@ti.com>","list_archive_url":null,"date":"2017-10-02T12:46:40","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 6:43 PM, Marek Vasut wrote:\n> On 09/24/2017 02:33 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 5:29 PM, Marek Vasut wrote:\n>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>>>> Controller programming sequence, a delay equal to couple of QSPI master\n>>>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>>>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>>>> to handle this and set this flag for TI 66AK2G SoC.\n>>>>\n>>>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>>>\n>>>> Signed-off-by: Vignesh R \n>>>\n>>> Is this TI specific or is this controller property ? I wouldn't be\n>>> surprised of the later ...\n>>\n>> I am not sure, there is no generic public documentation by cadence for\n>> this IP. TI TRM clearly states this delay is required and I have\n>> verified it practically that this delay is indeed needed.\n>> But current user of this IP, socfpga does not seem to mention anything\n>> about it. So, I guess its TI specific quirk.\n> \n> OK, let's go with that then. I didn't observe any stability issues with\n> SoCFPGA, but I didn't run the flash at 100s of MHz either. At what kind\n> of frequencies does the quirk become relevant ?\n> \n\nActually, delay is tied to QSPI master clk rate(not SPI bus clk rate).\nIt runs at 384MHz. Changing SPI bus rate has no effect.\n\nRegards\nVignesh\n\n>>>\n>>>> ---\n>>>>\n>>>> v3:\n>>>> Fix build warnings reported by kbuild test bot.\n>>>>\n>>>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>>>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>>>\n>>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> @@ -38,6 +38,9 @@\n>>>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>>>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>>>> \n>>>> +/* Quirks */\n>>>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>>>> +\n>>>> struct cqspi_st;\n>>>> \n>>>> struct cqspi_flash_pdata {\n>>>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>>>> \tu32\t\t\tfifo_depth;\n>>>> \tu32\t\t\tfifo_width;\n>>>> \tu32\t\t\ttrigger_address;\n>>>> +\tu32\t\t\twr_delay;\n>>>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>>>> };\n>>>> \n>>>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>>>> \treinit_completion(&cqspi->transfer_complete);\n>>>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>>>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>>>> +\t/*\n>>>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>>>> +\t * Controller programming sequence, couple of cycles of\n>>>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>>>> +\t * be internally synchronized by the QSPI module. Provide 5\n>>>> +\t * cycles of delay.\n>>>> +\t */\n>>>> +\tif (cqspi->wr_delay)\n>>>> +\t\tndelay(cqspi->wr_delay);\n>>>> \n>>>> \twhile (remaining > 0) {\n>>>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>>>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>>>> \tstruct cqspi_st *cqspi;\n>>>> \tstruct resource *res;\n>>>> \tstruct resource *res_ahb;\n>>>> +\tunsigned long data;\n>>>> \tint ret;\n>>>> \tint irq;\n>>>> \n>>>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>>>> \t}\n>>>> \n>>>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>>>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>>>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>>>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>>>> \n>>>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>>>> \t\t\t pdev->name, cqspi);\n>>>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>>>> #endif\n>>>> \n>>>> static const struct of_device_id cqspi_dt_ids[] = {\n>>>> -\t{.compatible = \"cdns,qspi-nor\",},\n>>>> +\t{\n>>>> +\t\t.compatible = \"cdns,qspi-nor\",\n>>>> +\t\t.data = (void *)0,\n>>>> +\t},\n>>>> +\t{\n>>>> +\t\t.compatible = \"ti,k2g-qspi\",\n>>>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>>>> +\t},\n>>>> \t{ /* end of table */ }\n>>>> };\n>>>> \n>>>>\n>>>\n>>>\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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