[{"id":1865285,"web_url":"http://patchwork.ozlabs.org/comment/1865285/","msgid":"","list_archive_url":null,"date":"2018-02-27T22:31:43","subject":"Re: [Qemu-devel] [PATCH v5 2/7] hw/mdio: Add PHY register definition","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Fri, Sep 22, 2017 at 10:13 AM, Philippe Mathieu-Daudé\n wrote:\n> From: Grant Likely \n>\n> Trivial patch to add #defines for defined PHY register address and bit fields\n>\n> Signed-off-by: Grant Likely \n> Signed-off-by: Philippe Mathieu-Daudé \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> include/hw/net/mdio.h | 24 ++++++++++++++++++++++--\n> hw/net/mdio.c | 8 ++++----\n> 2 files changed, 26 insertions(+), 6 deletions(-)\n>\n> diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\n> index ac36aed3c3..7ffa4389b9 100644\n> --- a/include/hw/net/mdio.h\n> +++ b/include/hw/net/mdio.h\n> @@ -25,14 +25,34 @@\n> * THE SOFTWARE.\n> */\n>\n> -/* PHY Advertisement control register */\n> +/* PHY MII Register/Bit Definitions */\n> +/* PHY Registers defined by IEEE */\n> +#define PHY_CTRL 0x00 /* Control Register */\n> +#define PHY_STATUS 0x01 /* Status Regiser */\n> +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */\n> +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */\n> +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */\n> +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */\n> +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */\n> +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */\n> +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */\n> +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */\n> +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */\n> +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */\n> +\n> +#define NUM_PHY_REGS 0x20 /* 5 bit address bus (0-0x1F) */\n> +\n> +#define PHY_CTRL_RST 0x8000 /* PHY reset command */\n> +#define PHY_CTRL_ANEG_RST 0x0200 /* Autonegotiation reset command */\n> +\n> +/* PHY Advertisement control and remote capability registers (same bitfields) */\n> #define PHY_ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\n> #define PHY_ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\n> #define PHY_ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\n> #define PHY_ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\n>\n> struct qemu_phy {\n> - uint32_t regs[32];\n> + uint32_t regs[NUM_PHY_REGS];\n>\n> int link;\n>\n> diff --git a/hw/net/mdio.c b/hw/net/mdio.c\n> index 3763fcc8af..3d70d99077 100644\n> --- a/hw/net/mdio.c\n> +++ b/hw/net/mdio.c\n> @@ -122,12 +122,12 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n>\n> void tdk_init(struct qemu_phy *phy)\n> {\n> - phy->regs[0] = 0x3100;\n> + phy->regs[PHY_CTRL] = 0x3100;\n> /* PHY Id. */\n> - phy->regs[2] = 0x0300;\n> - phy->regs[3] = 0xe400;\n> + phy->regs[PHY_ID1] = 0x0300;\n> + phy->regs[PHY_ID2] = 0xe400;\n> /* Autonegotiation advertisement reg. */\n> - phy->regs[4] = 0x01e1;\n> + phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n> phy->link = 1;\n>\n> phy->read = tdk_read;\n> --\n> 2.14.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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